From 3a83235f914f8d320868a672bfb5901abb94f1a2 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 13 May 2026 15:59:45 +0200 Subject: [PATCH] gowin: Enable driving FF XD from SEL Signed-off-by: gatecat --- himbaechel/uarch/gowin/gowin.cc | 2 +- himbaechel/uarch/gowin/gowin_arch_gen.py | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc index d86bca98..0be082c7 100644 --- a/himbaechel/uarch/gowin/gowin.cc +++ b/himbaechel/uarch/gowin/gowin.cc @@ -1424,7 +1424,7 @@ bool GowinImpl::slice_valid(int x, int y, int z) const } else { src = fast_cell_info.at(alu->flat_index).alu_sum; } - if (ff_data.ff_d != src) { + if (ff_data.ff_d != src && bels.at(mux_z.at(z)) != nullptr) { return false; } } diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py index 2bda0e00..f3a1e40d 100644 --- a/himbaechel/uarch/gowin/gowin_arch_gen.py +++ b/himbaechel/uarch/gowin/gowin_arch_gen.py @@ -1120,10 +1120,9 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT) if i < 6 or "HAS_DFF67" in db.chip_flags: tt.create_pip(f"F{i}", f"XD{i}", get_tm_class(db, f"F{i}")) - # also experimental input for FF using SEL wire - this theory will + # also experimental input for FF using SEL wire - this will # allow to place unrelated LUT and FF next to each other - # don't create for now - #tt.create_pip(f"SEL{i}", f"XD{i}", get_tm_class(db, f"SEL{i}")) + tt.create_pip(f"SEL{i}", f"XD{i}", get_tm_class(db, f"SEL{i}")) # FF ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))