From 210e6c81588689d7cef4dbe0151459d209c88b2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= Date: Wed, 17 Dec 2025 11:53:10 +0100 Subject: [PATCH] gatemate: add missing MULT timing path (#1618) --- himbaechel/uarch/gatemate/delay.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/himbaechel/uarch/gatemate/delay.cc b/himbaechel/uarch/gatemate/delay.cc index cbfcfcfc..3a7a563b 100644 --- a/himbaechel/uarch/gatemate/delay.cc +++ b/himbaechel/uarch/gatemate/delay.cc @@ -120,6 +120,10 @@ bool GateMateImpl::getCellDelay(const CellInfo *cell, IdString fromPort, IdStrin } else if (cell->type.in(id_CPE_MX4)) { return get_delay_from_tmg_db(ctx->idf("timing__MX4A_%s_%s", fromPort.c_str(ctx), toPort.c_str(ctx)), delay); } else if (cell->type.in(id_CPE_MULT)) { + if (toPort == id_CPOUT1) + return get_delay_from_tmg_db(ctx->id("timing_cpout_OUT1"), delay); + if (toPort == id_CPOUT2) + return get_delay_from_tmg_db(ctx->id("timing_cpout_OUT2"), delay); return get_delay_from_tmg_db(ctx->idf("timing__MULT_%s_%s", fromPort.c_str(ctx), toPort.c_str(ctx)), delay); } else if (cell->type.in(id_CPE_FF, id_CPE_LATCH, id_CPE_FF_L, id_CPE_FF_U)) { return false;