diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc
index 813a69ae..0f50b9fe 100644
--- a/himbaechel/uarch/gatemate/bitstream.cc
+++ b/himbaechel/uarch/gatemate/bitstream.cc
@@ -153,6 +153,13 @@ struct BitstreamBackend
     void export_connection(ChipConfig &cc, PipId pip)
     {
         const auto &extra_data = *uarch->pip_extra_data(pip);
+        if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
+            IdString resource = IdString(extra_data.resource);
+            if (resource != IdString()) {
+                auto n = ctx->getPipName(pip);
+                printf("PASS %s %s -> %s\n", n[0].c_str(ctx), n[2].c_str(ctx), n[1].c_str(ctx));
+            }
+        }
         if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_VISIBLE)) {
             IdString name = IdString(extra_data.name);
             CfgLoc loc = get_config_loc(pip.tile);
diff --git a/himbaechel/uarch/gatemate/extra_data.h b/himbaechel/uarch/gatemate/extra_data.h
index bacde2e5..cd11799e 100644
--- a/himbaechel/uarch/gatemate/extra_data.h
+++ b/himbaechel/uarch/gatemate/extra_data.h
@@ -45,6 +45,7 @@ NPNR_PACKED_STRUCT(struct GateMatePipExtraDataPOD {
     uint16_t dummy2;
     uint32_t data;
     uint32_t mask;
+    int32_t resource;
 });
 
 NPNR_PACKED_STRUCT(struct GateMateBelPinConstraintPOD {
diff --git a/himbaechel/uarch/gatemate/gen/arch_gen.py b/himbaechel/uarch/gatemate/gen/arch_gen.py
index 81f2074c..3ca46b0c 100644
--- a/himbaechel/uarch/gatemate/gen/arch_gen.py
+++ b/himbaechel/uarch/gatemate/gen/arch_gen.py
@@ -75,6 +75,7 @@ class PipExtraData(BBAStruct):
     plane: int = 0
     data: int = 0
     mask: int = 0
+    resource: IdString = IdString(0)
 
     def serialise_lists(self, context: str, bba: BBAWriter):
         pass
@@ -89,6 +90,7 @@ class PipExtraData(BBAStruct):
         bba.u16(0)
         bba.u32(self.data)
         bba.u32(self.mask)
+        bba.u32(self.resource.index)
 
 @dataclass
 class BelPinConstraint(BBAStruct):
@@ -314,7 +316,7 @@ def main():
                     plane = int(mux.name[10:12])
                 if mux.name == "CPE.C_SN":
                     mux_flags |= MUX_ROUTING
-                pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(mux.name), mux.bits, mux.value, mux_flags, plane, mux.data, mux.mask)
+                pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(mux.name), mux.bits, mux.value, mux_flags, plane, mux.data, mux.mask, ch.strs.id(mux.resource) if mux.resource else IdString(0))
         if type_name in new_wires:
             for wire in sorted(new_wires[type_name]):
                 delay = wire_delay[wire]