From 097062c5cb5c600e0a4a74937e7bf3a3d336a4a7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 8 Dec 2018 22:49:39 -0800 Subject: [PATCH] Remove pip_to_dst_wire lookup --- xc7/arch.cc | 93 +++++++++++++++++++++++++++++----------------------- xc7/arch.h | 23 ++++++------- xc7/delay.cc | 9 +++-- 3 files changed, 68 insertions(+), 57 deletions(-) diff --git a/xc7/arch.cc b/xc7/arch.cc index 96c574d6..ee8b3f78 100644 --- a/xc7/arch.cc +++ b/xc7/arch.cc @@ -138,8 +138,6 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str const boost::regex re_CLB_I1_6("CLBL[LM]_(L|LL|M)_[A-D]([1-6])"); const boost::regex bufg_i("CLK_BUFG_BUFGCTRL\\d+_I0"); const boost::regex bufg_o("CLK_BUFG_BUFGCTRL\\d+_O"); - const boost::regex int_clk("CLK(_L)?[01]"); - const boost::regex gclk("GCLK_(L_)?B\\d+(_EAST|_WEST)?"); std::unordered_map> delay_lookup; Tilewire currentTilewire; WireId w; @@ -259,57 +257,64 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str const bool clb = boost::starts_with( tileTypeName, "CLB"); // Disable all CLB route-throughs (i.e. LUT in->out, LUT A->AMUX, for now) - arcs.clear(); - const_cast(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone, - false /* inUseTied */, true /*inUseRegular */, - true /* inUseIrregular */, !clb /* inUseRoutethrough */); - auto &pips = wire_to_pips_downhill[w.index]; - pips.reserve(arcs.size()); const bool clk_tile = boost::starts_with(tileTypeName, "CLK"); - const bool int_tile = boost::starts_with(tileTypeName, "INT"); - const bool global_tile = boost::starts_with(tileTypeName, "CLK") || boost::starts_with(tileTypeName, "HCLK") || boost::starts_with(tileTypeName, "CFG"); - if (global_tile) - wire_is_global[w.index] = true; + bool global_tile = false; - for (const auto &a : arcs) { - // Disable BUFG I0 -> O routethrough - if (clk_tile) { - ewi.set(a.getSourceTilewire()); - if (boost::regex_match(ewi.mWireName, bufg_i)) { - ewi.set(a.getSinkTilewire()); - if (boost::regex_match(ewi.mWireName, bufg_o)) - continue; + arcs.clear(); + //const_cast(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone, + // false /* inUseTied */, true /*inUseRegular */, + // true /* inUseIrregular */, !clb /* inUseRoutethrough */); + { + // expand the segment + TilewireVector segment; + const_cast(*ddb).expandSegment(currentTilewire, segment, DDB::eExpandDirectionNone); + // expand all of the arcs + TilewireVector::const_iterator sep = segment.begin(); + TilewireVector::const_iterator see = segment.end(); + while(sep < see) { + // expand the tilewire sinks + const Tilewire& tilewire = *sep++; + + const auto &tileInfo = tiles.getTileInfo(tilewire.getTileIndex()); + const auto &tileTypeName = tiles.getTileTypeName(tileInfo.getTypeIndex()); + global_tile = global_tile || boost::starts_with(tileTypeName, "CLK") || boost::starts_with(tileTypeName, "HCLK") || boost::starts_with(tileTypeName, "CFG"); + + TilewireVector sinks; + const_cast(*ddb).expandTilewireSinks(tilewire, sinks, false /*inUseTied*/, true /*inUseRegular*/, true /*inUseIrregular*/, + !clb /* inUseRoutethrough */); + // rewrite the sinks as arcs + TilewireVector::const_iterator sip = sinks.begin(); + TilewireVector::const_iterator sie = sinks.end(); + while(sip < sie) { + Arc a(tilewire, *sip++); + + // Disable BUFG I0 -> O routethrough + if (clk_tile) { + ewi.set(a.getSourceTilewire()); + if (boost::regex_match(ewi.mWireName, bufg_i)) { + ewi.set(a.getSinkTilewire()); + if (boost::regex_match(ewi.mWireName, bufg_o)) + continue; + } + } + + pips.emplace_back(p); + pip_to_arc.emplace_back(a); + // arc_to_pip.emplace(a, p.index); + ++p.index; } } - // Disable CLK inputs from being driven from the fabric (must be from global clock network) - else if (int_tile) { - ewi.set(a.getSinkTilewire()); - if (boost::regex_match(ewi.mWireName, int_clk)) { - ewi.set(a.getSourceTilewire()); - if (!boost::regex_match(ewi.mWireName, gclk)) - continue; - } - } - pips.emplace_back(p); - pip_to_arc.emplace_back(a); - // arc_to_pip.emplace(a, p.index); - const auto &tw = a.getSinkTilewire(); - pip_to_dst_wire.emplace_back(tilewire_to_wire(tw)); - ++p.index; } pips.shrink_to_fit(); + + if (global_tile) + wire_is_global[w.index] = true; } pip_to_arc.shrink_to_fit(); num_pips = pip_to_arc.size(); - pip_to_dst_wire.reserve(num_pips); - for (const auto &arc : pip_to_arc) { - const auto &tw = arc.getSinkTilewire(); - pip_to_dst_wire.emplace_back(tilewire_to_wire(tw)); - } - height = (int)tiles.getRowCount(); width = (int)tiles.getColCount(); } @@ -685,6 +690,12 @@ IdString Arch::getPipName(PipId pip) const //#endif } +//IdString Arch::getPipType(PipId pip) const +//{ +// NPNR_ASSERT(pip != PipId()); +// return IdString(); +//} + std::vector> Arch::getPipAttrs(PipId pip) const { std::vector> ret; diff --git a/xc7/arch.h b/xc7/arch.h index b3145b6d..f0b48d43 100644 --- a/xc7/arch.h +++ b/xc7/arch.h @@ -321,7 +321,6 @@ struct TorcInfo std::vector> wire_to_pips_downhill; std::vector pip_to_arc; int num_pips; - std::vector pip_to_dst_wire; int width; int height; std::vector wire_is_global; @@ -348,7 +347,6 @@ private: ar & wire_to_pips_downhill; ar & pip_to_arc; ar & num_pips; - ar & pip_to_dst_wire; ar & wire_is_global; ar & tile_to_xy; } @@ -814,15 +812,16 @@ struct Arch : BaseCtx Loc getPipLocation(PipId pip) const { - const auto &arc = torc_info->pip_to_arc[pip.index]; - const auto &tw = arc.getSourceTilewire(); - const auto &tile_info = torc_info->tiles.getTileInfo(tw.getTileIndex()); + //const auto &arc = torc_info->pip_to_arc[pip.index]; + //const auto &tw = arc.getSourceTilewire(); + //const auto &tile_info = torc_info->tiles.getTileInfo(tw.getTileIndex()); - Loc loc; - loc.x = tile_info.getCol(); - loc.y = tile_info.getRow(); - loc.z = 0; - return loc; + //Loc loc; + //loc.x = tile_info.getCol(); + //loc.y = tile_info.getRow(); + //loc.z = 0; + //return loc; + throw; } IdString getPipName(PipId pip) const; @@ -844,7 +843,9 @@ struct Arch : BaseCtx WireId getPipDstWire(PipId pip) const { NPNR_ASSERT(pip != PipId()); - return torc_info->pip_to_dst_wire[pip.index]; + const auto &arc = torc_info->pip_to_arc[pip.index]; + const auto &tw = arc.getSinkTilewire(); + return torc_info->tilewire_to_wire(tw); } DelayInfo getPipDelay(PipId pip) const diff --git a/xc7/delay.cc b/xc7/delay.cc index 1c94d3b6..8b8b0ae7 100644 --- a/xc7/delay.cc +++ b/xc7/delay.cc @@ -105,8 +105,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const const auto &dst_tw = torc_info->wire_to_tilewire[dst.index]; const auto &dst_loc = torc_info->tile_to_xy[dst_tw.getTileIndex()]; - auto abs_delta_x = abs(dst_loc.first - src_loc.first); - if (!torc_info->wire_is_global[src.index] || torc_info->wire_is_global[dst.index]) { + if (!torc_info->wire_is_global[src.index]) { auto abs_delta_x = abs(dst_loc.first - src_loc.first); auto abs_delta_y = abs(dst_loc.second - src_loc.second); auto div_LH = std::div(abs_delta_x, 12); @@ -127,9 +126,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const else { auto src_y = src_loc.second; auto dst_y = dst_loc.second; - dst_y -= (dst_y % 52) - 26; - auto abs_delta_y = abs(src_y - dst_y); - return abs_delta_x + abs_delta_y; + auto div_src_y = std::div(src_y, 52); + auto div_dst_y = std::div(dst_y, 52); + return abs(div_dst_y.quot - div_src_y.quot) * 52 + abs(div_dst_y.rem - div_src_y.rem); } }