diff --git a/VERSION b/VERSION index ef37072..8740e51 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.5.159 +1.5.160 diff --git a/base/verilog.c b/base/verilog.c index c7dd050..b762d6f 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -553,9 +553,43 @@ void CleanupModule() { int maxnode = 0; int has_submodules = FALSE; struct objlist *sobj, *nobj, *lobj, *pobj; + struct objlist *myLastPort, *object_it, *myNextObject; if (CurrentCell == NULL) return; + myLastPort = NULL; + + /* Reorder objects so that all ports come first, before nodes, because + * parts of the code depend on it. + */ + + for (object_it = CurrentCell->cell; object_it && object_it->type <= 0; + object_it = myNextObject ) { + + myNextObject = object_it->next; + if (!myNextObject) // end of list + continue; + + if (myLastPort == NULL) { + if (object_it->type == PORT) { + myLastPort = object_it; // port at begining of list + myNextObject = object_it; // otherwise skips one + } + else if (myNextObject->type == PORT) { + object_it->next = myNextObject->next; + myNextObject->next = CurrentCell->cell; + CurrentCell->cell = myNextObject; + myLastPort = myNextObject; + } + } + else if (myNextObject->type == PORT) { + object_it->next = myNextObject->next; + myNextObject->next = myLastPort->next; + myLastPort->next = myNextObject; + myLastPort = myNextObject; + } + } + for (sobj = CurrentCell->cell; sobj; sobj = sobj->next) if (sobj->node > maxnode) maxnode = sobj->node + 1; @@ -1946,7 +1980,9 @@ nextinst: sprintf(localnet, "_noconnect_%d_", localcount++); Node(localnet); join(localnet, obptr->name); - Fprintf(stderr, "Note: Implicit pin %s\n", obpinname); + Fprintf(stderr, + "Note: Implicit pin %s in instance %s of %s in cell %s\n", + obpinname, locinst, modulename, CurrentCell->name); } else if (GetBus(scan->net, &wb) == 0) { char *bptr2;