From cec6d894743b1da70fe9a272363a8febe473576a Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Tue, 16 Jun 2020 12:52:29 -0400
Subject: [PATCH] Corrected an uninitialized variable error in the verilog
 reading code that produces a segfault condition.

---
 VERSION        | 2 +-
 base/verilog.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/VERSION b/VERSION
index ebc3416..bc47a65 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.5.147
+1.5.148
diff --git a/base/verilog.c b/base/verilog.c
index aba10e4..6b36a93 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -1786,7 +1786,7 @@ nextinst:
 	       // Net is bit-sliced across array of instances.
 
 	       if (wb.start > wb.end) {
-		  char *bptr, *cptr = NULL, cchar, *netname;
+		  char *bptr = NULL, *cptr = NULL, cchar, *netname;
 		  unsigned char is_bundle = 0;
 		  struct bus wbb;