From 88d53fab15eb611cffc024eebf8743fae5cf8cb7 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Sun, 11 Jul 2021 12:06:16 -0400 Subject: [PATCH] Correction to the verilog parser to recognize modifiers such as "~", "!", or "-" in front of variable names in a pin list that would render the module behavioral verilog. --- base/verilog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/base/verilog.c b/base/verilog.c index 92dfbd1..f5ac6b0 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -1577,6 +1577,14 @@ nextinst: } new_port->net = wire_bundle; } + else if (nexttok[0] == '~' || nexttok[0] == '!' || nexttok[0] == '-') { + /* All of these imply that the signal is logically manipulated */ + /* in turn implying behavioral code. */ + Printf("Module '%s' is not structural verilog, " + "making black-box.\n", model); + SetClass(CLASS_MODULE); + goto skip_endmodule; + } else new_port->net = strsave(nexttok);