From 82be18ec4b106d25e03929aa0111349a88d5f61b Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Mon, 3 Aug 2020 22:57:19 -0400
Subject: [PATCH] Corrected a bounds check on sub-arrays inside bundles, that
 prevents the bundle from being parsed correctly when any sub-array is only
 one bit wide.

---
 base/verilog.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/base/verilog.c b/base/verilog.c
index 8d3bcef..c7dd050 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -1867,7 +1867,7 @@ nextinst:
 		     if (is_bundle &&
 			    ((i == -1) ||
 			    ((wbb.start > wbb.end) && (i < wbb.end)) ||
-			    ((wbb.start < wbb.end) && (i > wbb.end)))) {
+			    ((wbb.start <= wbb.end) && (i > wbb.end)))) {
 		         if (bptr) *bptr = '[';
 
 			 netname = cptr + 1;