From 4ee3a1464b46ed81d38fff7672a109c2eda9766f Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Mon, 3 Aug 2020 11:49:09 -0400
Subject: [PATCH] Corrected the left-hand side assignment for "assign"
 statements and corrected the error statement so that it refers both to the
 (corrected) left-hand side and also the portion of the right-hand side that
 cannot be parsed as structural verilog.

---
 VERSION        |  2 +-
 base/verilog.c | 19 ++++++++++++++++---
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/VERSION b/VERSION
index 336a6bc..1fd08a2 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.5.153
+1.5.154
diff --git a/base/verilog.c b/base/verilog.c
index f6f04b0..8d3bcef 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -1225,7 +1225,12 @@ skip_endmodule:
 		    lhs = LookupObject(nodename, CurrentCell);
 		    *aptr = '[';
 		}
-		else strcpy(noderoot, nexttok);
+		else {
+		    strcpy(noderoot, nexttok);
+		    /* Set LHS to the start of the vector */
+		    sprintf(nodename, "%s[%d]", nexttok, wb.start);
+		    lhs = LookupObject(nodename, CurrentCell);
+		}
 	    }
 	    else {
 		lhs = LookupObject(nexttok, CurrentCell);
@@ -1290,13 +1295,21 @@ skip_endmodule:
 			if (rhs != NULL) {
 			    Printf("Improper assignment;  left-hand side cannot "
 					"be parsed.\n");
-			    Printf("Right-hand side is \"%s\".\n", rhs->name);
+			    if (j != -1)
+			    	Printf("Right-hand side is \"%s\".\n", assignroot);
+			    else
+			    	Printf("Right-hand side is \"%s\".\n", rhs->name);
+			    Printf("Improper expression is \"%s\".\n", nexttok);
 			    break;
 			}
 			if (lhs != NULL) {
 			    Printf("Improper assignment;  right-hand side cannot "
 					"be parsed.\n");
-			    Printf("Left-hand side is \"%s\".\n", lhs->name);
+			    if (i != -1)
+			    	Printf("Left-hand side is \"%s\".\n", noderoot);
+			    else
+			    	Printf("Left-hand side is \"%s\".\n", lhs->name);
+			    Printf("Improper expression is \"%s\".\n", nexttok);
 			    /* Not parsable, probably behavioral verilog? */
 			    Printf("Module '%s' is not structural verilog, "
 				    "making black-box.\n", model);