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netgen
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Implemented the patch from Sylvain Munaut in github PR#90 (issue 

that the position in the code has shifted quite a bit and I
don't really trust that git will do a clean merge.
This commit is contained in:
Tim Edwards 2024-11-14 20:39:19 -05:00
parent 7d910b616c
commit 3b9dca0cf2
2 changed files with 10 additions and 1 deletions
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2
VERSION
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@ -1 +1 @@
1.5.286 1.5.287

9
base/verilog.c
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@ -1852,6 +1852,15 @@ skip_endmodule:
} }
else { else {
lhs = LookupObject(nexttok, CurrentCell); lhs = LookupObject(nexttok, CurrentCell);
/* Handle the case in which an assignment is made
* without first declaring a wire for the signal,
* which is considered valid syntax (patch by
* Sylvain Munaut).
*/
if (lhs == NULL) {
Node(nexttok);
lhs = LookupObject(nexttok, CurrentCell);
}
strcpy(noderoot, nexttok); strcpy(noderoot, nexttok);
} }
SkipTokComments(VLOG_DELIMITERS); SkipTokComments(VLOG_DELIMITERS);