From 362fb7120bd9529bc2e0b1f75656717b34bd566f Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Thu, 13 May 2021 15:50:12 -0400 Subject: [PATCH] Modified the behavior of the parallel combination of devices with "similar no connect" pins so that it is not done on top-level netlists. This is mainly to deal with the problem where connections that would normally be pins (but may have, for example, been connected to a voltage source in a schematic that was deleted because it was not a netlistable device) are treated as no-connects. The parallel combination of devices with similar no-connects can then differ between netlists that differ in describing transistors as fingered vs. individual devices. This is an obscure case, but the output of netgen then becomes not only wrong but difficult to understand what happened, so it is better to avoid. --- base/netgen.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/base/netgen.c b/base/netgen.c index c68b62a..590db5d 100644 --- a/base/netgen.c +++ b/base/netgen.c @@ -3166,7 +3166,16 @@ int CombineParallel(char *model, int file) nodecount = (int *)CALLOC((tp->nodename_cache_maxnodenum + 1), sizeof(int)); - if (GlobalParallelOpen) { + /* Do not combine open connections on top level cells. The situation */ + /* where it is meant to optimize run time, namely large digital */ + /* standard cell layouts, will generally have ports and not be run on */ + /* the top level cell, while a small analog circuit might. A */ + /* combination of running on the top level and a difference between */ + /* individual devices in one netlist vs. fingered devices in the */ + /* can cause parallelizing devices with similar "no-connect" pins to */ + /* produce incorrect results. */ + + if (GlobalParallelOpen && !(tp->flags & CELL_TOP)) { for (ob = tp->cell; ob; ob = ob->next) { if (ob->node >= 0) if (ob->type != NODE)