From 3b9dca0cf2fedcb51c91400ad64c03b27c1eb9b9 Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Thu, 14 Nov 2024 20:39:19 -0500
Subject: [PATCH 1/2] Implemented the patch from Sylvain Munaut in github PR#90
 (issue that the position in the code has shifted quite a bit and I don't
 really trust that git will do a clean merge.

---
 VERSION        | 2 +-
 base/verilog.c | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 86e7118..268b24f 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.5.286
+1.5.287
diff --git a/base/verilog.c b/base/verilog.c
index 80d2e03..98f8e86 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -1852,6 +1852,15 @@ skip_endmodule:
 	    }
 	    else {
 		lhs = LookupObject(nexttok, CurrentCell);
+		/* Handle the case in which an assignment is made
+		 * without first declaring a wire for the signal,
+		 * which is considered valid syntax (patch by
+		 * Sylvain Munaut).
+		 */
+		if (lhs == NULL) {
+		    Node(nexttok);
+		    lhs = LookupObject(nexttok, CurrentCell);
+		}
 		strcpy(noderoot, nexttok);
 	    }
 	    SkipTokComments(VLOG_DELIMITERS);

From 49c0de0433b6e5b899b6e7ba99fca262dbd44573 Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Thu, 14 Nov 2024 21:28:51 -0500
Subject: [PATCH 2/2] Corrected an error found by Sylvain Munaut and discussed
 on open-source-silicon slack on Nov. 3 in which the simple verilog expression
 "assign name1 = name2[a:b]";  this revealed an error where the parsing of
 "name2" was being incorrectly run with GetBusTok() which must be called when
 the token starts with "[". This problem existed both for the left-hand-side
 parsing and the right-hand-side parsing, and has been fixed for both (where
 either side may be a subset of a bus and the other a complete bus).

---
 base/verilog.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/base/verilog.c b/base/verilog.c
index 98f8e86..548d274 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -717,10 +717,12 @@ int GetBus(char *astr, struct bus *wb)
     return 0;
 }
 
+//--------------------------------------------------------------------
 // Output a Verilog Module.  Note that since Verilog does not describe
 // low-level devices like transistors, capacitors, etc., then this
 // format is limited to black-box subcircuits.  Cells containing any
 // such low-level devices are ignored.
+//--------------------------------------------------------------------
 
 void VerilogModule(struct nlist *tp)
 {
@@ -1833,8 +1835,9 @@ skip_endmodule:
 	}
 	else {	    /* "assign" */
 	    SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
-	    if (GetBusTok(&wb) == 0) {
-		char *aptr = strvchr(nexttok, '[');
+	    char *aptr = strvchr(nexttok, '[');
+	    if (((aptr == NULL) && (GetBusTok(&wb) == 0)) ||
+			((aptr != NULL) && (GetBus(aptr, &wb) == 0))) {
 		if (aptr != NULL) {
 		    *aptr = '\0';
 		    /* Find object of first net in bus */
@@ -1909,8 +1912,9 @@ skip_endmodule:
 		    break;
 		}
 		else {
-		    if (GetBusTok(&wb2) == 0) {
-			char *aptr = strvchr(nexttok, '[');
+		    char *aptr = strvchr(nexttok, '[');
+		    if (((aptr == NULL) && (GetBusTok(&wb2) == 0)) ||
+				((aptr != NULL) && (GetBus(aptr, &wb2) == 0))) {
 			j = wb2.start;
 			if (aptr != NULL) {
 			    *aptr = '\0';