From cec6d894743b1da70fe9a272363a8febe473576a Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 16 Jun 2020 12:52:29 -0400 Subject: [PATCH 1/3] Corrected an uninitialized variable error in the verilog reading code that produces a segfault condition. --- VERSION | 2 +- base/verilog.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/VERSION b/VERSION index ebc3416..bc47a65 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.5.147 +1.5.148 diff --git a/base/verilog.c b/base/verilog.c index aba10e4..6b36a93 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -1786,7 +1786,7 @@ nextinst: // Net is bit-sliced across array of instances. if (wb.start > wb.end) { - char *bptr, *cptr = NULL, cchar, *netname; + char *bptr = NULL, *cptr = NULL, cchar, *netname; unsigned char is_bundle = 0; struct bus wbb; From 6f81e1d294bbf17186c0a16c146e00878492e683 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 16 Jun 2020 15:56:59 -0400 Subject: [PATCH 2/3] Removed a restriction on the "equate pins" command such that pins are matched on circuits that have no elements. This condition does not necessarily indicate an error, and matching pins has no adverse affect (while refusing to match them certainly can). --- tcltk/tclnetgen.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tcltk/tclnetgen.c b/tcltk/tclnetgen.c index 67ea64f..22dc13f 100644 --- a/tcltk/tclnetgen.c +++ b/tcltk/tclnetgen.c @@ -2982,8 +2982,7 @@ _netcmp_equate(ClientData clientData, else { Fprintf(stdout, "Equate pins: cell %s and/or %s " "has no elements.\n", name1, name2); - Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0)); - return TCL_OK; + /* This is not necessarily an error, so go ahead and match pins. */ } } if (ElementClasses == NULL) { From fb0e1d10b06533a91aa6a02492cf95727ea283e1 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 16 Jun 2020 17:16:30 -0400 Subject: [PATCH 3/3] Added back a correction that did not get made in this code base and so didn't make it into the commit. Handles implicit pins in verilog. --- base/verilog.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/base/verilog.c b/base/verilog.c index 6b36a93..8fa0453 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -1918,11 +1918,15 @@ nextinst: scan = scan->next; } if (scan == NULL) { - Fprintf(stderr, "Error: No match in call for pin %s\n", obpinname); - break; - } + char localnet[100]; - if (GetBus(scan->net, &wb) == 0) { + /* Assume an implicit unconnected pin */ + sprintf(localnet, "_noconnect_%d_", localcount++); + Node(localnet); + join(localnet, obptr->name); + Fprintf(stderr, "Note: Implicit pin %s\n", obpinname); + } + else if (GetBus(scan->net, &wb) == 0) { char *bptr2; char *scanroot; scanroot = strsave(scan->net);