From 079e0ab5d3cf315cc5647e4bf774e2efdaf275c2 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Wed, 14 Nov 2018 19:53:19 -0500 Subject: [PATCH] Corrected an error in the handling of node names in verilog that was accidentally erasing array delimiters from node names, a move that surprisingly has no effect at all on LVS until the cell containing the truncated nodes is flattened, at which point it causes odd and confusing behavior that seems to have nothing to do with node names at all. --- base/verilog.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/base/verilog.c b/base/verilog.c index 4052571..0eaa59e 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -1396,6 +1396,7 @@ skip_endmodule: result = GetBus(scan->net, &wb); if (result == -1) { + /* CHECK: THIS CODE SHOULD BE DELETED, IT IS NOT THE ISSUE */ /* Not bus notation, but check if signal was defined as a bus */ wb.start = wb.end = -1; minnet = maxnet = -1; @@ -1420,7 +1421,6 @@ skip_endmodule: if ((bptr = strchr(bobj->name, '[')) != NULL) { *bptr = '\0'; if (!strcmp(bobj->name, scan->net)) { - *bptr = '['; if (sscanf(bptr + 1, "%d", &testidx) == 1) { if (minnet == -1) { minnet = maxnet = bobj->node; @@ -1436,6 +1436,7 @@ skip_endmodule: } } } + *bptr = '['; } } }