108 lines
3.2 KiB
Python
108 lines
3.2 KiB
Python
from amaranth import *
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from amaranth.sim import Simulator
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from manta.io_core import IOCore
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from manta.utils import *
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from random import randint
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probe0 = Signal(1)
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probe1 = Signal(2)
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probe2 = Signal(8)
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probe3 = Signal(20)
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inputs = [probe0, probe1, probe2, probe3]
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probe4 = Signal(1, reset=1)
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probe5 = Signal(2, reset=2)
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probe6 = Signal(8)
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probe7 = Signal(20, reset=65538)
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outputs = [probe4, probe5, probe6, probe7]
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io_core = IOCore(base_addr=0, interface=None, inputs=inputs, outputs=outputs)
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def pulse_strobe_register():
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strobe_addr = io_core._memory_map["strobe"]["addrs"][0]
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yield from write_register(io_core, strobe_addr, 0)
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yield from write_register(io_core, strobe_addr, 1)
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yield from write_register(io_core, strobe_addr, 0)
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@simulate(io_core)
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def test_input_probe_buffer_initial_value():
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# Verify all input probe buffers initialize to zero
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for i in inputs:
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addrs = io_core._memory_map[i.name]["addrs"]
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for addr in addrs:
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yield from verify_register(io_core, addr, 0)
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@simulate(io_core)
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def test_output_probe_buffer_initial_value():
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# Verify all output probe buffers initialize to the values in the config
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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datas = value_to_words(o.reset, len(addrs))
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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@simulate(io_core)
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def test_output_probes_are_writeable():
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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test_value = randint(0, (2**o.width) - 1)
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datas = value_to_words(test_value, len(addrs))
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# write value to registers
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for addr, data in zip(addrs, datas):
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yield from write_register(io_core, addr, data)
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# read value back from registers
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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@simulate(io_core)
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def test_output_probes_update():
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for o in outputs:
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addrs = io_core._memory_map[o.name]["addrs"]
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test_value = randint(0, (2**o.width) - 1)
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datas = value_to_words(test_value, len(addrs))
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# write value to registers
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for addr, data in zip(addrs, datas):
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yield from write_register(io_core, addr, data)
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# pulse strobe register
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yield from pulse_strobe_register()
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# check that outputs took updated value
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value = yield (o)
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if value != test_value:
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raise ValueError(
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f"Output probe {o.name} took value {value} instead of {test_value} after pulsing strobe."
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)
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else:
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print(f"Output probe {o.name} took value {value} after pulsing strobe.")
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@simulate(io_core)
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def test_input_probes_update():
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for i in inputs:
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# set input probe value
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test_value = randint(0, (2**i.width) - 1)
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yield i.eq(test_value)
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# pulse strobe register
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yield from pulse_strobe_register()
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# check that values are as expected once read back
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addrs = io_core._memory_map[i.name]["addrs"]
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datas = value_to_words(test_value, len(addrs))
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for addr, data in zip(addrs, datas):
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yield from verify_register(io_core, addr, data)
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