38 lines
640 B
Systemverilog
38 lines
640 B
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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module top_level (
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input wire clk,
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input wire uart_txd_in,
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output logic uart_rxd_out
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);
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logic probe0;
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logic [3:0] probe1;
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logic [7:0] probe2;
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logic [15:0] probe3;
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always @(posedge clk) begin
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probe0 <= probe0 + 1;
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probe1 <= probe1 + 1;
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probe2 <= probe2 + 1;
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probe3 <= probe3 + 1;
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end
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manta manta_inst (
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.clk(clk),
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.rst(0),
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.rx(uart_txd_in),
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.tx(uart_rxd_out),
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.probe0(probe0),
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.probe1(probe1),
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.probe2(probe2),
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.probe3(probe3));
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endmodule
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`default_nettype wire
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