From fef4f83c3d488fbba17fa2fd1e1e210902655c91 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Wed, 14 Jan 2026 14:33:36 -0700
Subject: [PATCH] logic_analyzer: fix 100% CPU wait loop in capture function

---
 src/manta/logic_analyzer/fsm.py | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py
index 25d4703..414fdd4 100644
--- a/src/manta/logic_analyzer/fsm.py
+++ b/src/manta/logic_analyzer/fsm.py
@@ -1,3 +1,5 @@
+import time
+
 from amaranth import *
 from amaranth.lib.enum import IntEnum
 
@@ -187,10 +189,17 @@ class LogicAnalyzerFSM(Elaboratable):
         self.registers.set_probe("request_start", 1)
         self.registers.set_probe("request_start", 0)
 
-    def wait_for_capture(self):
+    def wait_for_capture(self, timeout=None):
         # Poll the state machine, and wait for the capture to complete
+
+        start_time = time.monotonic()
         while self.registers.get_probe("state") != States.CAPTURED:
-            pass
+            if timeout is not None and (time.monotonic() - start_time) >= timeout:
+                raise TimeoutError(
+                    f"Capture did not complete within {timeout} seconds!"
+                )
+
+            time.sleep(0.1)
 
     def read_register(self, name):
         return self.registers.get_probe(name)