From fd98003db4525a3de30087a063daed336ea091c4 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 27 Nov 2024 13:40:20 -0800 Subject: [PATCH] meta: add pre-commit, commit changes it makes --- .github/workflows/run_tests.yml | 4 +-- .gitignore | 2 +- .pre-commit-config.yaml | 21 +++++++++++ LICENSE.txt | 2 +- codecov.yml | 2 +- doc/assets/bus_architecture.drawio.svg | 2 +- doc/assets/io_core_architecture.drawio.svg | 2 +- .../logic_analyzer_architecture.drawio.svg | 2 +- doc/assets/memory_architecture.drawio.svg | 18 +++++----- doc/assets/system_architecture.drawio.svg | 4 +-- doc/assets/uart_packets.drawio.svg | 2 +- doc/assets/write_transaction.json5 | 8 ++--- doc/ethernet_interface.md | 6 ++-- doc/getting_started.md | 1 - doc/installation.md | 5 +-- doc/logic_analyzer_core.md | 2 +- doc/memory_core.md | 4 +-- doc/overrides/main.html | 2 +- doc/overrides/outdated.html | 2 +- doc/similar_tools.md | 6 ++-- doc/stylesheets/extra.css | 2 +- doc/uart_interface.md | 4 +-- doc/use_cases.md | 2 +- examples/amaranth/ethernet_io_core.py | 2 +- examples/common/.gitignore | 2 +- examples/common/divider.sv | 2 +- .../verilog/icestick/uart_io_core/.gitignore | 2 +- .../verilog/icestick/uart_io_core/build.sh | 2 +- .../verilog/icestick/uart_io_core/manta.yaml | 2 +- .../icestick/uart_io_core/top_level.sv | 2 +- .../icestick/uart_logic_analyzer/.gitignore | 2 +- .../icestick/uart_logic_analyzer/build.sh | 2 +- .../icestick/uart_logic_analyzer/manta.yaml | 2 +- .../icestick/uart_logic_analyzer/top_level.sv | 2 +- .../ether_logic_analyzer_io_core/.gitignore | 2 +- .../ether_logic_analyzer_io_core/build.sh | 2 +- .../ether_logic_analyzer_io_core/top_level.sv | 2 +- .../top_level.xdc | 1 - .../uart_host_to_fpga_mem/.gitignore | 2 +- .../nexys4_ddr/uart_host_to_fpga_mem/build.sh | 2 +- .../uart_host_to_fpga_mem/manta.yaml | 2 +- .../uart_host_to_fpga_mem/top_level.sv | 2 +- .../uart_host_to_fpga_mem/top_level.xdc | 2 -- .../nexys4_ddr/uart_io_core/.gitignore | 2 +- .../verilog/nexys4_ddr/uart_io_core/build.sh | 2 +- .../nexys4_ddr/uart_io_core/manta.yaml | 2 +- .../nexys4_ddr/uart_io_core/top_level.sv | 2 +- .../nexys4_ddr/uart_io_core/top_level.xdc | 2 -- .../nexys4_ddr/uart_logic_analyzer/.gitignore | 2 +- .../nexys4_ddr/uart_logic_analyzer/build.sh | 2 +- .../nexys4_ddr/uart_logic_analyzer/manta.yaml | 2 +- .../uart_logic_analyzer/top_level.sv | 2 +- .../uart_logic_analyzer/top_level.xdc | 2 -- pyproject.toml | 1 + src/manta/ethernet/__init__.py | 2 +- src/manta/io_core.py | 2 +- src/manta/logic_analyzer/__init__.py | 4 +-- src/manta/logic_analyzer/capture.py | 8 ++--- src/manta/logic_analyzer/playback.py | 2 +- src/manta/memory_core.py | 2 +- src/manta/uart/__init__.py | 36 +++++++++---------- src/manta/utils.py | 8 ++--- test/test_mem_core_sim.py | 2 +- 63 files changed, 123 insertions(+), 108 deletions(-) create mode 100644 .pre-commit-config.yaml diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index 12c74a6..125946b 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -15,7 +15,7 @@ jobs: # Update pip python3 -m pip install -U pip - # omitting the following commmand causes the version of setuptools + # omitting the following command causes the version of setuptools # used by python to get confused, and it doesn't detect the name # or version of the package from pyproject.toml - so the following # workaround is used: @@ -39,4 +39,4 @@ jobs: - name: Upload results to Codecov run: | source venv/bin/activate - python3 -m codecov -t ${{ secrets.CODECOV_TOKEN }} \ No newline at end of file + python3 -m codecov -t ${{ secrets.CODECOV_TOKEN }} diff --git a/.gitignore b/.gitignore index e28f46b..0189552 100644 --- a/.gitignore +++ b/.gitignore @@ -29,4 +29,4 @@ build/ # Yosys/IceStorm files *.asc *.bin -*.json \ No newline at end of file +*.json diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml new file mode 100644 index 0000000..73806dd --- /dev/null +++ b/.pre-commit-config.yaml @@ -0,0 +1,21 @@ +repos: + - repo: https://github.com/pre-commit/pre-commit-hooks + rev: v5.0.0 + hooks: + - id: check-yaml + - id: end-of-file-fixer + - id: trailing-whitespace + - id: check-added-large-files + - id: destroyed-symlinks + + - repo: https://github.com/astral-sh/ruff-pre-commit + rev: v0.8.0 + hooks: + - id: ruff + args: [--select, I, --fix, --exit-non-zero-on-fix] + - id: ruff-format + + - repo: https://github.com/shellcheck-py/shellcheck-py + rev: v0.10.0.1 + hooks: + - id: shellcheck diff --git a/LICENSE.txt b/LICENSE.txt index e72bfdd..f288702 100644 --- a/LICENSE.txt +++ b/LICENSE.txt @@ -671,4 +671,4 @@ into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read -. \ No newline at end of file +. diff --git a/codecov.yml b/codecov.yml index c586b21..e8db153 100644 --- a/codecov.yml +++ b/codecov.yml @@ -1,2 +1,2 @@ ignore: - - "test/" \ No newline at end of file + - "test/" diff --git a/doc/assets/bus_architecture.drawio.svg b/doc/assets/bus_architecture.drawio.svg index 739e2ad..9123168 100644 --- a/doc/assets/bus_architecture.drawio.svg +++ b/doc/assets/bus_architecture.drawio.svg @@ -443,4 +443,4 @@ - \ No newline at end of file + diff --git a/doc/assets/io_core_architecture.drawio.svg b/doc/assets/io_core_architecture.drawio.svg index 65f936d..121e17d 100644 --- a/doc/assets/io_core_architecture.drawio.svg +++ b/doc/assets/io_core_architecture.drawio.svg @@ -394,4 +394,4 @@ - \ No newline at end of file + diff --git a/doc/assets/logic_analyzer_architecture.drawio.svg b/doc/assets/logic_analyzer_architecture.drawio.svg index 8e6f240..1f30832 100644 --- a/doc/assets/logic_analyzer_architecture.drawio.svg +++ b/doc/assets/logic_analyzer_architecture.drawio.svg @@ -775,4 +775,4 @@ - \ No newline at end of file + diff --git a/doc/assets/memory_architecture.drawio.svg b/doc/assets/memory_architecture.drawio.svg index 84c6998..519e446 100644 --- a/doc/assets/memory_architecture.drawio.svg +++ b/doc/assets/memory_architecture.drawio.svg @@ -140,13 +140,13 @@
- dout + doubt
- dout + doubt @@ -300,13 +300,13 @@
- user_dout + user_doubt
- user_dout + user_doubt @@ -372,13 +372,13 @@
- dout + doubt
- dout + doubt @@ -495,13 +495,13 @@
- dout + doubt
- dout + doubt @@ -665,4 +665,4 @@ - \ No newline at end of file + diff --git a/doc/assets/system_architecture.drawio.svg b/doc/assets/system_architecture.drawio.svg index 6e01b9f..cc7b8f7 100644 --- a/doc/assets/system_architecture.drawio.svg +++ b/doc/assets/system_architecture.drawio.svg @@ -331,7 +331,7 @@ - USB-UART Conver... + USB-UART Convert... @@ -344,4 +344,4 @@ - \ No newline at end of file + diff --git a/doc/assets/uart_packets.drawio.svg b/doc/assets/uart_packets.drawio.svg index e3cc3b0..4dad827 100644 --- a/doc/assets/uart_packets.drawio.svg +++ b/doc/assets/uart_packets.drawio.svg @@ -1208,4 +1208,4 @@ - \ No newline at end of file + diff --git a/doc/assets/write_transaction.json5 b/doc/assets/write_transaction.json5 index aab055f..3e00bd3 100644 --- a/doc/assets/write_transaction.json5 +++ b/doc/assets/write_transaction.json5 @@ -2,20 +2,20 @@ signal: [ {name: 'clk', wave: 'p...|....'}, {}, - ['input port', + ['input port', {name: 'addr', wave: 'x3x.|....', data: ['A0']}, {name: 'data', wave: 'x5x.|....', data: ["D0"]}, {name: 'rw', wave: 'x1x.|....'}, - {name: 'valid', wave: '010.|....'}, + {name: 'valid', wave: '010.|....'}, ], {}, {}, - ['output port', + ['output port', {name: 'addr', wave: 'x...|.3x.', data: ['A0']}, {name: 'data', wave: 'x...|.5x.', data: ['D0']}, {name: 'rw', wave: 'x...|.1x.'}, - {name: 'valid', wave: '0...|.10.'}, + {name: 'valid', wave: '0...|.10.'}, ], {}, {}, diff --git a/doc/ethernet_interface.md b/doc/ethernet_interface.md index 749e04a..4ecd765 100644 --- a/doc/ethernet_interface.md +++ b/doc/ethernet_interface.md @@ -1,6 +1,6 @@ ## Overview -For applications where UART is too slow or isn't available, Manta provides the option to run over Ethernet. This is done via UDP, so the FPGA can be anywhere on the same network as the host machine - as opposed to MAC-based Ethernet interfaces, which usually require a point-to-point network connection between the FPGA and the host. Although UDP does not guaruntee reliable, in-order packet delivery, this generally tends to be the case on uncongested networks. In the future, Manta will enforce this at the [application layer](https://github.com/fischermoseley/manta/issues/10). +For applications where UART is too slow or isn't available, Manta provides the option to run over Ethernet. This is done via UDP, so the FPGA can be anywhere on the same network as the host machine - as opposed to MAC-based Ethernet interfaces, which usually require a point-to-point network connection between the FPGA and the host. Although UDP does not guarantee reliable, in-order packet delivery, this generally tends to be the case on uncongested networks. In the future, Manta will enforce this at the [application layer](https://github.com/fischermoseley/manta/issues/10). !!! info "Not every device is supported!" @@ -46,7 +46,7 @@ Inside this configuration, the following parameters may be set: - `udp_port` _(optional)_: The UDP port to communicate over. Defaults to 2001. -Lastly, any additonal arguments provided in the `ethernet` section of the config file will be passed to the LiteEth standalone core generator. As a result, the [examples](https://github.com/enjoy-digital/liteeth/tree/master/examples) provided by LiteEth may be of some service to you if you're bringing up a different FPGA! +Lastly, any additional arguments provided in the `ethernet` section of the config file will be passed to the LiteEth standalone core generator. As a result, the [examples](https://github.com/enjoy-digital/liteeth/tree/master/examples) provided by LiteEth may be of some service to you if you're bringing up a different FPGA! !!! warning "LiteEth doesn't always generate its own `refclk`!" @@ -70,4 +70,4 @@ For more information on the connections between your PHY and FPGA, please refere - set_rmii_phy_io - set_gmii_phy_io - set_rgmii_phy_io - - set_sgmii_phy_io \ No newline at end of file + - set_sgmii_phy_io diff --git a/doc/getting_started.md b/doc/getting_started.md index 0646a01..6353437 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -112,4 +112,3 @@ It’s worth noting that this usage represents a slight departure from typical A This is necessary as the `Manta` object contains both HDL needed for build and methods for operating the cores. Saving the `Manta` instance in the class and re-using it later removes the need to define and configure separate instances when elaborating and operating the cores. Lastly, including `manta` as an instance variable also allows it to be directly accessed from an interpreter, as shown above. This allows for a more interactive debugging session, as the definition of the `operate` method doesn’t have to change when you wish to use Manta’s cores differently. - diff --git a/doc/installation.md b/doc/installation.md index 5b91dae..17fa5de 100644 --- a/doc/installation.md +++ b/doc/installation.md @@ -25,9 +25,10 @@ If you're working on the source, you might want an editable installation with so git clone https://github.com/fischermoseley/manta.git cd manta pip install -e ".[dev]" +pre-commit install ``` -Manta's hardware-in-the-loop tests rely on Amaranth's build system for programming FPGAs, which in turn rely on the open-source `xc3sprog` and `iceprog` tools for programming Xilinx and ice40 devices, respecitvely. If you'd like to run these tests locally, you may need to install these tools and have them available on your `PATH`. +Manta's hardware-in-the-loop tests rely on Amaranth's build system for programming FPGAs, which in turn rely on the open-source `xc3sprog` and `iceprog` tools for programming Xilinx and ice40 devices, respectively. If you'd like to run these tests locally, you may need to install these tools and have them available on your `PATH`. If you're on Linux, you may also need to add a new udev rule to give non-superuser accounts access to any connected FTDI devices. This can be done by making a new file at `/etc/udev/rules.d/99-ftdi-devices.rules`, which contains: @@ -49,4 +50,4 @@ Although optional, it is convenient to add the `manta` executable to your system - macOS/Linux/BSD: `$HOME/.local/bin`, or `path\to\venv\bin` if using a virtual environment. -This also adds any other Python scripts exposed by your installed packages to your PATH. \ No newline at end of file +This also adds any other Python scripts exposed by your installed packages to your PATH. diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index 4f807d0..a82ce98 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -122,4 +122,4 @@ This is useful for two situations in particular: ::: manta.LogicAnalyzerCapture -::: manta.LogicAnalyzerPlayback \ No newline at end of file +::: manta.LogicAnalyzerPlayback diff --git a/doc/memory_core.md b/doc/memory_core.md index fb1a4a7..70fed3b 100644 --- a/doc/memory_core.md +++ b/doc/memory_core.md @@ -9,12 +9,12 @@ Manta won't impose any limit on the width or depth of the memory you instantiate !!! warning "Words update 16 bits at a time!" - Due to the structure of Manta's internal bus, the Memory core only updates 16 bits of a word at a time. For instance, writing a new value to a 33-bit wide memory would update bits 0-15 on one clock cycle, bits 16-31 on another, and bit 32 on another still. Manta makes no guaruntees about the time taken between each of these updates. If this is a problem for your application, consider using an IO Core as a doorbell to signal when the memory is valid, or ping-pong between two Memory Cores. + Due to the structure of Manta's internal bus, the Memory core only updates 16 bits of a word at a time. For instance, writing a new value to a 33-bit wide memory would update bits 0-15 on one clock cycle, bits 16-31 on another, and bit 32 on another still. Manta makes no guarantees about the time taken between each of these updates. If this is a problem for your application, consider using an IO Core as a doorbell to signal when the memory is valid, or ping-pong between two Memory Cores. ## On-Chip Implementation -Manta will make a best-effort attempt to implement the memory in Block RAM, if it is available on the device. This is done by exporting Verilog that synthesis tools should infer as Block RAMs, however this inference is not guarunteed. Depending on your toolchain and the FPGA's architecture, the Verilog produced by Manta may be implemented as FF RAM, LUT (Distributed) RAM, or something else. These memory types are well explained in the [Yosys documentation](https://yosyshq.readthedocs.io/projects/yosys/en/latest/using_yosys/synthesis/memory.html), but be sure to check your toolchain's documentation as well. +Manta will make a best-effort attempt to implement the memory in Block RAM, if it is available on the device. This is done by exporting Verilog that synthesis tools should infer as Block RAMs, however this inference is not guaranteed. Depending on your toolchain and the FPGA's architecture, the Verilog produced by Manta may be implemented as FF RAM, LUT (Distributed) RAM, or something else. These memory types are well explained in the [Yosys documentation](https://yosyshq.readthedocs.io/projects/yosys/en/latest/using_yosys/synthesis/memory.html), but be sure to check your toolchain's documentation as well. ## Configuration diff --git a/doc/overrides/main.html b/doc/overrides/main.html index 35591d6..0af326a 100644 --- a/doc/overrides/main.html +++ b/doc/overrides/main.html @@ -5,4 +5,4 @@ Click here to go to latest. -{% endblock %} \ No newline at end of file +{% endblock %} diff --git a/doc/overrides/outdated.html b/doc/overrides/outdated.html index 35591d6..0af326a 100644 --- a/doc/overrides/outdated.html +++ b/doc/overrides/outdated.html @@ -5,4 +5,4 @@ Click here to go to latest. -{% endblock %} \ No newline at end of file +{% endblock %} diff --git a/doc/similar_tools.md b/doc/similar_tools.md index 9de9f3c..22df92c 100644 --- a/doc/similar_tools.md +++ b/doc/similar_tools.md @@ -15,7 +15,7 @@ An embedded logic analyzer written in Migen, primarily for use in LiteX SoC desi ### GateMate ILA -An embedded logic analyzer written in Verilog, targeting the GateMate FPGA family from Colonge Chip and the Yosys/NextPNR toolchain. Communication between the host and FPGA is accomplished with SPI, via a FT232 or FT2232 used as a USB-SPI adapter. GateMate is inteneded to be used with GTKWave, so the tool generates `.gtkw` files in addition to VCD files. +An embedded logic analyzer written in Verilog, targeting the GateMate FPGA family from Cologne Chip and the Yosys/NextPNR toolchain. Communication between the host and FPGA is accomplished with SPI, via a FT232 or FT2232 used as a USB-SPI adapter. GateMate is intended to be used with GTKWave, so the tool generates `.gtkw` files in addition to VCD files. - [Source Code](https://github.com/colognechip/gatemate_ila) @@ -28,7 +28,7 @@ A set of embedded debugging modules written by Dan Gisselquist of ZipCPU fame. C ## Commercial Tools -### Xilinx Integrated Logic Analzyer +### Xilinx Integrated Logic Analyzer An embedded logic analyzer for Xilinx FPGAs, provided as part of the Xilinx Vivado development suite. Communication between the host and FPGA is accomplished with JTAG, typically running over a USB cable to the device. Includes an integrated waveform viewer, and VCD and CSV export. Also supports a JTAG-to-AXI mode, which integrates well with Xilinx IP, which uses primarily AXI. Also integrates with the ChipScoPy API, which allows for Python control of the ILA on Versal devices. The ILA was previously known as ChipScope in earlier versions of Vivado. @@ -75,4 +75,4 @@ Unlike other entries in this list, Opal Kelly's FrontPanel SDK is not marketed a An embedded logic analyzer for Xilinx and Altera FPGAs, provided as part of MATLAB. Communication between the host and FPGA is accomplished with JTAG, but Ethernet is supported for Xilinx FPGAs. Notably, this tool allows for data to be captured and used directly inside MATLAB, which also includes a framework for FPGA-in-the-loop testing. It also provides an AXI manager IP block that allows for reads and writes to an AXI memory map from MATLAB. This IP supports PCI Express on Xilinx FPGAs, in addition to JTAG and Ethernet. -- [Documentation](https://www.mathworks.com/help/hdlverifier/fpga-data-capture-xilinx.html) \ No newline at end of file +- [Documentation](https://www.mathworks.com/help/hdlverifier/fpga-data-capture-xilinx.html) diff --git a/doc/stylesheets/extra.css b/doc/stylesheets/extra.css index 95b68bf..cc76681 100644 --- a/doc/stylesheets/extra.css +++ b/doc/stylesheets/extra.css @@ -1,3 +1,3 @@ :root { --md-primary-fg-color: #3499f3; - } \ No newline at end of file + } diff --git a/doc/uart_interface.md b/doc/uart_interface.md index ba40b5c..3ab3d31 100644 --- a/doc/uart_interface.md +++ b/doc/uart_interface.md @@ -24,7 +24,7 @@ Inside this configuration, the following parameters may be set: - `baudrate` _(required)_: The baudrate of the serial port. Generally, this should be set to the maximum baudrate supported by the USB/UART chip on your dev board for fastest operation. Manta will throw an error if this baudrate is not achievable with your FPGA's clock frequency. -- `clock_freq` _(required)_: The frequency of the clock provided to the `manta` module, in Hertz (Hz). This is used to calculate an appropriate prescaler onboard the FPGA to acheive the desired baudrate. Manta will throw an error if this clock frequency does not allow you to achieve your desired baudrate. +- `clock_freq` _(required)_: The frequency of the clock provided to the `manta` module, in Hertz (Hz). This is used to calculate an appropriate prescaler onboard the FPGA to achieve the desired baudrate. Manta will throw an error if this clock frequency does not allow you to achieve your desired baudrate. - `stall_interval` _(optional)_: The number of read requests to send before sending a stall byte. This prevents packets from being dropped if the FPGA's baudrate is less than the USB-Serial adapter's baudrate. This is usually caused by a mismatch between the clock frequency of the USB-Serial adapter and the FPGA fabric. See issue [#18](https://github.com/fischermoseley/manta/issues/18) on GitHub. Defaults to 16, reduce this if Manta reports that bytes are being dropped. @@ -36,4 +36,4 @@ Since Amaranth modules are Python objects, the configuration of the IO Core is g ::: manta.UARTInterface options: - members: false \ No newline at end of file + members: false diff --git a/doc/use_cases.md b/doc/use_cases.md index eae6c73..48c7ac8 100644 --- a/doc/use_cases.md +++ b/doc/use_cases.md @@ -16,7 +16,7 @@ You may find this core useful for: _More details available on the [full documentation page](./io_core.md)._ -This core presents a series of user-accessbile registers to the FPGA fabric, which may be configured as either inputs or outputs. The value of an input register can be read off the FPGA by the host machine, and the value of an output register on the FPGA may be set by the host machine. This is handy for getting small amounts of information into and out of the FPGA, debugging, configuration, or experimentation. This concept is very similar to the Xilinx [Virtual IO](https://docs.xilinx.com/v/u/en-US/pg159-vio) and Intel [In-System Sources and Probes](https://www.intel.com/content/www/us/en/docs/programmable/683552/18-1/in-system-sources-and-probes-66964.html) tools. +This core presents a series of user-accessible registers to the FPGA fabric, which may be configured as either inputs or outputs. The value of an input register can be read off the FPGA by the host machine, and the value of an output register on the FPGA may be set by the host machine. This is handy for getting small amounts of information into and out of the FPGA, debugging, configuration, or experimentation. This concept is very similar to the Xilinx [Virtual IO](https://docs.xilinx.com/v/u/en-US/pg159-vio) and Intel [In-System Sources and Probes](https://www.intel.com/content/www/us/en/docs/programmable/683552/18-1/in-system-sources-and-probes-66964.html) tools. You may find this core useful for: diff --git a/examples/amaranth/ethernet_io_core.py b/examples/amaranth/ethernet_io_core.py index 868049c..9e2ab2f 100644 --- a/examples/amaranth/ethernet_io_core.py +++ b/examples/amaranth/ethernet_io_core.py @@ -107,7 +107,7 @@ class EthernetIOCoreExample(Elaboratable): # Although Amaranth provides an environment that is almost entirely independent -# of FPGA vendor or family, it does not provide any facilites for clock +# of FPGA vendor or family, it does not provide any facilities for clock # generation. As a result, this example design includes an external Verilog # snippet containing a clock generator created by Vivado's Clock Wizard. # This uses a MMCM clock generation primitive to make a 50MHz clock from the diff --git a/examples/common/.gitignore b/examples/common/.gitignore index c54b99a..8365015 100644 --- a/examples/common/.gitignore +++ b/examples/common/.gitignore @@ -1 +1 @@ -!divider.sv \ No newline at end of file +!divider.sv diff --git a/examples/common/divider.sv b/examples/common/divider.sv index f6ade06..400c145 100644 --- a/examples/common/divider.sv +++ b/examples/common/divider.sv @@ -190,4 +190,4 @@ wire clk_in2_divider; endmodule -`default_nettype none \ No newline at end of file +`default_nettype none diff --git a/examples/verilog/icestick/uart_io_core/.gitignore b/examples/verilog/icestick/uart_io_core/.gitignore index a670a87..1e11c14 100644 --- a/examples/verilog/icestick/uart_io_core/.gitignore +++ b/examples/verilog/icestick/uart_io_core/.gitignore @@ -1 +1 @@ -!top_level.sv \ No newline at end of file +!top_level.sv diff --git a/examples/verilog/icestick/uart_io_core/build.sh b/examples/verilog/icestick/uart_io_core/build.sh index bce3a33..78b10b9 100755 --- a/examples/verilog/icestick/uart_io_core/build.sh +++ b/examples/verilog/icestick/uart_io_core/build.sh @@ -4,4 +4,4 @@ set -e python3 -m manta gen manta.yaml manta.v $YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv $NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc -$ICEPACK top_level.asc top_level.bin \ No newline at end of file +$ICEPACK top_level.asc top_level.bin diff --git a/examples/verilog/icestick/uart_io_core/manta.yaml b/examples/verilog/icestick/uart_io_core/manta.yaml index 162311e..d957e31 100644 --- a/examples/verilog/icestick/uart_io_core/manta.yaml +++ b/examples/verilog/icestick/uart_io_core/manta.yaml @@ -13,4 +13,4 @@ cores: uart: port: "/dev/ttyUSB3" baudrate: 115200 - clock_freq: 12000000 \ No newline at end of file + clock_freq: 12000000 diff --git a/examples/verilog/icestick/uart_io_core/top_level.sv b/examples/verilog/icestick/uart_io_core/top_level.sv index f0740f1..1d7d13b 100644 --- a/examples/verilog/icestick/uart_io_core/top_level.sv +++ b/examples/verilog/icestick/uart_io_core/top_level.sv @@ -30,4 +30,4 @@ module top_level ( .LED4(LED4)); endmodule -`default_nettype wire \ No newline at end of file +`default_nettype wire diff --git a/examples/verilog/icestick/uart_logic_analyzer/.gitignore b/examples/verilog/icestick/uart_logic_analyzer/.gitignore index a670a87..1e11c14 100644 --- a/examples/verilog/icestick/uart_logic_analyzer/.gitignore +++ b/examples/verilog/icestick/uart_logic_analyzer/.gitignore @@ -1 +1 @@ -!top_level.sv \ No newline at end of file +!top_level.sv diff --git a/examples/verilog/icestick/uart_logic_analyzer/build.sh b/examples/verilog/icestick/uart_logic_analyzer/build.sh index bce3a33..78b10b9 100755 --- a/examples/verilog/icestick/uart_logic_analyzer/build.sh +++ b/examples/verilog/icestick/uart_logic_analyzer/build.sh @@ -4,4 +4,4 @@ set -e python3 -m manta gen manta.yaml manta.v $YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv $NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc -$ICEPACK top_level.asc top_level.bin \ No newline at end of file +$ICEPACK top_level.asc top_level.bin diff --git a/examples/verilog/icestick/uart_logic_analyzer/manta.yaml b/examples/verilog/icestick/uart_logic_analyzer/manta.yaml index a6be86c..af3d95d 100644 --- a/examples/verilog/icestick/uart_logic_analyzer/manta.yaml +++ b/examples/verilog/icestick/uart_logic_analyzer/manta.yaml @@ -17,4 +17,4 @@ cores: uart: port: "/dev/ttyUSB3" baudrate: 115200 - clock_freq: 12000000 \ No newline at end of file + clock_freq: 12000000 diff --git a/examples/verilog/icestick/uart_logic_analyzer/top_level.sv b/examples/verilog/icestick/uart_logic_analyzer/top_level.sv index dd40f96..3895af7 100644 --- a/examples/verilog/icestick/uart_logic_analyzer/top_level.sv +++ b/examples/verilog/icestick/uart_logic_analyzer/top_level.sv @@ -32,4 +32,4 @@ module top_level ( .probe3(probe3)); endmodule -`default_nettype wire \ No newline at end of file +`default_nettype wire diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore index f6ca93a..0245c4b 100644 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore +++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore @@ -1,2 +1,2 @@ !top_level.sv -!divider.sv \ No newline at end of file +!divider.sv diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh index 6cbe4aa..591adda 100755 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh +++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh @@ -3,4 +3,4 @@ set -e python3 -m manta gen manta.yaml manta.v mkdir -p build/ -$VIVADO -mode batch -source build.tcl \ No newline at end of file +$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.sv b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.sv index c38deb8..751b36d 100644 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.sv +++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.sv @@ -51,4 +51,4 @@ manta manta_inst( .led(led), .sw(sw)); -endmodule \ No newline at end of file +endmodule diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.xdc b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.xdc index e2ad6f3..0c0c2b9 100644 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.xdc +++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/top_level.xdc @@ -257,4 +257,3 @@ set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_in #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] #set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore index a670a87..1e11c14 100644 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore +++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore @@ -1 +1 @@ -!top_level.sv \ No newline at end of file +!top_level.sv diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh index 6cbe4aa..591adda 100755 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh +++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh @@ -3,4 +3,4 @@ set -e python3 -m manta gen manta.yaml manta.v mkdir -p build/ -$VIVADO -mode batch -source build.tcl \ No newline at end of file +$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml index 382458c..6bb32d6 100644 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml +++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml @@ -9,4 +9,4 @@ cores: uart: port: "/dev/ttyUSB1" baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file + clock_freq: 100000000 diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.sv b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.sv index 7272c36..173217a 100644 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.sv +++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.sv @@ -20,4 +20,4 @@ module top_level ( endmodule -`default_nettype wire \ No newline at end of file +`default_nettype wire diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.xdc b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.xdc index 2dbee5f..69f5762 100644 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.xdc +++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/top_level.xdc @@ -250,5 +250,3 @@ set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_r #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] #set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/verilog/nexys4_ddr/uart_io_core/.gitignore b/examples/verilog/nexys4_ddr/uart_io_core/.gitignore index a670a87..1e11c14 100644 --- a/examples/verilog/nexys4_ddr/uart_io_core/.gitignore +++ b/examples/verilog/nexys4_ddr/uart_io_core/.gitignore @@ -1 +1 @@ -!top_level.sv \ No newline at end of file +!top_level.sv diff --git a/examples/verilog/nexys4_ddr/uart_io_core/build.sh b/examples/verilog/nexys4_ddr/uart_io_core/build.sh index 6cbe4aa..591adda 100755 --- a/examples/verilog/nexys4_ddr/uart_io_core/build.sh +++ b/examples/verilog/nexys4_ddr/uart_io_core/build.sh @@ -3,4 +3,4 @@ set -e python3 -m manta gen manta.yaml manta.v mkdir -p build/ -$VIVADO -mode batch -source build.tcl \ No newline at end of file +$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml b/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml index b924fb3..e179440 100644 --- a/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml +++ b/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml @@ -23,4 +23,4 @@ cores: uart: port: "/dev/ttyUSB1" baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file + clock_freq: 100000000 diff --git a/examples/verilog/nexys4_ddr/uart_io_core/top_level.sv b/examples/verilog/nexys4_ddr/uart_io_core/top_level.sv index a005530..e891750 100644 --- a/examples/verilog/nexys4_ddr/uart_io_core/top_level.sv +++ b/examples/verilog/nexys4_ddr/uart_io_core/top_level.sv @@ -46,4 +46,4 @@ module top_level ( endmodule -`default_nettype wire \ No newline at end of file +`default_nettype wire diff --git a/examples/verilog/nexys4_ddr/uart_io_core/top_level.xdc b/examples/verilog/nexys4_ddr/uart_io_core/top_level.xdc index 695ff17..6237da3 100644 --- a/examples/verilog/nexys4_ddr/uart_io_core/top_level.xdc +++ b/examples/verilog/nexys4_ddr/uart_io_core/top_level.xdc @@ -250,5 +250,3 @@ set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_r #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] #set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore b/examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore index a670a87..1e11c14 100644 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore +++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore @@ -1 +1 @@ -!top_level.sv \ No newline at end of file +!top_level.sv diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh index 6cbe4aa..591adda 100755 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh +++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh @@ -3,4 +3,4 @@ set -e python3 -m manta gen manta.yaml manta.v mkdir -p build/ -$VIVADO -mode batch -source build.tcl \ No newline at end of file +$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml b/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml index 908e47f..093613d 100644 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml +++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml @@ -17,4 +17,4 @@ cores: uart: port: "/dev/ttyUSB1" baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file + clock_freq: 100000000 diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.sv b/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.sv index b79f36b..ca2259e 100644 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.sv +++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.sv @@ -34,4 +34,4 @@ module top_level ( endmodule -`default_nettype wire \ No newline at end of file +`default_nettype wire diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.xdc b/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.xdc index f234e47..3c62139 100644 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.xdc +++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/top_level.xdc @@ -250,5 +250,3 @@ set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_da #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] #set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/pyproject.toml b/pyproject.toml index c3bfa7f..cb03c64 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -21,6 +21,7 @@ dev = [ "pytest", "pytest-cov", "codecov", + "pre-commit", "ruff", "mkdocs-material", "mkdocstrings[python]", diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index f97565a..fd6cc63 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -275,7 +275,7 @@ class EthernetInterface(Elaboratable): mii_mdio (IOPort): Management Data mii_mdc (IOPort): Management Data Clock mii_rx_dv (IOPort): Receive Data Valid - mii_rx_er (IOPort): Recieve Error + mii_rx_er (IOPort): Receive Error mii_rx_data (IOPort): Receive Data mii_tx_en (IOPort): Transmit Enable mii_tx_data (IOPort): Transmit Data diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 6ff4298..fcb0d7e 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -171,7 +171,7 @@ class IOCore(MantaCore): # Save the last used address, for use later. # Normally we'd just grab this from self._memory_map, but Python - # dictionaries don't guaruntee that insertion order is preserved, + # dictionaries don't guarantee that insertion order is preserved, # so it's more convenient to just save it now. self._max_addr = last_used_addr diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index c337583..7f3f985 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -234,7 +234,7 @@ class LogicAnalyzerCore(MantaCore): else: raise ValueError(f"Unrecognized trigger mode {trigger_mode} provided.") - # Peform checks based on trigger mode + # Perform checks based on trigger mode if mode == TriggerModes.IMMEDIATE: # Warn on triggers if triggers: @@ -311,7 +311,7 @@ class LogicAnalyzerCore(MantaCore): raw_capture = self._sample_mem.read(addrs) # Revolve the memory around the read_pointer, such that all the beginning - # of the caputure is at the first element + # of the capture is at the first element print(" -> Checking read pointer and revolving memory...") read_pointer = self._fsm.read_register("read_pointer") diff --git a/src/manta/logic_analyzer/capture.py b/src/manta/logic_analyzer/capture.py index d112ff3..fcd2615 100644 --- a/src/manta/logic_analyzer/capture.py +++ b/src/manta/logic_analyzer/capture.py @@ -45,16 +45,16 @@ class LogicAnalyzerCapture: """ # Get index of probe with given name - indicies = [i for i, p in enumerate(self._probes) if p.name == name] - if len(indicies) == 0: + indices = [i for i, p in enumerate(self._probes) if p.name == name] + if len(indices) == 0: raise ValueError(f"Probe {name} not found in LogicAnalyzerCapture!") - if len(indicies) > 1: + if len(indices) > 1: raise ValueError( f"Probe {name} found multiple times in LogicAnalyzerCapture!" ) - idx = indicies[0] + idx = indices[0] # Sum up the widths of all the probes below this one lower = sum([len(p) for p in self._probes[:idx]]) diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index 939c9c4..9392a50 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -46,7 +46,7 @@ class LogicAnalyzerPlayback(Elaboratable): with m.Else(): m.d.sync += read_port.addr.eq(read_port.addr + 1) - # Pipeline to accomodate for the 2-cycle latency in the RAM + # Pipeline to accommodate for the 2-cycle latency in the RAM m.d.sync += self.valid.eq(busy) # Assign the probe values by part-selecting from the data port diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index c66d2aa..5a2ca89 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -238,7 +238,7 @@ class MemoryCore(MantaCore): for i, mem in enumerate(self._mems): m.submodules[f"mem_{i}"] = mem - # Pipeline the bus to accomodate the two clock-cycle delay in the memories + # Pipeline the bus to accommodate the two clock-cycle delay in the memories self._bus_pipe = [Signal(InternalBus()) for _ in range(3)] m.d.sync += self._bus_pipe[0].eq(self.bus_i) diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index 7ed01d1..b983537 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -34,7 +34,7 @@ class UARTInterface(Elaboratable): clock_freq (float | int): The frequency of the clock provided to this module, in Hertz (Hz). This is used to calculate an - appropriate prescaler onboard the FPGA to acheive the desired + appropriate prescaler onboard the FPGA to achieve the desired baudrate. stall_interval (Optional[int]): The number of read requests to send @@ -53,7 +53,7 @@ class UARTInterface(Elaboratable): did not work. Raises: - ValueError: The baudrate is not acheivable with the clock frequency + ValueError: The baudrate is not achievable with the clock frequency provided, or the clock frequency or baudrate is invalid. """ @@ -213,9 +213,9 @@ class UARTInterface(Elaboratable): # buffer from overflowing and dropping bytes, as the FPGA will send # responses instantly after it's received a request. - ser = self._get_serial_device() + set = self._get_serial_device() addr_chunks = split_into_chunks(addrs, self._chunk_size) - datas = [] + data = [] for addr_chunk in addr_chunks: # Encode addrs into read requests @@ -226,11 +226,11 @@ class UARTInterface(Elaboratable): bytes_out = split_into_chunks(bytes_out, 7 * self._stall_interval) bytes_out = "\n".join(bytes_out) - ser.write(bytes_out.encode("ascii")) + set.write(bytes_out.encode("ascii")) # Read responses have the same length as read requests bytes_expected = 7 * len(addr_chunk) - bytes_in = ser.read(bytes_expected) + bytes_in = set.read(bytes_expected) if len(bytes_in) != bytes_expected: raise ValueError( @@ -240,11 +240,11 @@ class UARTInterface(Elaboratable): # Split received bytes into individual responses and decode responses = split_into_chunks(bytes_in, 7) data_chunk = [self._decode_read_response(r) for r in responses] - datas += data_chunk + data += data_chunk - return datas + return data - def write(self, addrs, datas): + def write(self, addrs, data): """ Write the provided data into the provided addresses in Manta's internal memory. Addresses and data must be specified as either integers or a @@ -252,11 +252,11 @@ class UARTInterface(Elaboratable): """ # Handle a single integer address and data - if isinstance(addrs, int) and isinstance(datas, int): - return self.write([addrs], [datas]) + if isinstance(addrs, int) and isinstance(data, int): + return self.write([addrs], [data]) - # Make sure address and datas are all integers - if not isinstance(addrs, list) or not isinstance(datas, list): + # Make sure address and data are all integers + if not isinstance(addrs, list) or not isinstance(data, list): raise TypeError( "Write addresses and data must be an integer or list of integers." ) @@ -264,17 +264,17 @@ class UARTInterface(Elaboratable): if not all(isinstance(a, int) for a in addrs): raise TypeError("Write addresses must be all be integers.") - if not all(isinstance(d, int) for d in datas): + if not all(isinstance(d, int) for d in data): raise TypeError("Write data must all be integers.") # Since the FPGA doesn't issue any responses to write requests, we # the host's input buffer isn't written to, and we don't need to # send the data as chunks as the to avoid overflowing the input buffer. - # Encode addrs and datas into write requests - bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, datas)]) - ser = self._get_serial_device() - ser.write(bytes_out.encode("ascii")) + # Encode addrs and data into write requests + bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, data)]) + set = self._get_serial_device() + set.write(bytes_out.encode("ascii")) def _decode_read_response(self, response_bytes): """ diff --git a/src/manta/utils.py b/src/manta/utils.py index 0cb891b..26ec5d6 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -10,7 +10,7 @@ from amaranth.sim import Simulator class MantaCore(ABC, Elaboratable): # These attributes are meant to be settable and gettable, but max_addr and - # top_level_ports are indended to be only gettable. Do not implement + # top_level_ports are intended to be only gettable. Do not implement # setters for them in subclasses. base_addr = None @@ -139,7 +139,7 @@ def value_to_words(data, n_words): def check_value_fits_in_bits(value, n_bits): """ - Rasies an exception if the provided value isn't an integer that cannot + Raises an exception if the provided value isn't an integer that cannot be expressed with the provided number of bits. """ @@ -200,7 +200,7 @@ def simulate(top): def jumble(iterable): """ Returns the provided iterable, but with every element moved to a random - index. Very similar to random.shuffle, but returns an iteratable, instead + index. Very similar to random.shuffle, but returns an iterable, instead of modifying one in-place. """ return sample(iterable, len(iterable)) @@ -213,7 +213,7 @@ async def verify_register(module, ctx, addr, expected_data): Unfortunately because Amaranth uses generator functions to define processes, this must be a generator function and thus cannot return a value - it must - yield the next timestep. This means that the comparision with the expected + yield the next timestep. This means that the comparison with the expected value must occur inside this function and not somewhere else, it's not possible to return a value from here, and compare it in the calling function. diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 8e5c2d5..05b36bd 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -134,7 +134,7 @@ class MemoryCoreTests: async def one_bus_write_then_one_user_read(self): for user_addr in self.user_addrs: # Try and set the value at the user address to a given value, - # by writing to the appropriate memory locaitons on the bus side + # by writing to the appropriate memory locations on the bus side data = getrandbits(self.width) words = value_to_words(data, self.n_mems)