From fbaf93b110216c258864b1e90f6f52cc975da846 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Sun, 7 Jan 2024 18:54:33 -0800
Subject: [PATCH] fix typo introduced during refactor

---
 src/manta/logic_analyzer/trigger_block.py | 4 ++--
 src/manta/utils.py                        | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py
index 191b5d1..50f3496 100644
--- a/src/manta/logic_analyzer/trigger_block.py
+++ b/src/manta/logic_analyzer/trigger_block.py
@@ -18,8 +18,8 @@ class LogicAnalyzerTriggerBlock(Elaboratable):
         self.r = IOCore({"outputs": outputs}, base_addr, interface)
 
         # Bus Input/Output
-        self.bus_i = Signal(InternalBus())
-        self.bus_o = Signal(InternalBus())
+        self.bus_i = self.r.bus_i
+        self.bus_o = self.r.bus_o
 
         # Global trigger. High if any probe is triggered.
         self.trig = Signal(1)
diff --git a/src/manta/utils.py b/src/manta/utils.py
index 6ce9316..9c41948 100644
--- a/src/manta/utils.py
+++ b/src/manta/utils.py
@@ -4,6 +4,9 @@ from math import ceil
 import os
 
 class InternalBus(data.StructLayout):
+    """Describes the layout of Manta's internal bus, such that signals of
+    the appropriate dimension can be instantiated with Signal(InternalBus()).
+    """
     def __init__(self):
         super().__init__({
             "addr": 16,