From f8690176e7a12b9f29ad7a0a818562b977ad2ebb Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 28 Mar 2026 18:18:48 -0600 Subject: [PATCH] mem_core: update tests for 32-bit data words --- test/test_mem_core_sim.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 05d7a7b..ba04eab 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -14,8 +14,8 @@ class MemoryCoreTests: self.max_addr = mem_core.max_addr self.width = self.mem_core._width self.depth = self.mem_core._depth - self.n_full = self.width // 16 - self.n_mems = ceil(self.width / 16) + self.n_full = self.width // 32 + self.n_mems = ceil(self.width / 32) self.bus_addrs = list(range(self.base_addr, self.max_addr)) # include the endpoint! self.user_addrs = list(range(self.mem_core._depth)) @@ -201,13 +201,13 @@ class MemoryCoreTests: def get_data_width(self, addr): # this part is a little hard to check since we might have a # memory at the end of the address space that's less than - # 16-bits wide. so we'll have to calculate how wide our + # 32-bits wide. so we'll have to calculate how wide our # memory is if addr < self.base_addr + (self.n_full * self.depth): - return 16 + return 32 else: - return self.width % 16 + return self.width % 32 async def verify_bus_side(self, addr): await verify_register(self.mem_core, self.ctx, addr, self.model[addr])