From f6127791c7b406a71c2a61ac655da55715098fc2 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 14 Apr 2024 15:06:06 -0700 Subject: [PATCH] doc: add inline CSS to fix WaveDrom renders in dark mode --- doc/architecture.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/doc/architecture.md b/doc/architecture.md index 0cbe59a..ea5f62a 100644 --- a/doc/architecture.md +++ b/doc/architecture.md @@ -28,8 +28,16 @@ The data bus is designed for simplicity, and consists of five signals used to pe Each core has a bus input and output port, so that cores can be daisy-chained together. When it receives an incoming bus transaction (signalled by `valid`), the core checks the address on the wire against its own memory space. If the address lies within the core, the core will perform the requested operation against its own memory space. In the case of a read, it places the data at that address on `data`, and in the case of a write, it copies the value of `data` to the specified location in memory. However, if the address lies outside of the memory of the core, then no operations are performed. -![Read Transaction](https://svg.wavedrom.com/github/fischermoseley/manta/render_wavedrom_directly/doc/assets/read_transaction.json5){:style="width:49%"} -![Write Transaction](https://svg.wavedrom.com/github/fischermoseley/manta/render_wavedrom_directly/doc/assets/write_transaction.json5){:style="width:49%"} + + +![Read Transaction](https://svg.wavedrom.com/github/fischermoseley/manta/render_wavedrom_directly/doc/assets/read_transaction.json5){.svg-container} +![Write Transaction](https://svg.wavedrom.com/github/fischermoseley/manta/render_wavedrom_directly/doc/assets/write_transaction.json5){.svg-container} ## Message Format