From f4e211fe92b92154cc3b505b157bacc346dbc844 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 11 Feb 2026 14:54:26 -0700 Subject: [PATCH] uart: fix tests for receiver and transmitter modules --- test/test_uart_rx_sim.py | 6 +++--- test/test_uart_tx_sim.py | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/test/test_uart_rx_sim.py b/test/test_uart_rx_sim.py index b6b3680..55d41cd 100644 --- a/test/test_uart_rx_sim.py +++ b/test/test_uart_rx_sim.py @@ -15,9 +15,9 @@ async def verify_receive(ctx, data): bit_index = i // uart_rx._clocks_per_baud # Every cycle, run checks on uart_rx: - if ctx.get(uart_rx.valid_o): - if ctx.get(uart_rx.data_o) != data: - a = ctx.get(uart_rx.data_o) + if ctx.get(uart_rx.source.valid): + if ctx.get(uart_rx.source.data) != data: + a = ctx.get(uart_rx.source.data) print(data_bits) raise ValueError( f"Incorrect byte presented - gave {hex(a)} instead of {hex(data)}!" diff --git a/test/test_uart_tx_sim.py b/test/test_uart_tx_sim.py index 7933a84..744bbe6 100644 --- a/test/test_uart_tx_sim.py +++ b/test/test_uart_tx_sim.py @@ -10,12 +10,12 @@ async def verify_bit_sequence(ctx, byte): """ # Request byte to be transmitted - ctx.set(uart_tx.data_i, byte) - ctx.set(uart_tx.start_i, 1) + ctx.set(uart_tx.sink.data, byte) + ctx.set(uart_tx.sink.valid, 1) await ctx.tick() - ctx.set(uart_tx.data_i, 0) - ctx.set(uart_tx.start_i, 0) + ctx.set(uart_tx.sink.data, 0) + ctx.set(uart_tx.sink.valid, 0) # Check that data bit is correct on every clock baud period @@ -29,12 +29,12 @@ async def verify_bit_sequence(ctx, byte): if ctx.get(uart_tx.tx) != data_bits[bit_index]: raise ValueError("Wrong bit in sequence!") - if ctx.get(uart_tx.done_o) and (bit_index != 9): + if ctx.get(uart_tx.sink.ready) and (bit_index != 9): raise ValueError("Done asserted too early!") await ctx.tick() - if not ctx.get(uart_tx.done_o): + if not ctx.get(uart_tx.sink.ready): raise ValueError("Done not asserted at end of transmission!")