diff --git a/src/manta/cli.py b/src/manta/cli.py
index 9407fd2..b606f23 100644
--- a/src/manta/cli.py
+++ b/src/manta/cli.py
@@ -96,7 +96,7 @@ def capture(config_path, logic_analyzer_name, export_paths):
 
     for path in export_paths:
         if ".vcd" in path:
-            cap.export_vcd(path)
+            cap.export_vcd(path, m.interface.get_frequency())
         elif ".csv" in path:
             cap.export_csv(path)
         elif ".v" in path:
diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py
index 6b334da..4d481a2 100644
--- a/src/manta/ethernet/__init__.py
+++ b/src/manta/ethernet/__init__.py
@@ -90,6 +90,9 @@ class EthernetInterface(Elaboratable):
         """
         return [io[2] for io in self._phy_io]
 
+    def get_frequency(self):
+        return self._clk_freq
+
     def _binarize_ip_addr(self, ip_addr):
         octets = [bin(int(o))[2:].zfill(8) for o in ip_addr.split(".")]
         return int("".join(octets), 2)
diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py
index 2276a6a..545efa8 100644
--- a/src/manta/logic_analyzer/__init__.py
+++ b/src/manta/logic_analyzer/__init__.py
@@ -322,7 +322,7 @@ class LogicAnalyzerCapture:
             writer.writerow(names)
             writer.writerows(values_t)
 
-    def export_vcd(self, path):
+    def export_vcd(self, path, frequency):
         """
         Export the capture to a VCD file, containing the data of all probes in
         the core.
@@ -335,7 +335,15 @@ class LogicAnalyzerCapture:
         timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y")
         vcd_file = open(path, "w")
 
-        with VCDWriter(vcd_file, "10 ns", timestamp, "manta") as writer:
+        # Compute the timescale from the frequency of the provided clock
+        timescale_value = 0.5 / frequency
+        timescale_scale = 0
+        while timescale_value < 1.0:
+            timescale_scale += 1
+            timescale_value *= 10
+        timescale = ["1 s", "100 ms", "10 ms", "1 ms", "100 us", "10 us", "1 us", "100 ns", "10 ns", "1 ns"][timescale_scale]
+
+        with VCDWriter(vcd_file, timescale, timestamp, "manta") as writer:
             # Each probe has a name, width, and writer associated with it
             signals = []
             for name, width in self._config["probes"].items():
@@ -358,8 +366,10 @@ class LogicAnalyzerCapture:
 
             # Add the data to each probe in the vcd file
             for timestamp in range(0, 2 * len(self._data)):
+                # Calculate the nearest time step
+                ts = round(timestamp * timescale_value)
                 # Run the clock
-                writer.change(clock, timestamp, timestamp % 2 == 0)
+                writer.change(clock, ts, timestamp % 2 == 0)
 
                 # Set the trigger (if there is one)
                 if (
@@ -367,14 +377,14 @@ class LogicAnalyzerCapture:
                     or self._config["trigger_mode"] == "single_shot"
                 ):
                     triggered = (timestamp // 2) >= self.get_trigger_location()
-                    writer.change(trigger, timestamp, triggered)
+                    writer.change(trigger, ts, triggered)
 
                 # Add other signals
                 for signal in signals:
                     var = signal["var"]
                     sample = signal["data"][timestamp // 2]
 
-                    writer.change(var, timestamp, sample)
+                    writer.change(var, ts, sample)
 
         vcd_file.close()
 
diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py
index 2e38cf4..ab88e0e 100644
--- a/src/manta/uart/__init__.py
+++ b/src/manta/uart/__init__.py
@@ -138,6 +138,9 @@ class UARTInterface(Elaboratable):
         """
         return [self.rx, self.tx]
 
+    def get_frequency(self):
+        return self._clock_freq
+
     def read(self, addrs):
         """
         Read the data stored in a set of address on Manta's internal memory.