From e1ac69846375d24ca5700de5afcd208eb424913f Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Tue, 26 Nov 2024 21:24:50 -0800 Subject: [PATCH] ethernet: load divider.sv via symlink --- .../nexys4_ddr/ether_logic_analyzer_io_core/divider.sv | 1 + test/test_ethernet_interface.py | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) create mode 120000 examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/divider.sv diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/divider.sv b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/divider.sv new file mode 120000 index 0000000..d692cbb --- /dev/null +++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/divider.sv @@ -0,0 +1 @@ +../../../common/divider.sv \ No newline at end of file diff --git a/test/test_ethernet_interface.py b/test/test_ethernet_interface.py index 5fc3778..5905d07 100644 --- a/test/test_ethernet_interface.py +++ b/test/test_ethernet_interface.py @@ -1,6 +1,7 @@ -import pytest import time from random import getrandbits + +import pytest from amaranth import * from amaranth.lib import io from amaranth_boards.nexys4ddr import Nexys4DDRPlatform @@ -8,6 +9,7 @@ from amaranth_boards.nexys4ddr import Nexys4DDRPlatform from manta import * from manta.utils import * + class EthernetMemoryCoreTest(Elaboratable): def __init__(self, platform): self.platform = platform @@ -102,7 +104,6 @@ class EthernetMemoryCoreTest(Elaboratable): ) - @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_mem_core_xilinx(): - EthernetMemoryCoreTest(Nexys4DDRPlatform()).verify() \ No newline at end of file + EthernetMemoryCoreTest(Nexys4DDRPlatform()).verify()