diff --git a/examples/amaranth/uart_io_core.py b/examples/amaranth/uart_io_core.py index c5915a2..7d7f6ad 100644 --- a/examples/amaranth/uart_io_core.py +++ b/examples/amaranth/uart_io_core.py @@ -1,8 +1,6 @@ from amaranth import * from amaranth.lib import io from manta import * -from manta.io_core import IOCore -from manta.uart import UARTInterface from time import sleep diff --git a/examples/amaranth/uart_logic_analyzer.py b/examples/amaranth/uart_logic_analyzer.py index 0d5a999..69cabdc 100644 --- a/examples/amaranth/uart_logic_analyzer.py +++ b/examples/amaranth/uart_logic_analyzer.py @@ -1,8 +1,6 @@ from amaranth import * from amaranth.lib import io from manta import * -from manta.logic_analyzer import LogicAnalyzerCore, TriggerModes -from manta.uart import UARTInterface from time import sleep diff --git a/examples/amaranth/uart_memory_core.py b/examples/amaranth/uart_memory_core.py index f54521a..a135827 100644 --- a/examples/amaranth/uart_memory_core.py +++ b/examples/amaranth/uart_memory_core.py @@ -1,8 +1,6 @@ from amaranth import * from amaranth.lib import io from manta import * -from manta.memory_core import MemoryCore -from manta.uart import UARTInterface class UARTMemoryCoreExample(Elaboratable): diff --git a/src/manta/__init__.py b/src/manta/__init__.py index f95e36e..a5e8034 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -1,5 +1,20 @@ from manta.manta import Manta +from manta.uart import UARTInterface +from manta.ethernet import EthernetInterface +from manta.logic_analyzer import LogicAnalyzerCore, TriggerModes +from manta.io_core import IOCore +from manta.memory_core import MemoryCore from manta.cli import main +__all__ = [ + "Manta", + "UARTInterface", + "EthernetInterface", + "LogicAnalyzerCore", + "TriggerModes", + "IOCore", + "MemoryCore", +] + if __name__ == "__main__": main() diff --git a/src/manta/utils.py b/src/manta/utils.py index 248d198..47922c7 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,4 +1,4 @@ -from amaranth import * +from amaranth import Elaboratable from amaranth.lib import data from amaranth.sim import Simulator from abc import ABC, abstractmethod diff --git a/test/test_config_export.py b/test/test_config_export.py index 6340ee9..1234af5 100644 --- a/test/test_config_export.py +++ b/test/test_config_export.py @@ -1,10 +1,5 @@ -from manta import Manta -from manta.io_core import IOCore -from manta.memory_core import MemoryCore -from manta.logic_analyzer import LogicAnalyzerCore -from manta.uart import UARTInterface -from manta.ethernet import EthernetInterface from amaranth import * +from manta import * import tempfile import os import yaml diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 9f85c99..d6b1415 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -1,9 +1,8 @@ -from manta import Manta +from amaranth import * from amaranth.lib import io from amaranth_boards.nexys4ddr import Nexys4DDRPlatform from amaranth_boards.icestick import ICEStickPlatform -from manta.io_core import IOCore -from manta.uart import UARTInterface +from manta import * from manta.utils import * import pytest from random import getrandbits diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py index 4c841ab..31dbd6f 100644 --- a/test/test_io_core_sim.py +++ b/test/test_io_core_sim.py @@ -1,5 +1,5 @@ from amaranth import * -from manta.io_core import IOCore +from manta import * from manta.utils import * from random import getrandbits diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 1686294..c1aa6e7 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -2,9 +2,7 @@ from amaranth import * from amaranth.lib import io from amaranth_boards.nexys4ddr import Nexys4DDRPlatform from amaranth_boards.icestick import ICEStickPlatform -from manta import Manta -from manta.logic_analyzer import LogicAnalyzerCore -from manta.uart import UARTInterface +from manta import * from manta.utils import * import pytest import os diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index b84d978..0d42569 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -1,4 +1,4 @@ -from amaranth.sim import Simulator +from amaranth import * from manta.logic_analyzer import LogicAnalyzerCore from manta.logic_analyzer.trigger_block import Operations from manta.utils import * diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 8ad9b3e..03b0f58 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -2,10 +2,7 @@ from amaranth import * from amaranth.lib import io from amaranth_boards.nexys4ddr import Nexys4DDRPlatform from amaranth_boards.icestick import ICEStickPlatform -from manta import Manta -from manta.memory_core import MemoryCore -from manta.io_core import IOCore -from manta.uart import UARTInterface +from manta import * from manta.utils import * import pytest from random import getrandbits diff --git a/test/test_source_bridge_sim.py b/test/test_source_bridge_sim.py index 6c7c064..04654ba 100644 --- a/test/test_source_bridge_sim.py +++ b/test/test_source_bridge_sim.py @@ -1,4 +1,3 @@ -from amaranth.sim import Simulator from manta.ethernet import UDPSourceBridge from manta.utils import *