From d5dfd3bbf3bb6e7c3c9b0fb8fa374149b04f6e3a Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Thu, 23 Mar 2023 23:50:09 -0400
Subject: [PATCH] add boilerplate for API generation tests

---
 Makefile                                      | 113 ++++++++++--------
 doc/todo.md                                   |   3 -
 test/api_gen/run_test.py                      |   1 +
 test/api_gen/valid_configs/0_io_core.yaml     |  26 ++++
 .../valid_configs/1_logic_analyzer.yaml       |  19 +++
 test/api_gen/valid_configs/2_lut_ram.yaml     |  10 ++
 test/{ => hdl_tb}/bit_fifo_tb.sv              |   0
 test/{ => hdl_tb}/bridge_rx_tb.sv             |   0
 test/{ => hdl_tb}/bridge_tx_tb.sv             |   0
 test/{ => hdl_tb}/bus_fix_tb.sv               |   0
 test/{ => hdl_tb}/fifo_tb.sv                  |   0
 test/{ => hdl_tb}/io_core_tb.sv               |   0
 test/{ => hdl_tb}/logic_analyzer_tb.sv        |   0
 test/{ => hdl_tb}/lut_ram_tb.sv               |   0
 test/{ => hdl_tb}/uart_tb.sv                  |   0
 test/{ => hdl_tb}/uart_tx_tb.sv               |   0
 16 files changed, 116 insertions(+), 56 deletions(-)
 create mode 100644 test/api_gen/run_test.py
 create mode 100644 test/api_gen/valid_configs/0_io_core.yaml
 create mode 100644 test/api_gen/valid_configs/1_logic_analyzer.yaml
 create mode 100644 test/api_gen/valid_configs/2_lut_ram.yaml
 rename test/{ => hdl_tb}/bit_fifo_tb.sv (100%)
 rename test/{ => hdl_tb}/bridge_rx_tb.sv (100%)
 rename test/{ => hdl_tb}/bridge_tx_tb.sv (100%)
 rename test/{ => hdl_tb}/bus_fix_tb.sv (100%)
 rename test/{ => hdl_tb}/fifo_tb.sv (100%)
 rename test/{ => hdl_tb}/io_core_tb.sv (100%)
 rename test/{ => hdl_tb}/logic_analyzer_tb.sv (100%)
 rename test/{ => hdl_tb}/lut_ram_tb.sv (100%)
 rename test/{ => hdl_tb}/uart_tb.sv (100%)
 rename test/{ => hdl_tb}/uart_tx_tb.sv (100%)

diff --git a/Makefile b/Makefile
index 1e48206..b595e42 100644
--- a/Makefile
+++ b/Makefile
@@ -8,58 +8,6 @@ lint:
 	python3 -m black src/manta/__init__.py
 	python3 -m black src/manta/__main__.py
 
-sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb 
-
-io_core_tb:
-	iverilog -g2012 -o sim.out test/io_core_tb.sv src/manta/io_core.v
-	vvp sim.out
-	rm sim.out
-
-logic_analyzer_tb:
-	iverilog -g2012 -o sim.out test/logic_analyzer_tb.sv src/manta/logic_analyzer.v src/manta/la_fsm.v src/manta/trigger_block.v src/manta/trigger.v src/manta/sample_mem.v src/manta/xilinx_true_dual_port_read_first_2_clock_ram.v
-	vvp sim.out
-	rm sim.out
-
-bit_fifo_tb:
-	iverilog -g2012 -o sim.out test/bit_fifo_tb.sv src/manta/bit_fifo.v
-	vvp sim.out
-	rm sim.out
-
-bridge_rx_tb:
-	iverilog -g2012 -o sim.out test/bridge_rx_tb.sv src/manta/bridge_rx.v
-	vvp sim.out
-	rm sim.out
-
-bridge_tx_tb:
-	iverilog -g2012 -o sim.out test/bridge_tx_tb.sv src/manta/bridge_tx.v src/manta/uart_tx.v
-	vvp sim.out
-	rm sim.out
-
-fifo_tb:
-	iverilog -g2012 -o sim.out test/fifo_tb.sv src/manta/fifo.v src/manta/xilinx_true_dual_port_read_first_2_clock_ram.v
-	vvp sim.out >> /dev/null # this one is noisy right now
-	rm sim.out
-
-lut_ram_tb:
-	iverilog -g2012 -o sim.out test/lut_ram_tb.sv src/manta/lut_ram.v 
-	vvp sim.out
-	rm sim.out
-
-uart_tb:
-	iverilog -g2012 -o sim.out test/uart_tb.sv src/manta/tx_uart.v src/manta/uart_rx.v 
-	vvp sim.out
-	rm sim.out
-
-uart_tx_tb:
-	iverilog -g2012 -o sim.out test/uart_tx_tb.sv src/manta/tx_uart.v src/manta/uart_tx.v src/manta/rx_uart.v 
-	vvp sim.out
-	rm sim.out
-	
-clean:
-	rm -f *.out *.vcd
-	rm -rf dist/
-	rm -rf src/mantaray.egg-info
-
 serve_docs:
 	mkdocs serve
 
@@ -67,4 +15,63 @@ total_loc:
 	find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs  wc -l
 
 real_loc:
-	find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs  wc -l
\ No newline at end of file
+	find src ${TB} -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs  wc -l
+
+test: api_gen func_sim
+
+# API Generation Tests
+api_gen: 
+	python3 test/api_gen/run_test.py
+
+# Functional Simulation
+func_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb 
+
+io_core_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/io_core_tb.sv -y src/manta
+	vvp sim.out
+	rm sim.out
+
+logic_analyzer_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/logic_analyzer_tb.sv -y src/manta
+	vvp sim.out
+	rm sim.out
+
+bit_fifo_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/bit_fifo_tb.sv -y src/manta
+	vvp sim.out
+	rm sim.out
+
+bridge_rx_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/bridge_rx_tb.sv -y src/manta
+	vvp sim.out
+	rm sim.out
+
+bridge_tx_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/bridge_tx_tb.sv -y src/manta
+	vvp sim.out
+	rm sim.out
+
+fifo_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/fifo_tb.sv -y src/manta 
+	vvp sim.out >> /dev/null # this one is noisy right now
+	rm sim.out
+
+lut_ram_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/lut_ram_tb.sv -y src/manta
+	vvp sim.out
+	rm sim.out
+
+uart_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/uart_tb.sv -y src/manta
+	vvp sim.out
+	rm sim.out
+
+uart_tx_tb:
+	iverilog -g2012 -o sim.out test/hdl_tb/uart_tx_tb.sv -y src/manta
+	vvp sim.out
+	rm sim.out
+	
+clean:
+	rm -f *.out *.vcd
+	rm -rf dist/
+	rm -rf src/mantaray.egg-info
diff --git a/doc/todo.md b/doc/todo.md
index ab5e203..858243a 100644
--- a/doc/todo.md
+++ b/doc/todo.md
@@ -1,11 +1,8 @@
 # ToDo
 
 ## IO Core
-- test examples that build
 - add logic for ports >16 bits in width
 - clock domain crossing
-- figure out what happens for module naming - it's possible we could have two modules that have the same ports but have different names
-    - do we say that port names have to be globally unique? or do we allow something like `module_name_module_type_inst` for example
 
 ## Logic Analyzer Core
 - need to finish up simulations, those might get broken out into separate testbenches for each module
diff --git a/test/api_gen/run_test.py b/test/api_gen/run_test.py
new file mode 100644
index 0000000..a0b7ca4
--- /dev/null
+++ b/test/api_gen/run_test.py
@@ -0,0 +1 @@
+# try to build manta instances from valid and invalid configuration files
\ No newline at end of file
diff --git a/test/api_gen/valid_configs/0_io_core.yaml b/test/api_gen/valid_configs/0_io_core.yaml
new file mode 100644
index 0000000..867efbe
--- /dev/null
+++ b/test/api_gen/valid_configs/0_io_core.yaml
@@ -0,0 +1,26 @@
+---
+cores:
+  my_io_core:
+    type: io
+
+    inputs:
+      btnu: 1
+      btnd: 1
+      btnl: 1
+      btnr: 1
+      btnc: 1
+      sw: 16
+
+    outputs:
+      led: 16
+      led16_b: 1
+      led16_g: 1
+      led16_r: 1
+      led17_b: 1
+      led17_g: 1
+      led17_r: 1
+
+uart:
+  port: "auto"
+  baudrate: 115200
+  clock_freq: 100000000
\ No newline at end of file
diff --git a/test/api_gen/valid_configs/1_logic_analyzer.yaml b/test/api_gen/valid_configs/1_logic_analyzer.yaml
new file mode 100644
index 0000000..107efa8
--- /dev/null
+++ b/test/api_gen/valid_configs/1_logic_analyzer.yaml
@@ -0,0 +1,19 @@
+---
+cores:
+  my_logic_analyzer:
+    type: logic_analyzer
+    sample_depth: 4096
+    
+    probes:
+      larry: 1
+      curly: 1
+      moe: 1
+      shemp: 4
+      
+    triggers:
+    - larry && curly && ~moe
+
+uart:
+  port: "auto"
+  baudrate: 115200
+  clock_freq: 100000000
\ No newline at end of file
diff --git a/test/api_gen/valid_configs/2_lut_ram.yaml b/test/api_gen/valid_configs/2_lut_ram.yaml
new file mode 100644
index 0000000..5427118
--- /dev/null
+++ b/test/api_gen/valid_configs/2_lut_ram.yaml
@@ -0,0 +1,10 @@
+---
+cores:
+  my_lut_ram:
+    type: lut_ram 
+    size: 64 
+
+uart:
+  port: "auto"
+  baudrate: 115200
+  clock_freq: 100000000
\ No newline at end of file
diff --git a/test/bit_fifo_tb.sv b/test/hdl_tb/bit_fifo_tb.sv
similarity index 100%
rename from test/bit_fifo_tb.sv
rename to test/hdl_tb/bit_fifo_tb.sv
diff --git a/test/bridge_rx_tb.sv b/test/hdl_tb/bridge_rx_tb.sv
similarity index 100%
rename from test/bridge_rx_tb.sv
rename to test/hdl_tb/bridge_rx_tb.sv
diff --git a/test/bridge_tx_tb.sv b/test/hdl_tb/bridge_tx_tb.sv
similarity index 100%
rename from test/bridge_tx_tb.sv
rename to test/hdl_tb/bridge_tx_tb.sv
diff --git a/test/bus_fix_tb.sv b/test/hdl_tb/bus_fix_tb.sv
similarity index 100%
rename from test/bus_fix_tb.sv
rename to test/hdl_tb/bus_fix_tb.sv
diff --git a/test/fifo_tb.sv b/test/hdl_tb/fifo_tb.sv
similarity index 100%
rename from test/fifo_tb.sv
rename to test/hdl_tb/fifo_tb.sv
diff --git a/test/io_core_tb.sv b/test/hdl_tb/io_core_tb.sv
similarity index 100%
rename from test/io_core_tb.sv
rename to test/hdl_tb/io_core_tb.sv
diff --git a/test/logic_analyzer_tb.sv b/test/hdl_tb/logic_analyzer_tb.sv
similarity index 100%
rename from test/logic_analyzer_tb.sv
rename to test/hdl_tb/logic_analyzer_tb.sv
diff --git a/test/lut_ram_tb.sv b/test/hdl_tb/lut_ram_tb.sv
similarity index 100%
rename from test/lut_ram_tb.sv
rename to test/hdl_tb/lut_ram_tb.sv
diff --git a/test/uart_tb.sv b/test/hdl_tb/uart_tb.sv
similarity index 100%
rename from test/uart_tb.sv
rename to test/hdl_tb/uart_tb.sv
diff --git a/test/uart_tx_tb.sv b/test/hdl_tb/uart_tx_tb.sv
similarity index 100%
rename from test/uart_tx_tb.sv
rename to test/hdl_tb/uart_tx_tb.sv