From bdc082e8d692fd554a3b98d21fc78cb4bc090abb Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Thu, 16 Mar 2023 08:30:19 -0400
Subject: [PATCH] add io core, playing with verilator lint

---
 doc/logic_analyzer_core.md |  2 +-
 src/manta/io_core.v        | 74 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+), 1 deletion(-)
 create mode 100644 src/manta/io_core.v

diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md
index a69e0e1..254b46c 100644
--- a/doc/logic_analyzer_core.md
+++ b/doc/logic_analyzer_core.md
@@ -32,7 +32,7 @@ There's a few parameters that get configured here, including:
 
 ## Probes
 
-Probes are the signals read by the core. These are meant to be connected to your RTL design when you instantiate your generated copy of Manta. These can be given whatever name and width you like (within reason). You can have up to 256 probes in your design. 
+Probes are the signals read by the core. These are meant to be connected to your RTL design when you instantiate your generated copy of Manta. These can be given whatever name and width you like (within reason). You can have up to ~32k probes in your design. 
 
 ## Sample Depth
 
diff --git a/src/manta/io_core.v b/src/manta/io_core.v
new file mode 100644
index 0000000..fb8dd97
--- /dev/null
+++ b/src/manta/io_core.v
@@ -0,0 +1,74 @@
+`default_nettype none
+`timescale 1ns/1ps
+
+module io_core(
+    input wire clk,
+
+    // inputs
+    input wire picard,
+    input wire [6:0] data,
+    input wire [9:0] laforge,
+    input wire troi,
+
+    // outputs
+    output reg kirk,
+    output reg [4:0] spock,
+    output reg [2:0] uhura,
+    output reg chekov,
+
+    // input port
+    input wire [15:0] addr_i,
+    input wire [15:0] wdata_i,
+    input wire [15:0] rdata_i,
+    input wire rw_i,
+    input wire valid_i,
+
+    // output port
+    output reg [15:0] addr_o,
+    output reg [15:0] wdata_o,
+    output reg [15:0] rdata_o,
+    output reg rw_o,
+    output reg valid_o
+    );
+
+    parameter DEPTH = 8;
+    parameter BASE_ADDR = 0;
+
+    always @(posedge clk) begin
+        addr_o <= addr_i;
+        wdata_o <= wdata_i;
+        rdata_o <= rdata_i;
+        rw_o <= rw_i;
+        valid_o <= valid_i;
+        rdata_o <= rdata_i;
+        
+
+        // check if address is valid
+        if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + 2)) begin
+
+            if(!rw_i) begin // reads
+                case (addr_i)
+                    BASE_ADDR + 0: rdata_o <= {15'b0, picard};
+                    BASE_ADDR + 1: rdata_o <= {9'b0,  data};
+                    BASE_ADDR + 2: rdata_o <= {6'b0,  laforge};
+                    BASE_ADDR + 3: rdata_o <= {15'b0, troi};
+                    BASE_ADDR + 4: rdata_o <= {15'b0, kirk};
+                    BASE_ADDR + 5: rdata_o <= {11'b0, spock};
+                    BASE_ADDR + 6: rdata_o <= {13'b0, uhura};
+                    BASE_ADDR + 7: rdata_o <= {15'b0, chekov};
+                endcase
+            end
+
+            else begin // writes
+                case (addr_i)
+                    BASE_ADDR + 4: kirk   <= wdata_i[0];
+                    BASE_ADDR + 5: spock  <= wdata_i[4:0];
+                    BASE_ADDR + 6: uhura  <= wdata_i[2:0];
+                    BASE_ADDR + 7: chekov <= wdata_i[0];
+                endcase
+            end
+        end
+    end
+endmodule
+
+`default_nettype wire
\ No newline at end of file