diff --git a/.DS_Store b/.DS_Store new file mode 100644 index 0000000..81229e8 Binary files /dev/null and b/.DS_Store differ diff --git a/.github/workflows/build_docs.yml b/.github/workflows/build_docs.yml index 3c0d632..ef4ca38 100644 --- a/.github/workflows/build_docs.yml +++ b/.github/workflows/build_docs.yml @@ -1,4 +1,4 @@ -name: build_docs +name: docs_site on: push: branches: @@ -17,5 +17,5 @@ jobs: with: key: ${{ github.ref }} path: .cache - - run: pip install mkdocs-material + - run: pip install mkdocs-material - run: mkdocs gh-deploy --force diff --git a/.github/workflows/build_examples.yml b/.github/workflows/build_examples.yml deleted file mode 100644 index a9c0598..0000000 --- a/.github/workflows/build_examples.yml +++ /dev/null @@ -1,25 +0,0 @@ -name: build_examples -on: [push] -jobs: - examples: - runs-on: self-hosted - steps: - - uses: actions/checkout@v3 - - name: Install Manta from source - run: | - pip install setuptools --upgrade - - # omitting the following commmand causes the version of setuptools - # used by python to get confused, and it doesn't detect the name - # or version of the package from pyproject.toml - so the following - # workaround is used: - # https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377 - export DEB_PYTHON_INSTALL_LAYOUT=deb_system - - python3 -m pip install . - - - name: Build Nexys A7 examples - run: make nexys_a7 - - - name: Build Icestick examples - run: make icestick diff --git a/.github/workflows/functional_simulation.yml b/.github/workflows/functional_simulation.yml deleted file mode 100644 index 1232960..0000000 --- a/.github/workflows/functional_simulation.yml +++ /dev/null @@ -1,29 +0,0 @@ -name: functional_simulation -on: [push] -jobs: - all: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v3 - - - name: Install Manta from Source - run: | - pip install setuptools --upgrade - - # omitting the following commmand causes the version of setuptools - # used by python to get confused, and it doesn't detect the name - # or version of the package from pyproject.toml - so the following - # workaround is used: - # https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377 - export DEB_PYTHON_INSTALL_LAYOUT=deb_system - - python3 -m pip install . - - - name: Install oss-cad-suite - run: | - wget --no-verbose https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2023-02-23/oss-cad-suite-linux-x64-20230223.tgz - tar -xzf oss-cad-suite-linux-x64-20230223.tgz - echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH - - - name: Run functional simulations - run: make sim \ No newline at end of file diff --git a/.github/workflows/formal_verification.yml b/.github/workflows/run_tests.yml similarity index 53% rename from .github/workflows/formal_verification.yml rename to .github/workflows/run_tests.yml index 3b548cc..331fb58 100644 --- a/.github/workflows/formal_verification.yml +++ b/.github/workflows/run_tests.yml @@ -1,4 +1,4 @@ -name: formal_verification +name: run_tests on: [push] jobs: all: @@ -8,7 +8,7 @@ jobs: - name: Install Manta from Source run: | - pip install setuptools --upgrade + python -m pip install -U pip # omitting the following commmand causes the version of setuptools # used by python to get confused, and it doesn't detect the name @@ -17,13 +17,15 @@ jobs: # https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377 export DEB_PYTHON_INSTALL_LAYOUT=deb_system - python3 -m pip install . + python -m pip install ".[dev]" - - name: Install oss-cad-suite - run: | - wget --no-verbose https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2023-02-23/oss-cad-suite-linux-x64-20230223.tgz - tar -xzf oss-cad-suite-linux-x64-20230223.tgz - echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH + # export tool paths + export VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado + export YOSYS=/tools/oss-cad-suite/bin/yosys + export NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr_ice40 + export ICEPACK=/tools/oss-cad-suite/bin/icepack + export ICEPROG=/tools/oss-cad-suite/bin/iceprog - - name: Run formal verification - run: make formal \ No newline at end of file + + - name: Run tests + run: make test \ No newline at end of file diff --git a/.gitignore b/.gitignore index 39837fb..8fb17e5 100644 --- a/.gitignore +++ b/.gitignore @@ -1,33 +1,10 @@ -# Hidden files -.DS_Store -*.vscode/ - -# Python outputs venv/ -dist/ -build/ -*.egg-info +manta.egg-info/ +.pytest_cache __pycache__/ +build/ -# Vivado output products -*.Xil/ -*.log -*.jou -*.rpt -*.bit -cpu_impl_netlist.v - -# IceStorm output products -*.bin - -# iVerilog output products +*.v +*.sv *.vcd -*.out - -# Formal outputs -test/formal_verification/*_basic -test/formal_verification/*_cover - -# Manta output products -manta.v -*.mem \ No newline at end of file +*.out \ No newline at end of file diff --git a/Makefile b/Makefile index b0ecfe5..c22f0d1 100644 --- a/Makefile +++ b/Makefile @@ -1,123 +1,12 @@ -# Tool Paths -VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado -YOSYS=/tools/oss-cad-suite/bin/yosys -NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr-ice40 -ICEPACK=/tools/oss-cad-suite/bin/icepack +.PHONY: test format clean serve_docs +test: + pytest -test: auto_gen sim formal - -examples: icestick nexys_a7 +format: + black . clean: - @echo "Deleting everything matched by .gitignore" git clean -Xdf serve_docs: mkdocs serve - -# Python Operations -python_build: - python3 -m build - -pypi_upload: build - python3 -m twine upload --repository testpypi dist/* - -python_lint: - python3 -m black src/manta/__init__.py - python3 -m black src/manta/__main__.py - -# API Generation Tests -auto_gen: - python3 test/auto_gen/run_tests.py - -# Build Examples -NEXYS_A7_EXAMPLES := io_core_ether io_core_uart ps2_logic_analyzer video_sprite_ether video_sprite_uart block_mem_uart logic_analyzer_uart large_io_core_uart - -.PHONY: nexys_a7 $(NEXYS_A7_EXAMPLES) -nexys_a7: $(NEXYS_A7_EXAMPLES) - -$(NEXYS_A7_EXAMPLES): - cd examples/nexys_a7/$@; \ - python3 -m manta gen manta.yaml src/manta.v; \ - rm -rf obj; \ - mkdir -p obj; \ - $(VIVADO) -mode batch \ - -source ../build.tcl \ - -log obj/build.log \ - -jou obj/build.jou; \ - rm -rf .Xil; - -ICESTICK_EXAMPLES := io_core - -.PHONY: icestick $(ICESTICK_EXAMPLES) -icestick: $(ICESTICK_EXAMPLES) - -$(ICESTICK_EXAMPLES): - cd examples/icestick/$@; \ - python3 -m manta gen manta.yaml manta.v; \ - $(YOSYS) -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv; \ - $(NEXTPNR_ICE40) --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc; \ - $(ICEPACK) top_level.asc top_level.bin; \ - rm -f *.json; \ - rm -f *.asc; - -# Formal Verification -formal: - sby -f test/formal_verification/bridge_rx.sby - -# Functional Simulation -sim: ethernet_tx_tb ethernet_rx_tb mac_tb block_memory_tb io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb block_memory_tb - -ethernet_tx_tb: - iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_tx_tb.sv - vvp sim.out - rm sim.out - -ethernet_rx_tb: - iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_rx_tb.sv - vvp sim.out - rm sim.out - -mac_tb: - iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/mac_tb.sv - vvp sim.out - rm sim.out - -block_memory_tb: - iverilog -g2012 -o sim.out -y src/manta/block_mem_core test/functional_sim/block_memory_tb.sv - vvp sim.out - rm sim.out - -io_core_tb: - iverilog -g2012 -o sim.out \ - test/functional_sim/io_core_tb/io_core_tb.sv \ - test/functional_sim/io_core_tb/io_core.v - vvp sim.out - rm sim.out - -logic_analyzer_tb: - cd test/functional_sim/logic_analyzer_tb; \ - python3 -m manta gen manta.yaml manta.v; \ - iverilog -g2012 -o sim.out logic_analyzer_tb.sv manta.v; \ - vvp sim.out; \ - rm sim.out - -bridge_rx_tb: - iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_rx_tb.sv - vvp sim.out - rm sim.out - -bridge_tx_tb: - iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_tx_tb.sv - vvp sim.out - rm sim.out - -uart_rx_tb: - iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/uart_rx_tb.sv - vvp sim.out - rm sim.out - -uart_tx_tb: - iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/uart_tx_tb.sv - vvp sim.out - rm sim.out diff --git a/README.md b/README.md index 3a02d2b..e49515c 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,7 @@ ![](doc/assets/logo.png) ## Manta: An In-Situ Debugging Tool for Programmable Hardware -![functional_simulation](https://github.com/fischermoseley/manta/actions/workflows/functional_simulation.yml/badge.svg) -![formal_verification](https://github.com/fischermoseley/manta/actions/workflows/formal_verification.yml/badge.svg) -![build_examples](https://github.com/fischermoseley/manta/actions/workflows/build_examples.yml/badge.svg) +![run_tests](https://github.com/fischermoseley/manta/actions/workflows/run_tests.yml/badge.svg) ![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg) [![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0) diff --git a/examples/icestick/io_core/manta.yaml b/examples/icestick/io_core/manta.yaml deleted file mode 100644 index 80757ae..0000000 --- a/examples/icestick/io_core/manta.yaml +++ /dev/null @@ -1,16 +0,0 @@ ---- -cores: - my_io_core: - type: io - - outputs: - LED0: 1 - LED1: 1 - LED2: 1 - LED3: 1 - LED4: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 12000000 \ No newline at end of file diff --git a/examples/icestick/io_core/run_io_core.py b/examples/icestick/io_core/run_io_core.py deleted file mode 100644 index 36cc4dd..0000000 --- a/examples/icestick/io_core/run_io_core.py +++ /dev/null @@ -1,45 +0,0 @@ -from manta import Manta -from time import sleep - -m = Manta('manta.yaml') - -i = 0 -while True: - i = (i+1) % 5 - - if(i==0): - m.my_io_core.LED0.set(1) - m.my_io_core.LED1.set(0) - m.my_io_core.LED2.set(0) - m.my_io_core.LED3.set(0) - m.my_io_core.LED4.set(0) - - if(i==1): - m.my_io_core.LED0.set(0) - m.my_io_core.LED1.set(1) - m.my_io_core.LED2.set(0) - m.my_io_core.LED3.set(0) - m.my_io_core.LED4.set(0) - - if(i==2): - m.my_io_core.LED0.set(0) - m.my_io_core.LED1.set(0) - m.my_io_core.LED2.set(1) - m.my_io_core.LED3.set(0) - m.my_io_core.LED4.set(0) - - if(i==3): - m.my_io_core.LED0.set(0) - m.my_io_core.LED1.set(0) - m.my_io_core.LED2.set(0) - m.my_io_core.LED3.set(1) - m.my_io_core.LED4.set(0) - - if(i==4): - m.my_io_core.LED0.set(0) - m.my_io_core.LED1.set(0) - m.my_io_core.LED2.set(0) - m.my_io_core.LED3.set(0) - m.my_io_core.LED4.set(1) - - sleep(0.1) \ No newline at end of file diff --git a/examples/icestick/io_core/top_level.pcf b/examples/icestick/io_core/top_level.pcf deleted file mode 100644 index d042aa0..0000000 --- a/examples/icestick/io_core/top_level.pcf +++ /dev/null @@ -1,67 +0,0 @@ -# Generic iCEstick placement constraints file - -# Red LEDs -set_io LED0 99 -set_io LED1 98 -set_io LED2 97 -set_io LED3 96 - -# Green LED -set_io LED4 95 - -# IrDA port -#set_io RXD 106 -#set_io TXD 105 -#set_io SD 107 - -# Pmod connector -#set_io PIO1_02 78 # Pin 1 -#set_io PIO1_03 79 # Pin 2 -#set_io PIO1_04 80 # Pin 3 -#set_io PIO1_05 81 # Pin 4 -#set_io PIO1_06 87 # Pin 7 -#set_io PIO1_07 88 # Pin 8 -#set_io PIO1_08 90 # Pin 9 -#set_io PIO1_09 91 # Pin 10 - -# Connector J1 -#set_io PIO0_02 112 # Pin 3 -#set_io PIO0_03 113 # Pin 4 -#set_io PIO0_04 114 # Pin 5 -#set_io PIO0_05 115 # Pin 6 -#set_io PIO0_06 116 # Pin 7 -#set_io PIO0_07 117 # Pin 8 -#set_io PIO0_08 118 # Pin 9 -#set_io PIO0_09 119 # Pin 10 - -# Connector J3 -#set_io PIO2_17 62 # Pin 3 -#set_io PIO2_16 61 # Pin 4 -#set_io PIO2_15 60 # Pin 5 -#set_io PIO2_14 56 # Pin 6 -#set_io PIO2_13 48 # Pin 7 -#set_io PIO2_12 47 # Pin 8 -#set_io PIO2_11 45 # Pin 9 -#set_io PIO2_10 44 # Pin 10 - -# FTDI Port B UART -#set_io DCDn 1 -#set_io DSRn 2 -#set_io DTRn 3 -#set_io CTSn 4 -#set_io RTSn 7 -set_io rs232_tx_ttl 8 -set_io rs232_rx_ttl 9 - -# SPI -#set_io SPI_SCK 70 -#set_io SPI_SI 68 -#set_io SPI_SO 67 -#set_io SPI_SS_B 71 - -# Configuration pins -#set_io CDONE 65 -#set_io CRESET_B 66 - -# 12 MHz clock -set_io clk 21 diff --git a/examples/icestick/io_core/top_level.sv b/examples/icestick/io_core/top_level.sv deleted file mode 100644 index c8a1711..0000000 --- a/examples/icestick/io_core/top_level.sv +++ /dev/null @@ -1,32 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`include "manta.v" - -module top_level ( - input wire clk, - - output logic LED0, - output logic LED1, - output logic LED2, - output logic LED3, - output logic LED4, - - input wire rs232_rx_ttl, - output logic rs232_tx_ttl - ); - - manta manta_inst ( - .clk(clk), - - .rx(rs232_rx_ttl), - .tx(rs232_tx_ttl), - - .LED0(LED0), - .LED1(LED1), - .LED2(LED2), - .LED3(LED3), - .LED4(LED4)); -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/block_mem_uart/api_example.py b/examples/nexys_a7/block_mem_uart/api_example.py deleted file mode 100644 index 6323e75..0000000 --- a/examples/nexys_a7/block_mem_uart/api_example.py +++ /dev/null @@ -1,18 +0,0 @@ -from manta import Manta -from time import sleep -from random import randint - -m = Manta('manta.yaml') - -for addr in range(1024): - number = randint(0,65535) - m.my_block_memory.write(addr, number) - - readback = m.my_block_memory.read(addr) - - if readback == number: - print(f"Success! Wrote and read back {hex(number)} from {hex(addr)}") - - else: - print(f"Failure! Wrote {hex(number)} to {hex(addr)}, but received {hex(readback)}") - exit() diff --git a/examples/nexys_a7/block_mem_uart/manta.yaml b/examples/nexys_a7/block_mem_uart/manta.yaml deleted file mode 100644 index 756dab7..0000000 --- a/examples/nexys_a7/block_mem_uart/manta.yaml +++ /dev/null @@ -1,11 +0,0 @@ ---- -cores: - my_block_memory: - type: block_memory - width: 16 - depth: 1024 - -uart: - port: "/dev/ttyUSB1" - baudrate: 2000000 - clock_freq: 100000000 \ No newline at end of file diff --git a/examples/nexys_a7/block_mem_uart/src/top_level.sv b/examples/nexys_a7/block_mem_uart/src/top_level.sv deleted file mode 100644 index bb5cd1a..0000000 --- a/examples/nexys_a7/block_mem_uart/src/top_level.sv +++ /dev/null @@ -1,24 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire uart_txd_in, - output logic uart_rxd_out); - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .my_block_memory_clk(clk), - .my_block_memory_addr(0), - .my_block_memory_din(0), - .my_block_memory_dout(), - .my_block_memory_we(0)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/block_mem_uart/xdc/top_level.xdc b/examples/nexys_a7/block_mem_uart/xdc/top_level.xdc deleted file mode 100644 index df10467..0000000 --- a/examples/nexys_a7/block_mem_uart/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/build.tcl b/examples/nexys_a7/build.tcl deleted file mode 100644 index 810232a..0000000 --- a/examples/nexys_a7/build.tcl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir obj - -read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ] -read_xdc ./xdc/top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream - -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/nexys_a7/io_core_ether/api_example.py b/examples/nexys_a7/io_core_ether/api_example.py deleted file mode 100644 index d9d03b4..0000000 --- a/examples/nexys_a7/io_core_ether/api_example.py +++ /dev/null @@ -1,40 +0,0 @@ -from manta import Manta -from time import sleep - -m = Manta('manta.yaml') - -i = 0 -direction = "left" - -while True: - if direction == "left": - if i == 15: - direction = "right" - i = i - 1 - m.my_io_core.led16_r.set(1) - m.my_io_core.led16_g.set(0) - m.my_io_core.led16_b.set(1) - else: - i = i + 1 - - if direction == "right": - if i == 0: - direction = "left" - i = i + 1 - m.my_io_core.led16_r.set(0) - m.my_io_core.led16_g.set(1) - m.my_io_core.led16_b.set(0) - - else: - i = i - 1 - - m.my_io_core.led.set(2**i) - print(f"Input Ports:") - print(f" btnu: {m.my_io_core.btnu.get()}") - print(f" btnd: {m.my_io_core.btnd.get()}") - print(f" btnr: {m.my_io_core.btnr.get()}") - print(f" btnl: {m.my_io_core.btnl.get()}") - print(f" btnc: {m.my_io_core.btnc.get()}") - print(f" sw: {m.my_io_core.sw.get()}\n") - sleep(0.5) - diff --git a/examples/nexys_a7/io_core_ether/manta.yaml b/examples/nexys_a7/io_core_ether/manta.yaml deleted file mode 100644 index 4ca285e..0000000 --- a/examples/nexys_a7/io_core_ether/manta.yaml +++ /dev/null @@ -1,25 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: 1 - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -ethernet: - interface: "en8" - host_mac: "12:34:56:78:90:ab" \ No newline at end of file diff --git a/examples/nexys_a7/io_core_ether/src/divider.sv b/examples/nexys_a7/io_core_ether/src/divider.sv deleted file mode 100644 index 55aada8..0000000 --- a/examples/nexys_a7/io_core_ether/src/divider.sv +++ /dev/null @@ -1,193 +0,0 @@ -`default_nettype wire - -// file: divider.sv -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// popopopopopopopopopopop -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// __ethclk__50.00000______0.000______50.0______151.636_____98.575 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_________100.000____________0.010 - -`timescale 1ps/1ps - -module divider - - (// Clock in ports - // Clock out ports - output ethclk, - input clk - ); - // Input buffering - //------------------------------------ -wire clk_divider; -wire clk_in2_divider; - IBUF clkin1_ibufg - (.O (clk_divider), - .I (clk)); - - - - - // Clocking PRIMITIVE - //------------------------------------ - - // Instantiation of the MMCM PRIMITIVE - // * Unused inputs are tied off - // * Unused outputs are labeled unused - - wire ethclk_divider; - wire clk_out2_divider; - wire clk_out3_divider; - wire clk_out4_divider; - wire clk_out5_divider; - wire clk_out6_divider; - wire clk_out7_divider; - - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_int; - wire clkfbout_divider; - wire clkfbout_buf_divider; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (10.000), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (20.000), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (10.000)) - mmcm_adv_inst - // Output clocks - ( - .CLKFBOUT (clkfbout_divider), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (ethclk_divider), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clkout1_unused), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout_buf_divider), - .CLKIN1 (clk_divider), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (1'b0)); - -// Clock Monitor clock assigning -//-------------------------------------- - // Output buffering - //----------------------------------- - - BUFG clkf_buf - (.O (clkfbout_buf_divider), - .I (clkfbout_divider)); - - BUFG clkout1_buf - (.O (ethclk), - .I (ethclk_divider)); - -endmodule - -`default_nettype none diff --git a/examples/nexys_a7/io_core_ether/src/top_level.sv b/examples/nexys_a7/io_core_ether/src/top_level.sv deleted file mode 100644 index 913faca..0000000 --- a/examples/nexys_a7/io_core_ether/src/top_level.sv +++ /dev/null @@ -1,61 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire eth_crsdv, - input wire [1:0] eth_rxd, - output logic [1:0] eth_txd, - output logic eth_txen, - output logic eth_refclk, - output logic eth_rstn, - - input wire btnu, - input wire btnd, - input wire btnl, - input wire btnr, - input wire btnc, - input wire [15:0] sw, - output logic [15:0] led, - output logic led16_b, - output logic led16_g, - output logic led16_r, - output logic led17_b, - output logic led17_g, - output logic led17_r); - - // 50MHz clock generation for the RMII - logic ethclk; - divider div ( - .clk(clk), - .ethclk(ethclk)); - - assign eth_rstn = 1; - assign eth_refclk = ethclk; - - manta manta_inst ( - .clk(ethclk), - - .crsdv(eth_crsdv), - .rxd(eth_rxd), - .txen(eth_txen), - .txd(eth_txd), - - .btnu(btnu), - .btnd(btnd), - .btnl(btnl), - .btnr(btnr), - .btnc(btnc), - .sw(sw), - .led(led), - .led16_b(led16_b), - .led16_g(led16_g), - .led16_r(led16_r), - .led17_b(led17_b), - .led17_g(led17_g), - .led17_r(led17_r)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/io_core_ether/xdc/top_level.xdc b/examples/nexys_a7/io_core_ether/xdc/top_level.xdc deleted file mode 100644 index 119c5d3..0000000 --- a/examples/nexys_a7/io_core_ether/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/io_core_uart/api_example.py b/examples/nexys_a7/io_core_uart/api_example.py deleted file mode 100644 index d9d03b4..0000000 --- a/examples/nexys_a7/io_core_uart/api_example.py +++ /dev/null @@ -1,40 +0,0 @@ -from manta import Manta -from time import sleep - -m = Manta('manta.yaml') - -i = 0 -direction = "left" - -while True: - if direction == "left": - if i == 15: - direction = "right" - i = i - 1 - m.my_io_core.led16_r.set(1) - m.my_io_core.led16_g.set(0) - m.my_io_core.led16_b.set(1) - else: - i = i + 1 - - if direction == "right": - if i == 0: - direction = "left" - i = i + 1 - m.my_io_core.led16_r.set(0) - m.my_io_core.led16_g.set(1) - m.my_io_core.led16_b.set(0) - - else: - i = i - 1 - - m.my_io_core.led.set(2**i) - print(f"Input Ports:") - print(f" btnu: {m.my_io_core.btnu.get()}") - print(f" btnd: {m.my_io_core.btnd.get()}") - print(f" btnr: {m.my_io_core.btnr.get()}") - print(f" btnl: {m.my_io_core.btnl.get()}") - print(f" btnc: {m.my_io_core.btnc.get()}") - print(f" sw: {m.my_io_core.sw.get()}\n") - sleep(0.5) - diff --git a/examples/nexys_a7/io_core_uart/manta.yaml b/examples/nexys_a7/io_core_uart/manta.yaml deleted file mode 100644 index 867efbe..0000000 --- a/examples/nexys_a7/io_core_uart/manta.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: 1 - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/examples/nexys_a7/io_core_uart/src/top_level.sv b/examples/nexys_a7/io_core_uart/src/top_level.sv deleted file mode 100644 index d6e0f8c..0000000 --- a/examples/nexys_a7/io_core_uart/src/top_level.sv +++ /dev/null @@ -1,48 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire uart_txd_in, - output logic uart_rxd_out, - - input wire btnu, - input wire btnd, - input wire btnl, - input wire btnr, - input wire btnc, - - input wire [15:0] sw, - - output logic [15:0] led, - output logic led16_b, - output logic led16_g, - output logic led16_r, - output logic led17_b, - output logic led17_g, - output logic led17_r); - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .btnu(btnu), - .btnd(btnd), - .btnl(btnl), - .btnr(btnr), - .btnc(btnc), - .sw(sw), - .led(led), - .led16_b(led16_b), - .led16_g(led16_g), - .led16_r(led16_r), - .led17_b(led17_b), - .led17_g(led17_g), - .led17_r(led17_r)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/io_core_uart/xdc/top_level.xdc b/examples/nexys_a7/io_core_uart/xdc/top_level.xdc deleted file mode 100644 index 82c04c3..0000000 --- a/examples/nexys_a7/io_core_uart/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/large_io_core_uart/manta.yaml b/examples/nexys_a7/large_io_core_uart/manta.yaml deleted file mode 100644 index 25047eb..0000000 --- a/examples/nexys_a7/large_io_core_uart/manta.yaml +++ /dev/null @@ -1,23 +0,0 @@ ---- -cores: - io_core: - type: io - - inputs: - probe0: 1 - probe1: 2 - probe2: 8 - probe3: 20 - - outputs: - probe4: - width: 1 - initial_value: 1 - probe5: 2 - probe6: 8 - probe7: 20 - -uart: - port: "auto" - baudrate: 3000000 - clock_freq: 100000000 diff --git a/examples/nexys_a7/large_io_core_uart/src/top_level.sv b/examples/nexys_a7/large_io_core_uart/src/top_level.sv deleted file mode 100644 index 1664a41..0000000 --- a/examples/nexys_a7/large_io_core_uart/src/top_level.sv +++ /dev/null @@ -1,32 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire uart_txd_in, - output logic uart_rxd_out); - - logic probe0; - logic [1:0] probe1; - logic [7:0] probe2; - logic [19:0] probe3; - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .probe0(probe0), - .probe1(probe1), - .probe2(probe2), - .probe3(probe3), - .probe4(probe0), - .probe5(probe1), - .probe6(probe2), - .probe7(probe3)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/large_io_core_uart/test.py b/examples/nexys_a7/large_io_core_uart/test.py deleted file mode 100644 index f9bee51..0000000 --- a/examples/nexys_a7/large_io_core_uart/test.py +++ /dev/null @@ -1,26 +0,0 @@ -from manta import Manta -from random import randint -m = Manta('manta.yaml') - -n_tests = 100 -for i in range(n_tests): - print(f"-> Beginning test {i} of {n_tests}") - probe4 = randint(0, 1) - m.io_core.probe4.set(probe4) - assert m.io_core.probe4.get() == probe4 - assert m.io_core.probe0.get() == probe4 - - probe5 = randint(0, 3) - m.io_core.probe5.set(probe5) - assert m.io_core.probe5.get() == probe5 - assert m.io_core.probe1.get() == probe5 - - probe6 = randint(0, 255) - m.io_core.probe6.set(probe6) - assert m.io_core.probe6.get() == probe6 - assert m.io_core.probe2.get() == probe6 - - probe7 = randint(0, (2**20)-1) - m.io_core.probe7.set(probe7) - assert m.io_core.probe7.get() == probe7 - assert m.io_core.probe3.get() == probe7 diff --git a/examples/nexys_a7/large_io_core_uart/xdc/top_level.xdc b/examples/nexys_a7/large_io_core_uart/xdc/top_level.xdc deleted file mode 100644 index c23f104..0000000 --- a/examples/nexys_a7/large_io_core_uart/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] -# -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/logic_analyzer_uart/manta.yaml b/examples/nexys_a7/logic_analyzer_uart/manta.yaml deleted file mode 100644 index ccb1bea..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/manta.yaml +++ /dev/null @@ -1,20 +0,0 @@ ---- -cores: - my_logic_analyzer: - type: logic_analyzer - sample_depth: 1024 - - probes: - spike: 1 - jet: 2 - valentine: 3 - ed: 4 - ein: 5 - - triggers: - - ein EQ 3 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/examples/nexys_a7/logic_analyzer_uart/sim/playback.v b/examples/nexys_a7/logic_analyzer_uart/sim/playback.v deleted file mode 100644 index 9aa7a47..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/sim/playback.v +++ /dev/null @@ -1,58 +0,0 @@ -/* -This playback module was generated with Manta v0.0.5 on 23 Aug 2023 at 11:25:46 by fischerm - -If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! - -my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst ( - .clk(clk), - .enable(1'b1), - - .spike(spike), - .jet(jet), - .valentine(valentine), - .ed(ed), - .ein(ein)); - -*/ - - -module my_logic_analyzer_playback ( - input wire clk, - - input wire enable, - output reg done, - - output reg spike, - output reg [1:0] jet, - output reg [2:0] valentine, - output reg [3:0] ed, - output reg [4:0] ein); - - parameter MEM_FILE = ""; - localparam SAMPLE_DEPTH = 1024; - localparam TOTAL_PROBE_WIDTH = 15; - - reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0]; - reg [$clog2(SAMPLE_DEPTH)-1:0] addr; - reg [TOTAL_PROBE_WIDTH-1:0] sample; - - assign done = (addr >= SAMPLE_DEPTH); - - initial begin - $readmemb(MEM_FILE, capture, 0, SAMPLE_DEPTH-1); - addr = 0; - end - - always @(posedge clk) begin - if (enable && !done) begin - addr = addr + 1; - sample = capture[addr]; - {ein, ed, valentine, jet, spike} = sample; - end - end -endmodule \ No newline at end of file diff --git a/examples/nexys_a7/logic_analyzer_uart/sim/playback_tb.sv b/examples/nexys_a7/logic_analyzer_uart/sim/playback_tb.sv deleted file mode 100644 index d89ace9..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/sim/playback_tb.sv +++ /dev/null @@ -1,38 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module playback_tb(); - logic clk; - - always begin - #5; - clk = !clk; - end - - logic spike; - logic [1:0] jet; - logic [2:0] valentine; - logic [3:0] ed; - logic [4:0] ein; - - my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst ( - .clk(clk), - .enable(1'b1), - - .spike(spike), - .jet(jet), - .valentine(valentine), - .ed(ed), - .ein(ein)); - - initial begin - clk = 0; - $dumpfile("playback_tb.vcd"); - $dumpvars(0, playback_tb); - - #(450000*5); - $finish(); - end - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/logic_analyzer_uart/src/top_level.sv b/examples/nexys_a7/logic_analyzer_uart/src/top_level.sv deleted file mode 100644 index 2127b3d..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/src/top_level.sv +++ /dev/null @@ -1,28 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire uart_txd_in, - output logic uart_rxd_out - ); - - logic [4:0] counter = 0; - always @(posedge clk) counter <= counter + 1; - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .spike(counter[0]), - .jet(counter[1:0]), - .valentine(counter[2:0]), - .ed(counter[3:0]), - .ein(counter)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/logic_analyzer_uart/xdc/top_level.xdc b/examples/nexys_a7/logic_analyzer_uart/xdc/top_level.xdc deleted file mode 100644 index 81c1998..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/ps2_logic_analyzer/manta.yaml b/examples/nexys_a7/ps2_logic_analyzer/manta.yaml deleted file mode 100644 index c2d1e5f..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/manta.yaml +++ /dev/null @@ -1,18 +0,0 @@ ---- -cores: - my_logic_analyzer: - type: logic_analyzer - sample_depth: 64000 - trigger_location: 15000 - - probes: - ps2_clk: 1 - ps2_data: 1 - - triggers: - - ps2_data FALLING - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 50000000 \ No newline at end of file diff --git a/examples/nexys_a7/ps2_logic_analyzer/sim/playback.v b/examples/nexys_a7/ps2_logic_analyzer/sim/playback.v deleted file mode 100644 index acf7d73..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/sim/playback.v +++ /dev/null @@ -1,52 +0,0 @@ -/* -This playback module was generated with Manta v0.0.5 on 19 Jul 2023 at 18:52:11 by fischerm - -If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! - -my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst ( - .clk(clk), - .enable(1'b1), - - .ps2_clk(ps2_clk), - .ps2_data(ps2_data)); - -*/ - - -module my_logic_analyzer_playback ( - input wire clk, - - input wire enable, - output reg done, - - output reg ps2_clk, - output reg ps2_data); - - parameter MEM_FILE = ""; - localparam SAMPLE_DEPTH = 64000; - localparam TOTAL_PROBE_WIDTH = 2; - - reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0]; - reg [$clog2(SAMPLE_DEPTH)-1:0] addr; - reg [TOTAL_PROBE_WIDTH-1:0] sample; - - assign done = (addr >= SAMPLE_DEPTH); - - initial begin - $readmemb(MEM_FILE, capture, 0, SAMPLE_DEPTH-1); - addr = 0; - end - - always @(posedge clk) begin - if (enable && !done) begin - addr = addr + 1; - sample = capture[addr]; - {ps2_data, ps2_clk} = sample; - end - end -endmodule \ No newline at end of file diff --git a/examples/nexys_a7/ps2_logic_analyzer/sim/playback_tb.sv b/examples/nexys_a7/ps2_logic_analyzer/sim/playback_tb.sv deleted file mode 100644 index 7116fb8..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/sim/playback_tb.sv +++ /dev/null @@ -1,80 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module ps2_decoder( - input wire clk, - - input wire ps2_clk, - input wire ps2_data, - - output logic [7:0] data - ); - - reg prev_clk; - reg [10:0] buffer = 0; - reg [3:0] counter = 0; - - always @(posedge clk) begin - prev_clk <= ps2_clk; - - if (!prev_clk && ps2_clk) begin - buffer <= {buffer[9:0], ps2_data}; - counter <= counter + 1; - end - - if (counter == 11) begin - if (!buffer[10] && buffer[0]) begin - counter <= 0; - data <= {buffer[2], buffer[3], buffer[4], buffer[5], buffer[6], buffer[7], buffer[8], buffer[9]}; - end - end - - end - -endmodule - -module playback_tb(); - logic clk; - - always begin - #5; - clk = !clk; - end - - logic ps2_clk; - logic ps2_data; - - my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst ( - .clk(clk), - .enable(1'b1), - - .ps2_clk(ps2_clk), - .ps2_data(ps2_data)); - - logic [7:0] data; - - ps2_decoder decoder( - .clk(clk), - - .ps2_clk(ps2_clk), - .ps2_data(ps2_data), - - .data(data) - ); - - initial begin - clk = 0; - $dumpfile("playback_tb.vcd"); - $dumpvars(0, playback_tb); - - #(450000*5); - $finish(); - end - -endmodule - - - - - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/ps2_logic_analyzer/src/top_level.sv b/examples/nexys_a7/ps2_logic_analyzer/src/top_level.sv deleted file mode 100644 index b54ef17..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/src/top_level.sv +++ /dev/null @@ -1,25 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire ps2_clk, - input wire ps2_data, - - input wire uart_txd_in, - output logic uart_rxd_out - ); - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .ps2_clk(ps2_clk), - .ps2_data(ps2_data)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/ps2_logic_analyzer/xdc/top_level.xdc b/examples/nexys_a7/ps2_logic_analyzer/xdc/top_level.xdc deleted file mode 100644 index 81c1998..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/video_sprite_ether/img/buff_doge.png b/examples/nexys_a7/video_sprite_ether/img/buff_doge.png deleted file mode 100644 index d504d02..0000000 Binary files a/examples/nexys_a7/video_sprite_ether/img/buff_doge.png and /dev/null differ diff --git a/examples/nexys_a7/video_sprite_ether/img/no_testbenches.png b/examples/nexys_a7/video_sprite_ether/img/no_testbenches.png deleted file mode 100644 index 52ce7a5..0000000 Binary files a/examples/nexys_a7/video_sprite_ether/img/no_testbenches.png and /dev/null differ diff --git a/examples/nexys_a7/video_sprite_ether/img/pop_cat.png b/examples/nexys_a7/video_sprite_ether/img/pop_cat.png deleted file mode 100644 index 629e6f9..0000000 Binary files a/examples/nexys_a7/video_sprite_ether/img/pop_cat.png and /dev/null differ diff --git a/examples/nexys_a7/video_sprite_ether/manta.yaml b/examples/nexys_a7/video_sprite_ether/manta.yaml deleted file mode 100644 index 2bbc757..0000000 --- a/examples/nexys_a7/video_sprite_ether/manta.yaml +++ /dev/null @@ -1,10 +0,0 @@ ---- -cores: - image_mem: - type: block_memory - width: 12 - depth: 16384 - -ethernet: - interface: "en8" - host_mac: "12:34:56:78:90:ab" \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_ether/send_image.py b/examples/nexys_a7/video_sprite_ether/send_image.py deleted file mode 100644 index 20b7fee..0000000 --- a/examples/nexys_a7/video_sprite_ether/send_image.py +++ /dev/null @@ -1,37 +0,0 @@ -import sys -from PIL import Image, ImageOps - -if __name__ == "__main__": - if len(sys.argv) < 2: - print("Usage: {0} ".format(sys.argv[0])) - - else: - input_fname = sys.argv[1] - image_in = Image.open(input_fname) - image_in = image_in.convert('RGB') - - # Resize the image - image_in = image_in.resize((128, 128)) - image_out = image_in.copy() - w, h = image_in.size - - # Take input image and divide each color channel's value by 16 - for y in range(h): - for x in range(w): - r, g, b = image_in.getpixel((x, y)) - image_out.putpixel((x,y), (r//16, g//16, b//16)) - - - # Save the image itself - pixels = [] - for y in range(h): - for x in range(w): - (r, g, b) = image_out.getpixel((x,y)) - color = (r*16*16) + (g*16) + (b) - pixels.append(color) - - from manta import Manta - m = Manta('manta.yaml') - - addrs = list(range(len(pixels))) - m.image_mem.write(addrs, pixels) \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_ether/src/clk_gen.v b/examples/nexys_a7/video_sprite_ether/src/clk_gen.v deleted file mode 100644 index 91d4265..0000000 --- a/examples/nexys_a7/video_sprite_ether/src/clk_gen.v +++ /dev/null @@ -1,207 +0,0 @@ - -// file: clk_gen.v -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_50mhz__50.00000______0.000______50.0______150.541_____99.281 -// clk_65mhz__65.00000______0.000______50.0______142.278_____99.281 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_________100.000____________0.010 - -`timescale 1ps/1ps - -module clk_gen - - (// Clock in ports - // Clock out ports - output clk_50mhz, - output clk_65mhz, - input clk_100mhz - ); - // Input buffering - //------------------------------------ -wire clk_100mhz_clk_gen; -wire clk_in2_clk_gen; - IBUF clkin1_ibufg - (.O (clk_100mhz_clk_gen), - .I (clk_100mhz)); - - - - - // Clocking PRIMITIVE - //------------------------------------ - - // Instantiation of the MMCM PRIMITIVE - // * Unused inputs are tied off - // * Unused outputs are labeled unused - - wire clk_50mhz_clk_gen; - wire clk_65mhz_clk_gen; - wire clk_out3_clk_gen; - wire clk_out4_clk_gen; - wire clk_out5_clk_gen; - wire clk_out6_clk_gen; - wire clk_out7_clk_gen; - - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_int; - wire clkfbout_clk_gen; - wire clkfbout_buf_clk_gen; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (9.750), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (19.500), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (15), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (10.000)) - mmcm_adv_inst - // Output clocks - ( - .CLKFBOUT (clkfbout_clk_gen), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (clk_50mhz_clk_gen), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clk_65mhz_clk_gen), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout_buf_clk_gen), - .CLKIN1 (clk_100mhz_clk_gen), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (1'b0)); - -// Clock Monitor clock assigning -//-------------------------------------- - // Output buffering - //----------------------------------- - - BUFG clkf_buf - (.O (clkfbout_buf_clk_gen), - .I (clkfbout_clk_gen)); - - - - - - - BUFG clkout1_buf - (.O (clk_50mhz), - .I (clk_50mhz_clk_gen)); - - - BUFG clkout2_buf - (.O (clk_65mhz), - .I (clk_65mhz_clk_gen)); - - - -endmodule diff --git a/examples/nexys_a7/video_sprite_ether/src/top_level.sv b/examples/nexys_a7/video_sprite_ether/src/top_level.sv deleted file mode 100644 index c1023db..0000000 --- a/examples/nexys_a7/video_sprite_ether/src/top_level.sv +++ /dev/null @@ -1,108 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module top_level ( - input wire clk_100mhz, - - output reg eth_refclk, - output reg eth_rstn, - - input wire eth_crsdv, - input wire [1:0] eth_rxd, - - output reg eth_txen, - output reg [1:0] eth_txd, - - output logic [3:0] vga_r, vga_g, vga_b, - output logic vga_hs, vga_vs); - - assign eth_rstn = 1; - - // Clock generation - logic clk_50mhz; - logic clk_65mhz; - assign eth_refclk = clk_50mhz; - - clk_gen gen( - .clk_100mhz(clk_100mhz), - .clk_50mhz(clk_50mhz), - .clk_65mhz(clk_65mhz)); - - // VGA signals - logic [10:0] hcount; - logic [9:0] vcount; - logic hsync, vsync, blank; - - vga vga_gen( - .pixel_clk_in(clk_65mhz), - .hcount_out(hcount), - .vcount_out(vcount), - .hsync_out(hsync), - .vsync_out(vsync), - .blank_out(blank)); - - // VGA Pipelining - reg[1:0][10:0] hcount_pipe; - reg[1:0][10:0] vcount_pipe; - reg[1:0] hsync_pipe; - reg[1:0] vsync_pipe; - reg[1:0] blank_pipe; - - always_ff @(posedge clk_65mhz)begin - hcount_pipe[0] <= hcount; - vcount_pipe[0] <= vcount; - hsync_pipe[0] <= hsync; - vsync_pipe[0] <= vsync; - blank_pipe[0] <= blank; - for (int i=1; i<2; i = i+1)begin - hcount_pipe[i] <= hcount_pipe[i-1]; - vcount_pipe[i] <= vcount_pipe[i-1]; - hsync_pipe[i] <= hsync_pipe[i-1]; - vsync_pipe[i] <= vsync_pipe[i-1]; - blank_pipe[i] <= blank_pipe[i-1]; - end - end - - localparam WIDTH = 128; - localparam HEIGHT = 128; - - localparam X = 0; - localparam Y = 0; - - // calculate rom address - logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr; - assign image_addr = (hcount - X) + ((vcount - Y) * WIDTH); - - logic in_sprite; - assign in_sprite = ((hcount_pipe[1] >= X && hcount_pipe[1] < (X + WIDTH)) && - (vcount_pipe[1] >= Y && vcount_pipe[1] < (Y + HEIGHT))); - - manta manta_inst ( - .clk(clk_50mhz), - - .crsdv(eth_crsdv), - .rxd(eth_rxd), - .txen(eth_txen), - .txd(eth_txd), - - .image_mem_clk(clk_65mhz), - .image_mem_addr(image_addr), - .image_mem_din(), - .image_mem_dout(sprite_color), - .image_mem_we(1'b0)); - - logic [11:0] sprite_color; - logic [11:0] color; - assign color = in_sprite ? sprite_color : 12'h0; - - // the following lines are required for the Nexys4 VGA circuit - do not change - assign vga_r = ~blank_pipe[1] ? color[11:8]: 0; - assign vga_g = ~blank_pipe[1] ? color[7:4] : 0; - assign vga_b = ~blank_pipe[1] ? color[3:0] : 0; - - assign vga_hs = ~hsync_pipe[1]; - assign vga_vs = ~vsync_pipe[1]; - - -endmodule -`default_nettype wire diff --git a/examples/nexys_a7/video_sprite_ether/src/vga.sv b/examples/nexys_a7/video_sprite_ether/src/vga.sv deleted file mode 100644 index 3fa787f..0000000 --- a/examples/nexys_a7/video_sprite_ether/src/vga.sv +++ /dev/null @@ -1,68 +0,0 @@ - -/* vga: Generate VGA display signals (1024 x 768 @ 60Hz) - * - * ---- HORIZONTAL ----- ------VERTICAL ----- - * Active Active - * Freq Video FP Sync BP Video FP Sync BP - * 640x480, 60Hz 25.175 640 16 96 48 480 11 2 31 - * 800x600, 60Hz 40.000 800 40 128 88 600 1 4 23 - * 1024x768, 60Hz 65.000 1024 24 136 160 768 3 6 29 - * 1280x1024, 60Hz 108.00 1280 48 112 248 768 1 3 38 - * 1280x720p 60Hz 75.25 1280 72 80 216 720 3 5 30 - * 1920x1080 60Hz 148.5 1920 88 44 148 1080 4 5 36 - * - * change the clock frequency, front porches, sync's, and back porches to create - * other screen resolutions - */ - -module vga( - input wire pixel_clk_in, - output logic [10:0] hcount_out, // pixel number on current line - output logic [9:0] vcount_out, // line number - output logic vsync_out, hsync_out, - output logic blank_out); - - parameter DISPLAY_WIDTH = 1024; // display width - parameter DISPLAY_HEIGHT = 768; // number of lines - - parameter H_FP = 24; // horizontal front porch - parameter H_SYNC_PULSE = 136; // horizontal sync - parameter H_BP = 160; // horizontal back porch - - parameter V_FP = 3; // vertical front porch - parameter V_SYNC_PULSE = 6; // vertical sync - parameter V_BP = 29; // vertical back porch - - // horizontal: 1344 pixels total - // display 1024 pixels per line - logic hblank,vblank; - logic hsyncon,hsyncoff,hreset,hblankon; - assign hblankon = (hcount_out == (DISPLAY_WIDTH -1)); - assign hsyncon = (hcount_out == (DISPLAY_WIDTH + H_FP - 1)); //1047 - assign hsyncoff = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE - 1)); // 1183 - assign hreset = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE + H_BP - 1)); //1343 - - // vertical: 806 lines total - // display 768 lines - logic vsyncon,vsyncoff,vreset,vblankon; - assign vblankon = hreset & (vcount_out == (DISPLAY_HEIGHT - 1)); // 767 - assign vsyncon = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP - 1)); // 771 - assign vsyncoff = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE - 1)); // 777 - assign vreset = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE + V_BP - 1)); // 805 - - // sync and blanking - logic next_hblank,next_vblank; - assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank; - assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank; - always_ff @(posedge pixel_clk_in) begin - hcount_out <= hreset ? 0 : hcount_out + 1; - hblank <= next_hblank; - hsync_out <= hsyncon ? 0 : hsyncoff ? 1 : hsync_out; // active low - - vcount_out <= hreset ? (vreset ? 0 : vcount_out + 1) : vcount_out; - vblank <= next_vblank; - vsync_out <= vsyncon ? 0 : vsyncoff ? 1 : vsync_out; // active low - - blank_out <= next_vblank | (next_hblank & ~hreset); - end -endmodule \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_ether/xdc/top_level.xdc b/examples/nexys_a7/video_sprite_ether/xdc/top_level.xdc deleted file mode 100644 index 8a3551b..0000000 --- a/examples/nexys_a7/video_sprite_ether/xdc/top_level.xdc +++ /dev/null @@ -1,253 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; - - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] - -set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] - -set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_uart/img/buff_doge.png b/examples/nexys_a7/video_sprite_uart/img/buff_doge.png deleted file mode 100644 index d504d02..0000000 Binary files a/examples/nexys_a7/video_sprite_uart/img/buff_doge.png and /dev/null differ diff --git a/examples/nexys_a7/video_sprite_uart/img/no_testbenches.png b/examples/nexys_a7/video_sprite_uart/img/no_testbenches.png deleted file mode 100644 index 52ce7a5..0000000 Binary files a/examples/nexys_a7/video_sprite_uart/img/no_testbenches.png and /dev/null differ diff --git a/examples/nexys_a7/video_sprite_uart/img/pop_cat.png b/examples/nexys_a7/video_sprite_uart/img/pop_cat.png deleted file mode 100644 index 629e6f9..0000000 Binary files a/examples/nexys_a7/video_sprite_uart/img/pop_cat.png and /dev/null differ diff --git a/examples/nexys_a7/video_sprite_uart/manta.yaml b/examples/nexys_a7/video_sprite_uart/manta.yaml deleted file mode 100644 index a1d285d..0000000 --- a/examples/nexys_a7/video_sprite_uart/manta.yaml +++ /dev/null @@ -1,11 +0,0 @@ ---- -cores: - image_mem: - type: block_memory - width: 12 - depth: 16384 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 65000000 \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_uart/send_image.py b/examples/nexys_a7/video_sprite_uart/send_image.py deleted file mode 100644 index 20b7fee..0000000 --- a/examples/nexys_a7/video_sprite_uart/send_image.py +++ /dev/null @@ -1,37 +0,0 @@ -import sys -from PIL import Image, ImageOps - -if __name__ == "__main__": - if len(sys.argv) < 2: - print("Usage: {0} ".format(sys.argv[0])) - - else: - input_fname = sys.argv[1] - image_in = Image.open(input_fname) - image_in = image_in.convert('RGB') - - # Resize the image - image_in = image_in.resize((128, 128)) - image_out = image_in.copy() - w, h = image_in.size - - # Take input image and divide each color channel's value by 16 - for y in range(h): - for x in range(w): - r, g, b = image_in.getpixel((x, y)) - image_out.putpixel((x,y), (r//16, g//16, b//16)) - - - # Save the image itself - pixels = [] - for y in range(h): - for x in range(w): - (r, g, b) = image_out.getpixel((x,y)) - color = (r*16*16) + (g*16) + (b) - pixels.append(color) - - from manta import Manta - m = Manta('manta.yaml') - - addrs = list(range(len(pixels))) - m.image_mem.write(addrs, pixels) \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_uart/src/clk_gen.v b/examples/nexys_a7/video_sprite_uart/src/clk_gen.v deleted file mode 100644 index 91d4265..0000000 --- a/examples/nexys_a7/video_sprite_uart/src/clk_gen.v +++ /dev/null @@ -1,207 +0,0 @@ - -// file: clk_gen.v -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_50mhz__50.00000______0.000______50.0______150.541_____99.281 -// clk_65mhz__65.00000______0.000______50.0______142.278_____99.281 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_________100.000____________0.010 - -`timescale 1ps/1ps - -module clk_gen - - (// Clock in ports - // Clock out ports - output clk_50mhz, - output clk_65mhz, - input clk_100mhz - ); - // Input buffering - //------------------------------------ -wire clk_100mhz_clk_gen; -wire clk_in2_clk_gen; - IBUF clkin1_ibufg - (.O (clk_100mhz_clk_gen), - .I (clk_100mhz)); - - - - - // Clocking PRIMITIVE - //------------------------------------ - - // Instantiation of the MMCM PRIMITIVE - // * Unused inputs are tied off - // * Unused outputs are labeled unused - - wire clk_50mhz_clk_gen; - wire clk_65mhz_clk_gen; - wire clk_out3_clk_gen; - wire clk_out4_clk_gen; - wire clk_out5_clk_gen; - wire clk_out6_clk_gen; - wire clk_out7_clk_gen; - - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_int; - wire clkfbout_clk_gen; - wire clkfbout_buf_clk_gen; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (9.750), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (19.500), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (15), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (10.000)) - mmcm_adv_inst - // Output clocks - ( - .CLKFBOUT (clkfbout_clk_gen), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (clk_50mhz_clk_gen), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clk_65mhz_clk_gen), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout_buf_clk_gen), - .CLKIN1 (clk_100mhz_clk_gen), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (1'b0)); - -// Clock Monitor clock assigning -//-------------------------------------- - // Output buffering - //----------------------------------- - - BUFG clkf_buf - (.O (clkfbout_buf_clk_gen), - .I (clkfbout_clk_gen)); - - - - - - - BUFG clkout1_buf - (.O (clk_50mhz), - .I (clk_50mhz_clk_gen)); - - - BUFG clkout2_buf - (.O (clk_65mhz), - .I (clk_65mhz_clk_gen)); - - - -endmodule diff --git a/examples/nexys_a7/video_sprite_uart/src/top_level.sv b/examples/nexys_a7/video_sprite_uart/src/top_level.sv deleted file mode 100644 index 01645fd..0000000 --- a/examples/nexys_a7/video_sprite_uart/src/top_level.sv +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module top_level ( - input wire clk_100mhz, - - input wire uart_txd_in, - output logic uart_rxd_out, - - output logic [3:0] vga_r, vga_g, vga_b, - output logic vga_hs, vga_vs); - - // Clock generation - logic clk_65mhz; - - clk_gen gen( - .clk_100mhz(clk_100mhz), - .clk_50mhz(), - .clk_65mhz(clk_65mhz)); - - // VGA signals - logic [10:0] hcount; - logic [9:0] vcount; - logic hsync, vsync, blank; - - vga vga_gen( - .pixel_clk_in(clk_65mhz), - .hcount_out(hcount), - .vcount_out(vcount), - .hsync_out(hsync), - .vsync_out(vsync), - .blank_out(blank)); - - // VGA Pipelining - reg[1:0][10:0] hcount_pipe; - reg[1:0][10:0] vcount_pipe; - reg[1:0] hsync_pipe; - reg[1:0] vsync_pipe; - reg[1:0] blank_pipe; - - always_ff @(posedge clk_65mhz)begin - hcount_pipe[0] <= hcount; - vcount_pipe[0] <= vcount; - hsync_pipe[0] <= hsync; - vsync_pipe[0] <= vsync; - blank_pipe[0] <= blank; - for (int i=1; i<2; i = i+1)begin - hcount_pipe[i] <= hcount_pipe[i-1]; - vcount_pipe[i] <= vcount_pipe[i-1]; - hsync_pipe[i] <= hsync_pipe[i-1]; - vsync_pipe[i] <= vsync_pipe[i-1]; - blank_pipe[i] <= blank_pipe[i-1]; - end - end - - localparam WIDTH = 128; - localparam HEIGHT = 128; - - localparam X = 0; - localparam Y = 0; - - // calculate rom address - logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr; - assign image_addr = (hcount - X) + ((vcount - Y) * WIDTH); - - logic in_sprite; - assign in_sprite = ((hcount_pipe[1] >= X && hcount_pipe[1] < (X + WIDTH)) && - (vcount_pipe[1] >= Y && vcount_pipe[1] < (Y + HEIGHT))); - - manta manta_inst ( - .clk(clk_65mhz), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .image_mem_clk(clk_65mhz), - .image_mem_addr(image_addr), - .image_mem_din(), - .image_mem_dout(sprite_color), - .image_mem_we(1'b0)); - - logic [11:0] sprite_color; - logic [11:0] color; - assign color = in_sprite ? sprite_color : 12'h0; - - // the following lines are required for the Nexys4 VGA circuit - do not change - assign vga_r = ~blank_pipe[1] ? color[11:8]: 0; - assign vga_g = ~blank_pipe[1] ? color[7:4] : 0; - assign vga_b = ~blank_pipe[1] ? color[3:0] : 0; - - assign vga_hs = ~hsync_pipe[1]; - assign vga_vs = ~vsync_pipe[1]; - - -endmodule -`default_nettype wire diff --git a/examples/nexys_a7/video_sprite_uart/src/vga.sv b/examples/nexys_a7/video_sprite_uart/src/vga.sv deleted file mode 100644 index 3fa787f..0000000 --- a/examples/nexys_a7/video_sprite_uart/src/vga.sv +++ /dev/null @@ -1,68 +0,0 @@ - -/* vga: Generate VGA display signals (1024 x 768 @ 60Hz) - * - * ---- HORIZONTAL ----- ------VERTICAL ----- - * Active Active - * Freq Video FP Sync BP Video FP Sync BP - * 640x480, 60Hz 25.175 640 16 96 48 480 11 2 31 - * 800x600, 60Hz 40.000 800 40 128 88 600 1 4 23 - * 1024x768, 60Hz 65.000 1024 24 136 160 768 3 6 29 - * 1280x1024, 60Hz 108.00 1280 48 112 248 768 1 3 38 - * 1280x720p 60Hz 75.25 1280 72 80 216 720 3 5 30 - * 1920x1080 60Hz 148.5 1920 88 44 148 1080 4 5 36 - * - * change the clock frequency, front porches, sync's, and back porches to create - * other screen resolutions - */ - -module vga( - input wire pixel_clk_in, - output logic [10:0] hcount_out, // pixel number on current line - output logic [9:0] vcount_out, // line number - output logic vsync_out, hsync_out, - output logic blank_out); - - parameter DISPLAY_WIDTH = 1024; // display width - parameter DISPLAY_HEIGHT = 768; // number of lines - - parameter H_FP = 24; // horizontal front porch - parameter H_SYNC_PULSE = 136; // horizontal sync - parameter H_BP = 160; // horizontal back porch - - parameter V_FP = 3; // vertical front porch - parameter V_SYNC_PULSE = 6; // vertical sync - parameter V_BP = 29; // vertical back porch - - // horizontal: 1344 pixels total - // display 1024 pixels per line - logic hblank,vblank; - logic hsyncon,hsyncoff,hreset,hblankon; - assign hblankon = (hcount_out == (DISPLAY_WIDTH -1)); - assign hsyncon = (hcount_out == (DISPLAY_WIDTH + H_FP - 1)); //1047 - assign hsyncoff = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE - 1)); // 1183 - assign hreset = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE + H_BP - 1)); //1343 - - // vertical: 806 lines total - // display 768 lines - logic vsyncon,vsyncoff,vreset,vblankon; - assign vblankon = hreset & (vcount_out == (DISPLAY_HEIGHT - 1)); // 767 - assign vsyncon = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP - 1)); // 771 - assign vsyncoff = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE - 1)); // 777 - assign vreset = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE + V_BP - 1)); // 805 - - // sync and blanking - logic next_hblank,next_vblank; - assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank; - assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank; - always_ff @(posedge pixel_clk_in) begin - hcount_out <= hreset ? 0 : hcount_out + 1; - hblank <= next_hblank; - hsync_out <= hsyncon ? 0 : hsyncoff ? 1 : hsync_out; // active low - - vcount_out <= hreset ? (vreset ? 0 : vcount_out + 1) : vcount_out; - vblank <= next_vblank; - vsync_out <= vsyncon ? 0 : vsyncoff ? 1 : vsync_out; // active low - - blank_out <= next_vblank | (next_hblank & ~hreset); - end -endmodule \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc b/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc deleted file mode 100644 index 817beb0..0000000 --- a/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc +++ /dev/null @@ -1,253 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; - - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] - -set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] - -set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file diff --git a/pyproject.toml b/pyproject.toml index 949089d..8e9b9e9 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,12 +1,13 @@ [project] -name = "mantaray" -version = "0.0.5" +name = "manta" +version = "0.1.0" authors = [ { name="Fischer Moseley", email="fischerm@mit.edu" }, ] description = "An In-Situ Debugging Tool for Programmable Hardware" readme = "README.md" dependencies = [ + "amaranth[builtin-yosys]@git+https://github.com/amaranth-lang/amaranth", "PyYAML", "pyserial", "pyvcd", @@ -15,6 +16,14 @@ dependencies = [ requires-python = ">=3.7" +[project.optional-dependencies] +dev = [ + "pytest", + "black", + "mkdocs-material", + "amaranth_boards@git+https://github.com/amaranth-lang/amaranth-boards" +] + [project.urls] "Homepage" = "https://github.com/fischermoseley/manta" @@ -24,9 +33,6 @@ manta = "manta:main" [tool.setuptools.packages.find] where = ["src"] -[tool.setuptools.package-data] -manta = ["**/*.v"] - [build-system] requires = ["setuptools"] build-backend = "setuptools.build_meta" \ No newline at end of file diff --git a/src/manta/__init__.py b/src/manta/__init__.py index 587e4d8..60b9f60 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -1,385 +1,5 @@ -# Internal Dependencies -from .utils import * -from .la_core import * -from .io_core import * -from .block_mem_core import * - -# External Dependencies -from sys import argv -import os -from datetime import datetime -from pkg_resources import get_distribution - -class Manta: - def __init__(self, config_filepath): - config = self.read_config_file(config_filepath) - - # set interface - if "uart" in config: - from .uart_iface import UARTInterface - self.interface = UARTInterface(config["uart"]) - - elif "ethernet" in config: - from .ether_iface import EthernetInterface - self.interface = EthernetInterface(config["ethernet"]) - - else: - raise ValueError("Unrecognized interface specified.") - - # check that cores were provided - assert "cores" in config, "No cores found." - assert len(config["cores"]) > 0, "Must specify at least one core." - - # add cores to self - base_addr = 0 - self.cores = [] - for i, core_name in enumerate(config["cores"]): - core = config["cores"][core_name] - - # make sure a type was specified for this core - assert "type" in core, f"No type specified for core {core_name}." - - # add the core to ourself - if core["type"] == "logic_analyzer": - new_core = LogicAnalyzerCore(core, core_name, base_addr, self.interface) - - elif core["type"] == "io": - new_core = IOCore(core, core_name, base_addr, self.interface) - - elif core["type"] == "block_memory": - new_core = BlockMemoryCore(core, core_name, base_addr, self.interface) - - else: - raise ValueError(f"Unrecognized core type specified for {core_name}.") - - # make sure we're not out of address space - assert new_core.max_addr < (2**16)-1, f"Ran out of address space to allocate to core {core_name}." - - # make the next core's base address start one address after the previous one's - base_addr = new_core.max_addr + 1 - - # add friendly name, so users can do Manta.my_logic_analyzer.read() for example - setattr(self, core_name, new_core) - self.cores.append(new_core) - - def read_config_file(self, path): - """Take path to configuration file, and retun the configuration as a python list/dict object.""" - extension = path.split(".")[-1] - - if "json" in extension: - with open(path, "r") as f: - import json - - config = json.load(f) - - elif "yaml" in extension or "yml" in extension: - with open(path, "r") as f: - import yaml - - config = yaml.safe_load(f) - - else: - raise ValueError("Unable to recognize configuration file extension.") - - return config - - def gen_connections(self): - # generates hdl for registers that connect two modules together - - # make pairwise cores - core_pairs = [(self.cores[i - 1], self.cores[i]) for i in range(1, len(self.cores))] - - conns = [] - for core_pair in core_pairs: - src = core_pair[0].name - dst = core_pair[1].name - - hdl = f"reg [15:0] {src}_{dst}_addr;\n" - hdl += f"reg [15:0] {src}_{dst}_data;\n" - hdl += f"reg {src}_{dst}_rw;\n" - hdl += f"reg {src}_{dst}_valid;\n" - conns.append(hdl) - - return conns - - def gen_instances(self): - # generates hdl for modules that need to be connected together - - insts = [] - for i, core in enumerate(self.cores): - # should probably check if core is LogicAnalyzerCore or IOCore - - hdl = core.hdl_inst() - - # connect input - if (i == 0): - src_name = "brx" - - else: - src_name = self.cores[i-1].name - - hdl = hdl.replace(".addr_i()", f".addr_i({src_name}_{core.name}_addr)") - hdl = hdl.replace(".data_i()", f".data_i({src_name}_{core.name}_data)") - hdl = hdl.replace(".rw_i()", f".rw_i({src_name}_{core.name}_rw)") - hdl = hdl.replace(".valid_i()", f".valid_i({src_name}_{core.name}_valid)") - - - - # connect output - if (i < len(self.cores)-1): - dst_name = self.cores[i+1].name - hdl = hdl.replace(".addr_o()", f".addr_o({core.name}_{dst_name}_addr)") - - else: - dst_name = "btx" - - hdl = hdl.replace(".data_o()", f".data_o({core.name}_{dst_name}_data)") - hdl = hdl.replace(".rw_o()", f".rw_o({core.name}_{dst_name}_rw)") - hdl = hdl.replace(".valid_o()", f".valid_o({core.name}_{dst_name}_valid)") - - insts.append(hdl) - - return insts - - def gen_core_chain(self): - insts = self.gen_instances() - conns = self.gen_connections() - core_chain = [] - for i, inst in enumerate(insts): - core_chain.append(inst) - - if (i != len(insts)-1): - core_chain.append(conns[i]) - - return '\n'.join(core_chain) - - def gen_example_inst_ports(self): - # this is a C-style block comment that contains an instantiation - # of the configured manta instance - the idea is that a user - # can copy-paste that into their design instead of trying to spot - # the difference between their code and the autogenerated code. - - # hopefully this saves time! - - - # this turns a list like ['input wire foo', 'output reg bar'] into - # a nice string like ".foo(foo),\n .bar(bar)" - interface_ports = self.interface.hdl_top_level_ports() - interface_ports = [port.split(',')[0] for port in interface_ports] - interface_ports = [port.split(' ')[-1] for port in interface_ports] - interface_ports = [f".{port}({port}),\n" for port in interface_ports] - interface_ports = "".join(interface_ports) - - core_chain_ports = [] - for core in self.cores: - ports = [port.split(',')[0] for port in core.hdl_top_level_ports()] - ports = [port.split(' ')[-1] for port in ports] - ports = [f".{port}({port}), \n" for port in ports] - ports = "".join(ports) - ports = "\n" + ports - core_chain_ports.append(ports) - - core_chain_ports = "\n".join(core_chain_ports) - - ports = interface_ports + core_chain_ports - - # remove trailing comma - ports = ports.rstrip() - if ports[-1] == ",": - ports = ports[:-1] - - return ports - - def gen_top_level_ports(self): - # get all the top level connections for each module. - - interface_ports = self.interface.hdl_top_level_ports() - interface_ports = [f"{port},\n" for port in interface_ports] - interface_ports = "".join(interface_ports) + "\n" - - core_chain_ports = [] - for core in self.cores: - ports = [f"{port},\n" for port in core.hdl_top_level_ports()] - ports = "".join(ports) - core_chain_ports.append(ports) - - core_chain_ports = "\n".join(core_chain_ports) - - ports = interface_ports + core_chain_ports - - # remove trailing comma - ports = ports.rstrip() - if ports[-1] == ",": - ports = ports[:-1] - - return ports - - def gen_interface_rx(self): - # instantiate interface_rx, substitute in register names - interface_rx_inst = self.interface.rx_hdl_inst() - - interface_rx_inst = interface_rx_inst.replace("addr_o()", f"addr_o(brx_{self.cores[0].name}_addr)") - interface_rx_inst = interface_rx_inst.replace("data_o()", f"data_o(brx_{self.cores[0].name}_data)") - interface_rx_inst = interface_rx_inst.replace("rw_o()", f"rw_o(brx_{self.cores[0].name}_rw)") - interface_rx_inst = interface_rx_inst.replace("valid_o()", f"valid_o(brx_{self.cores[0].name}_valid)") - - # connect interface_rx to core_chain - interface_rx_conn= f""" -reg [15:0] brx_{self.cores[0].name}_addr; -reg [15:0] brx_{self.cores[0].name}_data; -reg brx_{self.cores[0].name}_rw; -reg brx_{self.cores[0].name}_valid;\n""" - - return interface_rx_inst + interface_rx_conn - - def gen_interface_tx(self): - - # connect core_chain to interface_tx - interface_tx_conn = f""" -reg [15:0] {self.cores[-1].name}_btx_data; -reg {self.cores[-1].name}_btx_rw; -reg {self.cores[-1].name}_btx_valid;\n""" - - # instantiate interface_tx, substitute in register names - interface_tx_inst = self.interface.tx_hdl_inst() - - interface_tx_inst = interface_tx_inst.replace("addr_i()", f"addr_i({self.cores[-1].name}_btx_addr)") - interface_tx_inst = interface_tx_inst.replace("data_i()", f"data_i({self.cores[-1].name}_btx_data)") - interface_tx_inst = interface_tx_inst.replace("rw_i()", f"rw_i({self.cores[-1].name}_btx_rw)") - interface_tx_inst = interface_tx_inst.replace("valid_i()", f"valid_i({self.cores[-1].name}_btx_valid)") - - return interface_tx_conn + interface_tx_inst - - def gen_module_defs(self): - # aggregate module definitions and remove duplicates - module_defs_with_dups = [self.interface.rx_hdl_def()] + [core.hdl_def() for core in self.cores] + [self.interface.tx_hdl_def()] - module_defs = [] - module_defs = [m_def for m_def in module_defs_with_dups if m_def not in module_defs] - module_defs = [m_def.strip() for m_def in module_defs] - return '\n\n'.join(module_defs) - - def generate_hdl(self, output_filepath): - manta = VerilogManipulator("manta_def_tmpl.v") - - version = "v" + get_distribution('mantaray').version - manta.sub(version, "/* VERSION */") - - timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S") - manta.sub(timestamp, "/* TIMESTAMP */") - - user = os.environ.get("USER", os.environ.get("USERNAME")) - manta.sub(user, "/* USER */") - - ex_inst_ports = self.gen_example_inst_ports() - manta.sub(ex_inst_ports, "/* EX_INST_PORTS */") - - top_level_ports = self.gen_top_level_ports() - manta.sub(top_level_ports, "/* TOP_LEVEL_PORTS */") - - interface_rx = self.gen_interface_rx() - manta.sub(interface_rx, "/* INTERFACE_RX */") - - core_chain = self.gen_core_chain() - manta.sub(core_chain, "/* CORE_CHAIN */") - - interface_tx = self.gen_interface_tx() - manta.sub(interface_tx, "/* INTERFACE_TX */") - - module_defs = self.gen_module_defs() - manta.sub(module_defs, "/* MODULE_DEFS */") - - manta.hdl = "`timescale 1ns/1ps\n" + manta.hdl - manta.hdl = "`default_nettype none\n"+ manta.hdl - manta.hdl = manta.hdl + "\n`default_nettype wire" - - return manta.get_hdl() - -def main(): - # print help menu if no args passed or help menu requested - - if len(argv) == 1 or argv[1] == "help" or argv[1] == "ray" or argv[1] == "bae": - version = "v" + get_distribution('mantaray').version - print( - f""" -\033[96m (\.-./) -\033[96m / \\ -\033[96m .' : '. -\033[96m _.-'` ' `'-._ \033[34;49;1m | \033[34;49;1m Manta {version} \033[00m -\033[96m .-' : '-. \033[34;49;1m | \033[34;49;3m An In-Situ Debugging Tool for Programmable Hardware \033[00m -\033[96m ,'_.._ . _.._', \033[34;49;1m | \033[34;49m https://github.com/fischermoseley/manta \033[00m -\033[96m '` `'-. ' .-'` -\033[96m '. : .' \033[34;49;1m | \033[34;49;3m fischerm [at] mit.edu \033[00m -\033[96m \_. ._/ -\033[96m \ |^| -\033[96m | | ; -\033[96m \\'.___.' / -\033[96m '-....-' \033[00m - -Supported commands: - gen [config_file] [verilog_file] generate a verilog file specifying the Manta module from a given configuration file, and save to the provided path - capture [config_file] [LA_core_name] [vcd_file] [mem_file] start a capture on the specified core, and save the results to a .mem or .vcd file at the provided path(s) - playback [config file] [LA_core_name] [verilog_file] generate a verilog module that plays back a capture from a given logic analyzer core, and save to the provided path - ports list all available serial ports - help, ray display this splash screen (hehe...splash screen) -""" - ) - - # list available serial ports - elif argv[1] == "ports": - import serial.tools.list_ports - for port in serial.tools.list_ports.comports(): - print(port) - - # sometimes macOS will enumerate non-serial devices as serial ports, - # in which case the PID/VID/serial/location/etc are all None - pid = f"0x{port.vid:04X}" if port.pid is not None else "None" - vid = f"0x{port.vid:04X}" if port.vid is not None else "None" - - print(f" -> pid: {pid}") - print(f" -> vid: {vid}") - print(f" -> ser: {port.serial_number}") - print(f" -> loc: {port.location}") - print(f" -> mftr: {port.manufacturer}") - print(f" -> prod: {port.product}") - print(f" -> desc: {port.description}\n") - - # generate the specified configuration - elif argv[1] == "gen": - assert len(argv) == 4, "Wrong number of arguments, run 'manta help' for proper usage." - - m = Manta(argv[2]) - hdl = m.generate_hdl(argv[3]) - with open(argv[3], "w") as f: - f.write(hdl) - - # run the specified core - elif argv[1] == "capture": - assert len(argv) >= 5, "Wrong number of arguments, run 'manta help' for proper usage." - - m = Manta(argv[2]) - la = getattr(m, argv[3]) - data = la.capture() - - for path in argv[4:]: - if ".vcd" in path: - la.export_vcd(data, path) - - elif ".mem" in path: - la.export_mem(data, path) - - else: - print(f"Warning: Unknown output file format for {path}, skipping...") - - elif argv[1] == "playback": - assert len(argv) == 5, "Wrong number of arguments, run 'manta help' for proper usage." - - m = Manta(argv[2]) - la = getattr(m, argv[3]) - la.export_playback_module(argv[4]) - - else: - print("Option not recognized, run 'manta help' for proper usage.") - +from .manta import Manta +from .cli import main if __name__ == "__main__": main() diff --git a/src/manta/__main__.py b/src/manta/__main__.py index b23d9a5..4e28416 100644 --- a/src/manta/__main__.py +++ b/src/manta/__main__.py @@ -1,3 +1,3 @@ -import manta +from .cli import main -manta.main() +main() diff --git a/src/manta/block_mem_core/__init__.py b/src/manta/block_mem_core/__init__.py deleted file mode 100644 index dbe841c..0000000 --- a/src/manta/block_mem_core/__init__.py +++ /dev/null @@ -1,77 +0,0 @@ -from ..utils import * - -from math import ceil, log2 - -class BlockMemoryCore: - def __init__(self, config, name, base_addr, interface): - self.name = name - self.base_addr = base_addr - self.interface = interface - - # Warn if unrecognized options have been given - for option in config: - if option not in ["type", "depth", "width", "expose_port"]: - print(f"Warning: Ignoring unrecognized option '{option}' in Block Memory core '{self.name}'") - - # Determine if we expose the BRAM's second port to the top of the module - if "expose_port" in config: - assert isinstance(config["expose_port"], bool), "Configuring BRAM exposure must be done with a boolean." - self.expose_port = config["expose_port"] - - else: - self.expose_port = True - - # Get depth - assert "depth" in config, "Depth not specified for Block Memory core." - assert config["depth"] > 0, "Block Memory core must have positive depth." - assert isinstance(config["depth"], int), "Block Memory core must have integer depth." - self.depth = config["depth"] - - # Get width - assert "width" in config, "Width not specified for Block Memory core." - assert config["width"] > 0, "Block Memory core must have positive width." - assert isinstance(config["width"], int), "Block Memory core must have integer width." - self.width = config["width"] - - self.addr_width = ceil(log2(self.depth)) - self.n_brams = ceil(self.width / 16) - self.max_addr = self.base_addr + (self.depth * self.n_brams) - - def hdl_inst(self): - inst = VerilogManipulator("block_mem_core/block_memory_inst_tmpl.v") - inst.sub(self.name, "/* INST_NAME */") - inst.sub(self.depth, "/* DEPTH */") - inst.sub(self.width, "/* WIDTH */") - return inst.get_hdl() - - def hdl_def(self): - block_memory = VerilogManipulator("block_mem_core/block_memory.v").get_hdl() - dual_port_bram = VerilogManipulator("block_mem_core/dual_port_bram.v").get_hdl() - return block_memory + "\n" + dual_port_bram - - def hdl_top_level_ports(self): - if not self.expose_port: - return "" - - tlp = [] - tlp.append(f"input wire {self.name}_clk") - tlp.append(f"input wire [{self.addr_width-1}:0] {self.name}_addr") - tlp.append(f"input wire [{self.width-1}:0] {self.name}_din") - tlp.append(f"output reg [{self.width-1}:0] {self.name}_dout") - tlp.append(f"input wire {self.name}_we") - return tlp - - def get_physical_addr(self, addr): - if isinstance(addr, int): - return addr + self.base_addr - - elif isinstance(addr, list): - return [a + self.base_addr for a in addr] - - raise ValueError("Read address must be integer or list of integers.") - - def read(self, addr): - return self.interface.read(self.get_physical_addr(addr)) - - def write(self, addr, data): - return self.interface.write(self.get_physical_addr(addr), data) \ No newline at end of file diff --git a/src/manta/block_mem_core/block_memory.v b/src/manta/block_mem_core/block_memory.v deleted file mode 100644 index ae00f17..0000000 --- a/src/manta/block_mem_core/block_memory.v +++ /dev/null @@ -1,114 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module block_memory ( - input wire clk, - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o, - - // BRAM itself - input wire user_clk, - input wire [ADDR_WIDTH-1:0] user_addr, - input wire [WIDTH-1:0] user_din, - output reg [WIDTH-1:0] user_dout, - input wire user_we); - - parameter BASE_ADDR = 0; - parameter WIDTH = 0; - parameter DEPTH = 0; - localparam ADDR_WIDTH = $clog2(DEPTH); - - // ugly typecasting, but just computes ceil(WIDTH / 16) - localparam N_BRAMS = int'($ceil(real'(WIDTH) / 16.0)); - localparam MAX_ADDR = BASE_ADDR + (DEPTH * N_BRAMS); - - // Port A of BRAMs - reg [N_BRAMS-1:0][ADDR_WIDTH-1:0] addra = 0; - reg [N_BRAMS-1:0][15:0] dina = 0; - reg [N_BRAMS-1:0][15:0] douta; - reg [N_BRAMS-1:0] wea = 0; - - // Port B of BRAMs - reg [N_BRAMS-1:0][15:0] dinb; - reg [N_BRAMS-1:0][15:0] doutb; - assign dinb = user_din; - - // kind of a hack to part select from a 2d array that's been flattened to 1d - reg [(N_BRAMS*16)-1:0] doutb_flattened; - assign doutb_flattened = doutb; - assign user_dout = doutb_flattened[WIDTH-1:0]; - - // Pipelining - reg [2:0][15:0] addr_pipe = 0; - reg [2:0][15:0] data_pipe = 0; - reg [2:0] valid_pipe = 0; - reg [2:0] rw_pipe = 0; - - always @(posedge clk) begin - addr_pipe[0] <= addr_i; - data_pipe[0] <= data_i; - valid_pipe[0] <= valid_i; - rw_pipe[0] <= rw_i; - - addr_o <= addr_pipe[2]; - data_o <= data_pipe[2]; - valid_o <= valid_pipe[2]; - rw_o <= rw_pipe[2]; - - for(int i=1; i<3; i=i+1) begin - addr_pipe[i] <= addr_pipe[i-1]; - data_pipe[i] <= data_pipe[i-1]; - valid_pipe[i] <= valid_pipe[i-1]; - rw_pipe[i] <= rw_pipe[i-1]; - end - - // throw BRAM operations into the front of the pipeline - wea <= 0; - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= MAX_ADDR)) begin - wea[(addr_i - BASE_ADDR) % N_BRAMS] <= rw_i; - addra[(addr_i - BASE_ADDR) % N_BRAMS] <= (addr_i - BASE_ADDR) / N_BRAMS; - dina[(addr_i - BASE_ADDR) % N_BRAMS] <= data_i; - end - - // pull BRAM reads from the back of the pipeline - if( (valid_pipe[2]) && (addr_pipe[2] >= BASE_ADDR) && (addr_pipe[2] <= MAX_ADDR)) begin - data_o <= douta[(addr_pipe[2] - BASE_ADDR) % N_BRAMS]; - end - end - - // generate the BRAMs - genvar i; - generate - for(i=0; i pid: {pid}") + print(f" -> vid: {vid}") + print(f" -> ser: {port.serial_number}") + print(f" -> loc: {port.location}") + print(f" -> mftr: {port.manufacturer}") + print(f" -> prod: {port.product}") + print(f" -> desc: {port.description}\n") + + +def main(): + if len(argv) == 1: + help() + + elif argv[1] in ["help", "-h", "-help", "--help", "ray"]: + help() + + elif argv[1] == "gen": + if len(argv) != 4: + wrong_args() + gen(argv[2], argv[3]) + + elif argv[1] == "capture": + if len(argv) < 5: + wrong_args() + capture(argv[2], argv[3], argv[4]) + + elif argv[1] == "playback": + if len(argv) != 5: + wrong_args() + playback(argv[2], argv[3], argv[4]) + + elif argv[1] == "mmap": + if len(argv) != 3: + wrong_args() + mmap(argv[2]) + + elif argv[1] == "ports": + ports() + + else: + wrong_args() + + +if __name__ == "__main__": + main() diff --git a/src/manta/ether_iface/__init__.py b/src/manta/ether_iface/__init__.py deleted file mode 100644 index 042bffe..0000000 --- a/src/manta/ether_iface/__init__.py +++ /dev/null @@ -1,208 +0,0 @@ -from ..utils import * - -# Lazy and selective imports for quick builds! -from scapy.interfaces import get_if_list -from scapy.arch import get_if_hwaddr -from scapy.layers.l2 import Ether -from scapy.sendrecv import AsyncSniffer, sendp, sendpfast -from time import sleep - -from scapy.all import * - -class EthernetInterface: - def __init__(self, config): - # Warn if unrecognized options have been given - for option in config: - if option not in ["interface", "host_mac", "fpga_mac", "ethertype", "tcpreplay", "verbose"]: - print(f"Warning: Ignoring unrecognized option '{option}' in Ethernet interface.") - - # Obtain interface. - assert "interface" in config, "No interface provided for Ethernet core." - if config["interface"] not in get_if_list(): - print(f"Warning: Interface specified is not detected by the host.") - self.iface = config["interface"] - - # Obtain Host MAC address - if self.iface in get_if_list(): - self.host_mac = get_if_hwaddr(self.iface) - else: - assert "host_mac" in config, \ - "Can't automatically detect host mac address from interface, host_mac must be manually provided" - self.host_mac = config["host_mac"] - - # Obtain FPGA MAC address - # - the default address is a locally administered unicast address, - # which is an important distinction. please refer to: - # https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses - self.fpga_mac = "12:34:56:78:9A:BC" - if "fpga_mac" in config: - self.fpga_mac = config["fpga_mac"] - - # Obtain Ethertype - # - the default ethertype being used is reserved for local - # experimentation by the IEEE - and might not make it beyond - # your NIC as a result. - self.ethertype = 0x88B5 - if "ethertype" in config: - self.ethertype = int(config["ethertype"], 16) - - # Set whether we use tcpreplay for faster packet blasting - if "tcpreplay" in config: - assert isinstance(config["tcpreplay"], bool), \ - "tcpreplay configuration option must be boolean!" - - if config["tcpreplay"]: - self.send_packets = lambda p: sendpfast(p, iface=self.iface) - - else: - self.send_packets = lambda p: sendp(p, iface=self.iface, verbose=0) - - else: - self.send_packets = lambda p: sendp(p, iface=self.iface, verbose=0) - - - self.verbose = False - if "verbose" in config: - assert isinstance(config["verbose"], bool), \ - "verbose configuration option must be boolean!" - self.verbose = config["verbose"] - - def read(self, addr): - # Perform type checks, output list of addresses - if isinstance(addr, int): - addrs = [addr] - - elif isinstance(addr, list): - assert all(isinstance(a, int) for a in addr), \ - "Read addresses must be integer or list of integers." - addrs = addr - - else: - raise ValueError("Read addresses must be integer or list of integers.") - - # Prepare packets with read requests - request_pkts = [] - for a in addrs: - pkt = Ether() - pkt.src = self.host_mac - pkt.dst = self.fpga_mac - pkt.type = self.ethertype - - # one byte of rw, two bytes of address, and 44 of padding - # makes the 46 byte minimum length - msg = b'\x00' + a.to_bytes(2, 'big') + 43*b'\x00' - - pkt = pkt / msg - pkt.load = msg - request_pkts.append(pkt) - - # Start sniffer in another thread, send packets, grab responses - sniffer = AsyncSniffer(iface = self.iface, count = len(addrs), filter=f"ether src {self.fpga_mac}") - sniffer.start() - sleep(0.5) - self.send_packets(request_pkts) - sniffer.join() - response_pkts = sniffer.results - assert len(response_pkts) == len(request_pkts), "Received wrong number of packets!" - - # Get read data by pulling bytes 3 and 4 from the returned packets - # payload, and interpreting it as big endian - get_read_data = lambda x: int.from_bytes(bytes(x.payload)[3:5], 'big') - read_data = [get_read_data(pkt) for pkt in response_pkts] - - if len(read_data) == 1: - return read_data[0] - - else: - return read_data - - def write(self, addr, data): - # Perform type checks, output list of addresses - if isinstance(addr, int): - assert isinstance(data, int), \ - "Data must also be integer if address is integer." - addrs = [addr] - datas = [data] - - elif isinstance(addr, list): - assert all(isinstance(a, int) for a in addr), \ - "Write addresses must be integer or list of integers." - - assert all(isinstance(d, int) for d in data), \ - "Write data must be integer or list of integers." - - assert len(addr) == len(data), \ - "There must be equal number of write addresses and data." - - addrs = addr - datas = data - - else: - raise ValueError("Write addresses and data must be integer or list of integers.") - - # Prepare packets with write requests - request_pkts = [] - for a, d in zip(addrs, datas): - pkt = Ether() - pkt.src = self.host_mac - pkt.dst = self.fpga_mac - pkt.type = self.ethertype - - # one byte of rw, two bytes of address, two bytes of data, and 42 of padding - # makes the 46 byte minimum length - msg = b'\x01' + a.to_bytes(2, 'big') + d.to_bytes(2, 'big') + 41*b'\x00' - - pkt = pkt / msg - pkt.load = msg - request_pkts.append(pkt) - - self.send_packets(request_pkts) - - def hdl_top_level_ports(self): - return ["input wire crsdv", \ - "input wire [1:0] rxd", \ - "output reg txen", \ - "output reg [1:0] txd"] - - def rx_hdl_def(self): - tx = VerilogManipulator("ether_iface/ethernet_rx.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/mac_rx.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/ether.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/bitorder.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/firewall.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/aggregate.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/crc32.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/cksum.v").get_hdl() + "\n" - return tx - - def tx_hdl_def(self): - tx = VerilogManipulator("ether_iface/ethernet_tx.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/mac_tx.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/bitorder.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/crc32.v").get_hdl() + "\n" - return tx - - def rx_hdl_inst(self): - rx = VerilogManipulator("ether_iface/ethernet_rx_inst_tmpl.v") - - fpga_mac_verilog_literal = "48'h" + self.fpga_mac.replace(":", "_").upper() - rx.sub(fpga_mac_verilog_literal, "/* FPGA_MAC */") - - ethertype_verilog_literal = f"16'h{self.ethertype:02X}" - rx.sub(ethertype_verilog_literal, "/* ETHERTYPE */") - - return rx.get_hdl() - - def tx_hdl_inst(self): - tx = VerilogManipulator("ether_iface/ethernet_tx_inst_tmpl.v") - - fpga_mac_verilog_literal = "48'h" + self.fpga_mac.replace(":", "_").upper() - tx.sub(fpga_mac_verilog_literal, "/* FPGA_MAC */") - - host_mac_verilog_literal = "48'h" + self.host_mac.replace(":", "_").upper() - tx.sub(host_mac_verilog_literal, "/* HOST_MAC */") - - ethertype_verilog_literal = f"16'h{self.ethertype:02X}" - tx.sub(ethertype_verilog_literal, "/* ETHERTYPE */") - - return tx.get_hdl() \ No newline at end of file diff --git a/src/manta/ether_iface/aggregate.v b/src/manta/ether_iface/aggregate.v deleted file mode 100644 index aad4e53..0000000 --- a/src/manta/ether_iface/aggregate.v +++ /dev/null @@ -1,46 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -/* Aggregates the first 64 bits of an incoming - * Ethernet transmission (thus shedding the FCS - * and anything else extraneous) and outputs the - * first 32 bits on an AXI bus for a single cycle. - * If the packet is not at least 64 bits long, - * nothing happens - */ - -`define AGR_MAX 56 -`define AGR_SHOW 64 - -module aggregate ( - input wire clk, - input wire [1:0] axiid, - input wire axiiv, - - output reg [55:0] axiod, - output reg axiov); - - /* A quick and dirty counter. As long as this is below - * 32, we'll dump packets into the AXI output data buffer. - * Once the counter gets to AGR_MAX, we'll assert AXI valid. - * Then we'll hang until axiiv drops - */ - - reg [31:0] counter; - - assign axiov = counter == `AGR_SHOW; - - always @(posedge clk) begin: COUNTER - if (!axiiv) counter <= 32'b0; - else counter <= counter + 2; - end - - always @(posedge clk) begin: AXIOD - if (!axiiv) axiod <= 32'b0; - else if (counter < `AGR_MAX && axiiv) - axiod[`AGR_MAX - counter - 2 +: 2] <= axiid; - end - -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/bitorder.v b/src/manta/ether_iface/bitorder.v deleted file mode 100644 index e7ca283..0000000 --- a/src/manta/ether_iface/bitorder.v +++ /dev/null @@ -1,114 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`define BO_SENDA 2'b00 -`define BO_SENDB 2'b01 -`define BO_EMPTYA 2'b10 -`define BO_EMPTYB 2'b11 - -module bitorder ( - input wire clk, - - input wire axiiv, - input wire [1:0] axiid, - - output reg [1:0] axiod, - output reg axiov); - - /* Two registers to hold data coming in off the wire, - * byte by byte. This is where we'll buffer until - * we've received a byte of data, at which point - * we'll start sending out the byte in the correct - * order using one register. Meanwhile, we'll start - * receiving into the other register - dual buffers. - */ - reg [7:0] bufa = 8'b0; - reg [7:0] bufb = 8'b0; - - /* A counter. This indicates what 'stage' we're in, - * and always refers to the index we're reading into - * in the receiving buffer or sending out of in the - * sending buffer - */ - reg [2:0] countera = 3'b0; - reg [2:0] counterb = 3'b0; - - /* Which state we're in - should we be using buffer - * A to send, buffer B to send, or neither because - * we've just come out of reset? - */ - reg [1:0] state = `BO_EMPTYB; - initial axiov = 0; - initial axiod = 0; - - always @(*) begin: AXIOV - if (state == `BO_SENDA || state == `BO_SENDB) axiov = 1'b1; - else axiov = 1'b0; - end - - always @(*) begin: AXIOD - if (state == `BO_SENDA) axiod = bufa[countera +: 2]; - else if (state == `BO_SENDB) axiod = bufb[counterb +: 2]; - else axiod = 1'b0; - end - - always @(posedge clk) begin: BUFFERIN - if (axiiv) begin - case (state) - `BO_EMPTYB, `BO_SENDB: - bufa[countera +: 2] <= axiid; - `BO_EMPTYA, `BO_SENDA: - bufb[counterb +: 2] <= axiid; - endcase - end - - else if (state == `BO_EMPTYB || state == `BO_EMPTYA) begin - bufa <= 8'b0; - bufb <= 8'b0; - end - end - - always @(posedge clk) begin: STATES - case (state) - `BO_EMPTYB: begin - if (axiiv) begin - if (countera == 3'h6) - state <= `BO_SENDA; - else countera <= countera + 2; - end else countera <= 3'b0; - end - - `BO_EMPTYA: begin - if (axiiv) begin - if (counterb == 3'h6) - state <= `BO_SENDB; - else counterb <= counterb + 2; - end else counterb <= 3'b0; - end - - `BO_SENDB: begin - if (counterb == 3'h0) state <= `BO_EMPTYB; - else counterb <= counterb - 2; - - if (axiiv) begin - if (countera == 3'h6) - state <= `BO_SENDA; - else countera <= countera + 2; - end - end - - `BO_SENDA: begin - if (countera == 3'h0) state <= `BO_EMPTYA; - else countera <= countera - 2; - - if (axiiv) begin - if (counterb == 3'h6) - state <= `BO_SENDB; - else counterb <= counterb + 2; - end - end - endcase - end -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/cksum.v b/src/manta/ether_iface/cksum.v deleted file mode 100644 index a1b823b..0000000 --- a/src/manta/ether_iface/cksum.v +++ /dev/null @@ -1,80 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -/* Computes the ethernet checksum - * The following combinations of `done` and `kill` - * represent the state of the module: - * - * - done = 0, kill = 0: processing data or freshly reset - * - done = 1, kill = 0: correct ethernet checksum verified - * - done = 1, kill = 1: data valid set to zero before correct - * checksum value computed, therefore bad checksum - * - done = 0, kill = 1: never asserted - * - * the done and/or kill signals are asserted high beginning - * the cycle after input data ceases, and until new data - * is received via the AXI input - */ - -`define CK_FRESH 2'b00 -`define CK_COMPUTING 2'b01 -`define CK_DONE 2'b10 - -`define MAGIC_CHECK 32'h38_fb_22_84 - -module cksum ( - input wire clk, - input wire [1:0] axiid, - input wire axiiv, - - output reg done, - output reg kill); - - reg [31:0] crcd; - reg crcv; - - /* Decoupled logic to reset the CRC module independently - * Used to compute multiple CRCs back to back - */ - reg crcrst; - - reg [1:0] state = `CK_FRESH; - initial done = 0; - initial kill = 0; - initial crcrst = 0; - - crc32 cksum( - .clk(clk), - .rst(crcrst), - .axiiv(axiiv), - .axiid(axiid), - .axiov(crcv), - .axiod(crcd)); - - always @(posedge clk) begin: OUTPUTS - if (axiiv) begin - done <= 1'b0; - kill <= 1'b0; - crcrst <= 1'b0; - end else begin - if (state == `CK_COMPUTING && !axiiv) begin - done <= 1'b1; - crcrst <= 1'b1; - kill <= (crcd != `MAGIC_CHECK); - end - - else crcrst <= 1'b0; - end - end - - always @(posedge clk) begin: FSM - case (state) - `CK_FRESH: if (axiiv) state <= `CK_COMPUTING; - `CK_COMPUTING: if (!axiiv) state <= `CK_DONE; - `CK_DONE: if (axiiv) state <= `CK_COMPUTING; - endcase - end - -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/crc32.v b/src/manta/ether_iface/crc32.v deleted file mode 100644 index 51e4397..0000000 --- a/src/manta/ether_iface/crc32.v +++ /dev/null @@ -1,70 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`define LAGGING_SHIFT_IN (caxiod[30] ^ axiid[1]) -`define LEADING_SHIFT_IN (caxiod[31] ^ axiid[0]) -`define DOUBLED_SHIFT_IN (`LEADING_SHIFT_IN ^ `LAGGING_SHIFT_IN) - -`define LAGGING_TAPS 4, 7, 10, 16, 22, 26 -`define DOUBLED_TAPS 2, 5, 8, 11, 12, 23 -`define LEADING_TAPS 3, 6, 9, 13, 17, 24, 27 - -/* this module implements CRC32-BZIP2, with a two bit input: - * - poly 0x04C11DB7 - * - init 0xFFFFFFFF - * - NEW: XOR outputs - * - * == check: 0xfc891918 == - * - * this is the ethernet checksum!! - */ - -module crc32( - input wire clk, - input wire rst, - input wire axiiv, - input wire [1:0] axiid, - - output reg axiov, - output reg [31:0] axiod); - - reg [31:0] caxiod, saxiod; - initial caxiod = 32'hFFFF_FFFF; - integer i; - - assign axiov = 1; - assign axiod = ~caxiod; - - always @(*) begin - for (i = 0; i < 32; i = i + 1) begin - case (i) - 0: saxiod[i] = `LAGGING_SHIFT_IN; - 1: saxiod[i] = `DOUBLED_SHIFT_IN; - - `LAGGING_TAPS: - saxiod[i] = caxiod[i - 2] ^ `LAGGING_SHIFT_IN; - `DOUBLED_TAPS: - saxiod[i] = caxiod[i - 2] ^ `DOUBLED_SHIFT_IN; - `LEADING_TAPS: - saxiod[i] = caxiod[i - 2] ^ `LEADING_SHIFT_IN; - - default: saxiod[i] = caxiod[i - 2]; - endcase - end - end - - always @(posedge clk) begin - if (rst) caxiod <= 32'hFFFF_FFFF; - - /* our output validity hinges on whether - * we are calculating anything or not - * on this clock cycle. if there is no - * valid input for us, don't do a shift - * this cycle - */ - else caxiod <= (axiiv) ? saxiod : caxiod; - end - -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/ether.v b/src/manta/ether_iface/ether.v deleted file mode 100644 index 56ad986..0000000 --- a/src/manta/ether_iface/ether.v +++ /dev/null @@ -1,77 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`define EF_IDLE 3'b000 -`define EF_PREAM 3'b001 -`define EF_DATA 3'b011 -`define EF_BAD 3'b101 - -`define PREAM_BITS 64 -`define PREAM_SIZE (`PREAM_BITS / 2) - -`define PREAM_FIRST 2'b00 -`define PREAM_EXPECT 2'b01 -`define PREAM_LAST 2'b11 -`define PREAM_BAD 2'b10 - -module ether ( - input wire clk, - input wire [1:0] rxd, - input wire crsdv, - - output reg axiov, - output reg [1:0] axiod); - - reg [4:0] count; - reg [2:0] state; - - reg [1:0] preamex; - reg preamok, start; - - always @(*) begin: PREAM - if (count == `PREAM_SIZE - 1) preamex = `PREAM_LAST; - else preamex = `PREAM_EXPECT; - - preamok = crsdv && rxd == preamex; - end - - always @(*) start = crsdv && rxd != `PREAM_FIRST; - - always @(posedge clk) begin: COUNT - if (state == `EF_PREAM) count <= count + 1; - else if (state == `EF_IDLE && start) count <= count + 1; - else count <= 0; - end - - initial begin - axiod = 2'b0; - axiov = 1'b0; - state = 3'b0; - end - - always @(posedge clk) begin: FSM - case (state) - `EF_BAD: if (!crsdv) state <= `EF_IDLE; - `EF_IDLE: if (start) state <= `EF_PREAM; - - `EF_PREAM: begin - if (!preamok || !crsdv) state <= `EF_BAD; - else if (count == `PREAM_SIZE - 1) - state <= `EF_DATA; - end - - `EF_DATA: begin - if (crsdv) begin - axiov <= 1'b1; - axiod <= rxd; - end else begin - axiov <= 1'b0; - axiod <= 2'b0; - state <= `EF_IDLE; - end - end - endcase - end -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/ethernet_rx.v b/src/manta/ether_iface/ethernet_rx.v deleted file mode 100644 index ba36ec7..0000000 --- a/src/manta/ether_iface/ethernet_rx.v +++ /dev/null @@ -1,41 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module ethernet_rx ( - input wire clk, - - input wire crsdv, - input wire [1:0] rxd, - - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o - ); - - parameter FPGA_MAC = 0; - parameter ETHERTYPE = 0; - - reg [55:0] payload; - reg valid; - - mac_rx #( - .FPGA_MAC(FPGA_MAC), - .ETHERTYPE(ETHERTYPE) - ) mrx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .payload(payload), - .valid(valid)); - - assign rw_o = (payload[39:32] == 8'd1); - assign addr_o = payload[31:16]; - assign data_o = payload[15:0]; - assign valid_o = valid && ( payload[39:32] == 8'd0 || payload[39:32] == 8'd1) && (payload[55:40] == 16'h88B5); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/ether_iface/ethernet_rx_inst_tmpl.v b/src/manta/ether_iface/ethernet_rx_inst_tmpl.v deleted file mode 100644 index 7eae02b..0000000 --- a/src/manta/ether_iface/ethernet_rx_inst_tmpl.v +++ /dev/null @@ -1,13 +0,0 @@ -ethernet_rx #( - .FPGA_MAC(/* FPGA_MAC */), - .ETHERTYPE(/* ETHERTYPE */) -) erx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .addr_o(), - .data_o(), - .rw_o(), - .valid_o()); \ No newline at end of file diff --git a/src/manta/ether_iface/ethernet_tx.v b/src/manta/ether_iface/ethernet_tx.v deleted file mode 100644 index 318b3ba..0000000 --- a/src/manta/ether_iface/ethernet_tx.v +++ /dev/null @@ -1,40 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module ethernet_tx ( - input wire clk, - - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - output reg txen, - output reg [1:0] txd - ); - - parameter FPGA_MAC = 0; - parameter HOST_MAC = 0; - parameter ETHERTYPE = 0; - - reg [15:0] data_buf = 0; - - always @(posedge clk) - if(~rw_i && valid_i) data_buf <= data_i; - - mac_tx #( - .SRC_MAC(FPGA_MAC), - .DST_MAC(HOST_MAC), - .ETHERTYPE(ETHERTYPE), - .PAYLOAD_LENGTH_BYTES(5) - ) mtx ( - .clk(clk), - - .payload({24'd0, data_buf}), - .start(~rw_i && valid_i), - - .txen(txen), - .txd(txd)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/ether_iface/ethernet_tx_inst_tmpl.v b/src/manta/ether_iface/ethernet_tx_inst_tmpl.v deleted file mode 100644 index 6082910..0000000 --- a/src/manta/ether_iface/ethernet_tx_inst_tmpl.v +++ /dev/null @@ -1,13 +0,0 @@ -ethernet_tx #( - .FPGA_MAC(/* FPGA_MAC */), - .HOST_MAC(/* HOST_MAC */), - .ETHERTYPE(/* ETHERTYPE */) -) etx ( - .clk(clk), - - .data_i(), - .rw_i(), - .valid_i(), - - .txen(txen), - .txd(txd)); \ No newline at end of file diff --git a/src/manta/ether_iface/firewall.v b/src/manta/ether_iface/firewall.v deleted file mode 100644 index 611e310..0000000 --- a/src/manta/ether_iface/firewall.v +++ /dev/null @@ -1,80 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`define FW_DESTSTART 0 -`define FW_DESTEND (`FW_DESTSTART + 48) - -`define FW_DATASTART (48 + 48) - -module firewall ( - input wire clk, - input wire axiiv, - input wire [1:0] axiid, - - output reg axiov, - output reg [1:0] axiod); - - parameter ETHERTYPE = 0; - parameter FPGA_MAC = 0; - - /* Buffers to hold our MAC address in the reverse order, - * to make comparison easier than it otherwise would be - */ - reg [0:47] me; - - /* A counter, to determine whether we should be comparing - * with a MAC address or stripping off data - */ - reg [31:0] counter; - - /* An internal set of flags to mark whether the currently - * traversing packet is valid, i.e we should forward data, - * or not. One of these flags tracks whether the destination - * MAC address matches _our_ (FW_ME) mac address, the other - * tracks whether the destination matches the broadcast - * (FW_BCAST) MAC. If either one of these is high once the - * destination MAC finishes rolling through, the packet - * is forwarded. - */ - reg matchme, matchbcast; - - assign me = FPGA_MAC; - - always @(posedge clk) begin: MATCH - if (counter == 32'b0) begin - matchme <= 1'b1; - matchbcast <= 1'b1; - end - - /* could overwrite the above, which is ideal if - * FW_DESTSTART == 0 (it is) and we have a mismatch - * out the gate - */ - if (counter >= `FW_DESTSTART && counter < `FW_DESTEND) begin - if (axiiv) begin - if (axiid != {me[counter], me[counter + 1]}) - matchme <= 1'b0; - if (axiid != 2'b11) - matchbcast <= 1'b0; - end - end - end - - always @(*) begin: AXIOUT - if (counter >= `FW_DATASTART && (matchme | matchbcast)) begin - axiod = axiid; - axiov = axiiv; - end else begin - axiod = 2'b00; - axiov = 1'b0; - end - end - - always @(posedge clk) begin: COUNTER - if (axiiv) counter <= counter + 2; - else counter <= 32'b0; - end - -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/mac_rx.v b/src/manta/ether_iface/mac_rx.v deleted file mode 100644 index 46ff330..0000000 --- a/src/manta/ether_iface/mac_rx.v +++ /dev/null @@ -1,106 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module mac_rx ( - input wire clk, - - input wire crsdv, - input wire [1:0] rxd, - - output reg [55:0] payload, - output reg valid); - - parameter FPGA_MAC = 0; - parameter ETHERTYPE = 0; - - reg [1:0] ether_axiod; - reg ether_axiov; - - ether e ( - .clk(clk), - .rxd(rxd), - .crsdv(crsdv), - .axiov(ether_axiov), - .axiod(ether_axiod)); - - reg [1:0] bitorder_axiod; - reg bitorder_axiov; - - bitorder b ( - .clk(clk), - .axiiv(ether_axiov), - .axiid(ether_axiod), - .axiov(bitorder_axiov), - .axiod(bitorder_axiod)); - - reg [1:0] firewall_axiod; - reg firewall_axiov; - - firewall #( - .FPGA_MAC(FPGA_MAC), - .ETHERTYPE(ETHERTYPE) - ) f ( - .clk(clk), - .axiiv(bitorder_axiov), - .axiid(bitorder_axiod), - .axiov(firewall_axiov), - .axiod(firewall_axiod)); - - reg [55:0] aggregate_axiod; - reg aggregate_axiov; - - aggregate a ( - .clk(clk), - .axiiv(firewall_axiov), - .axiid(firewall_axiod), - .axiov(aggregate_axiov), - .axiod(aggregate_axiod)); - - reg cksum_done; - reg cksum_kill; - - cksum c ( - .clk(clk), - .axiiv(ether_axiov), - .axiid(ether_axiod), - .done(cksum_done), - .kill(cksum_kill)); - - // state machine - localparam IDLE = 0; - localparam WAIT_FOR_DATA = 1; - localparam WAIT_FOR_FCS = 2; - - reg [1:0] state = IDLE; - - initial valid = 0; - initial payload = 0; - - always @(posedge clk) begin - valid <= 0; - - if(state == IDLE) begin - if(crsdv) state <= WAIT_FOR_DATA; - end - - else if(state == WAIT_FOR_DATA) begin - if(aggregate_axiov) begin - state <= WAIT_FOR_FCS; - payload <= aggregate_axiod; - end - - // if aggregate never gives us data, - // go back to idle when the packet ends - else if(cksum_done) state <= IDLE; - end - - else if(state == WAIT_FOR_FCS) begin - if(cksum_done) begin - state <= IDLE; - valid <= ~cksum_kill; - end - end - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/ether_iface/mac_tx.v b/src/manta/ether_iface/mac_tx.v deleted file mode 100644 index 812c078..0000000 --- a/src/manta/ether_iface/mac_tx.v +++ /dev/null @@ -1,242 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module mac_tx ( - input wire clk, - - input wire [(8 * PAYLOAD_LENGTH_BYTES)-1:0] payload, - input wire start, - - output reg txen, - output reg [1:0] txd); - - // packet magic numbers - localparam PREAMBLE = {7{8'b01010101}}; - localparam SFD = 8'b11010101; - parameter [47:0] SRC_MAC = 0; - parameter [47:0] DST_MAC = 0; - parameter [15:0] ETHERTYPE = 0; - parameter PAYLOAD_LENGTH_BYTES = 0; - - // all lengths are in units of dibits, hence all the mulitplies by four - localparam PREAMBLE_LEN = 7 * 4; - localparam SFD_LEN = 1 * 4; - localparam SRC_MAC_LEN = 6 * 4; - localparam DST_MAC_LEN = 6 * 4; - localparam ETHERTYPE_LEN = 2 * 4; - localparam PAYLOAD_LEN = PAYLOAD_LENGTH_BYTES * 4; - localparam ZERO_PAD_LEN = (46 * 4) - PAYLOAD_LEN + 4; // minimum payload size is 46 bytes - localparam FCS_LEN = 4 * 4; - localparam IPG_LEN = 96 / 2; - - reg [1:0] bitorder_axiid; - reg [1:0] bitorder_axiod; - reg bitorder_axiiv; - reg bitorder_axiov; - - bitorder bitorder ( - .clk(clk), - - .axiiv(bitorder_axiiv), - .axiid(bitorder_axiid), - - .axiov(bitorder_axiov), - .axiod(bitorder_axiod)); - - reg crc_rst = 1; - reg crc_axiiv = 0; - reg [31:0] crc_axiod; - - crc32 crc ( - .clk(clk), - .rst(crc_rst), - - .axiiv(crc_axiiv), - .axiid(bitorder_axiod), - - // TODO: remove axiov from crc32 module, it's always valid - .axiov(), - .axiod(crc_axiod)); - - - // state machine - reg [8:0] counter = 0; - reg [3:0] state = 0; - - localparam IDLE_STATE = 0; - localparam PREAMBLE_STATE = 1; - localparam SFD_STATE = 2; - localparam DST_MAC_STATE = 3; - localparam SRC_MAC_STATE = 4; - localparam ETHERTYPE_STATE = 5; - localparam PAYLOAD_STATE = 6; - localparam ZERO_PAD_STATE = 7; - localparam FCS_STATE = 8; - localparam IPG_STATE = 9; - - - // sequential logic manages the state machine - always @(posedge clk) begin - counter <= counter + 1; - crc_rst <= 0; - - if(state == IDLE_STATE) begin - counter <= 0; - crc_axiiv <= 0; - if(start) state <= PREAMBLE_STATE; - end - - else if(state == PREAMBLE_STATE) begin - if(counter == PREAMBLE_LEN - 1) begin - counter <= 0; - state <= SFD_STATE; - end - end - - else if(state == SFD_STATE) begin - if(counter == SFD_LEN - 1) begin - counter <= 0; - state <= DST_MAC_STATE; - end - end - - else if(state == DST_MAC_STATE) begin - // this is because the crc module lags behind the FSM, - // as it has to go through bitorder first - if(counter == 3) crc_axiiv <= 1; - - if(counter == DST_MAC_LEN - 1) begin - counter <= 0; - state <= SRC_MAC_STATE; - end - end - - else if(state == SRC_MAC_STATE) begin - if(counter == SRC_MAC_LEN - 1) begin - counter <= 0; - state <= ETHERTYPE_STATE; - end - end - - else if(state == ETHERTYPE_STATE) begin - if(counter == ETHERTYPE_LEN - 1) begin - counter <= 0; - state <= PAYLOAD_STATE; - end - end - - else if(state == PAYLOAD_STATE) begin - if(counter == PAYLOAD_LEN - 1) begin - counter <= 0; - state <= ZERO_PAD_STATE; - end - end - - else if(state == ZERO_PAD_STATE) begin - if(counter == ZERO_PAD_LEN - 1) begin - crc_axiiv <= 0; - counter <= 0; - state <= FCS_STATE; - end - end - - else if(state == FCS_STATE) begin - if(counter == FCS_LEN - 1) begin - counter <= 0; - state <= IPG_STATE; - end - end - - else if(state == IPG_STATE) begin - if(counter == IPG_LEN - 1) begin - crc_rst <= 1; - counter <= 0; - state <= IDLE_STATE; - end - end - end - - // combinational logic handles the pipeline - always @(*) begin - case (state) - IDLE_STATE: begin - bitorder_axiiv = 0; - bitorder_axiid = 0; - txen = 0; - txd = 0; - end - - PREAMBLE_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = PREAMBLE[2*(PREAMBLE_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - SFD_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = SFD[2*(SFD_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - DST_MAC_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = DST_MAC[2*(DST_MAC_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - SRC_MAC_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = SRC_MAC[2*(SRC_MAC_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - ETHERTYPE_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = ETHERTYPE[2*(ETHERTYPE_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - PAYLOAD_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = payload[2*(PAYLOAD_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - ZERO_PAD_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = 0; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - FCS_STATE: begin - bitorder_axiiv = 0; - bitorder_axiid = 0; - txen = 1; - txd = {crc_axiod[2*(FCS_LEN-counter)-2], crc_axiod[2*(FCS_LEN-counter)-1]}; - end - - IPG_STATE: begin - bitorder_axiiv = 0; - bitorder_axiid = 0; - txen = 0; - txd = 0; - end - - default: begin - bitorder_axiiv = 0; - bitorder_axiid = 0; - txen = 0; - txd = 0; - end - endcase - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/io_core.py b/src/manta/io_core.py new file mode 100644 index 0000000..97d869f --- /dev/null +++ b/src/manta/io_core.py @@ -0,0 +1,260 @@ +from amaranth import * +from warnings import warn +from .utils import * +from math import ceil + + +class IOCore(Elaboratable): + """ + Contains the HDL to instantiate an IO core on a FPGA, and the functions to interact with it. For + more information on the core itself, check out the IO core documentation. + """ + + def __init__(self, config, base_addr, interface): + self.config = config + self.base_addr = base_addr + self.interface = interface + + self.check_config(self.config) + self.define_signals() + self.mmap, self.max_addr = self.assign_memory() + + def check_config(self, config): + # make sure ports are defined + if "inputs" not in config and "outputs" not in config: + raise ValueError("No input or output ports specified.") + + # check for unrecognized options + valid_options = ["type", "inputs", "outputs", "user_clock"] + for option in config: + if option not in valid_options: + warn(f"Ignoring unrecognized option '{option}' in IO core.'") + + # check that user_clock is a bool + if "user_clock" in config: + if not isinstance(config["user_clock"], bool): + raise ValueError("Option user_clock must be a boolean.") + + # check that inputs is only dicts of format name:width + if "inputs" in config: + for name, attrs in config["inputs"].items(): + if not isinstance(name, str): + raise ValueError( + f'Input probe "{name}" has invalid name, names must be strings.' + ) + + if not isinstance(attrs, int): + raise ValueError(f'Input probe "{name}" must have integer width.') + + if not attrs > 0: + raise ValueError(f'Input probe "{name}" must have positive width.') + + if "outputs" in config: + for name, attrs in config["outputs"].items(): + if not isinstance(name, str): + raise ValueError( + f'Output probe "{name}" has invalid name, names must be strings.' + ) + + if not isinstance(attrs, int) and not isinstance(attrs, dict): + raise ValueError(f'Unrecognized format for output probe "{name}".') + + if isinstance(attrs, int): + if not attrs > 0: + raise ValueError( + f'Output probe "{name}" must have positive width.' + ) + + if isinstance(attrs, dict): + # check that each output probe has only recognized options + valid_options = ["width", "initial_value"] + for option in attrs: + if option not in valid_options: + warn(f'Ignoring unrecognized option "{option}" in IO core.') + + # check that widths are appropriate + if "width" not in attrs: + raise ValueError(f"No width specified for output probe {name}.") + + if not isinstance(attrs["width"], int): + raise ValueError( + f'Output probe "{name}" must have integer width.' + ) + + if not attrs["width"] > 0: + raise ValueError( + f'Input probe "{name}" must have positive width.' + ) + + def define_signals(self): + # Bus Ports + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal() + self.valid_o = Signal() + + # Input Probes (and buffers) + if "inputs" in self.config: + for name, width in self.config["inputs"].items(): + setattr(self, name, Signal(width, name=name)) + setattr(self, name + "_buf", Signal(width, name=name + "_buf")) + + # Output Probes (and buffers) + if "outputs" in self.config: + for name, attrs in self.config["outputs"].items(): + if isinstance(attrs, dict): + width = attrs["width"] + initial_value = attrs["initial_value"] + else: + width = attrs + initial_value = 0 + + setattr(self, name, Signal(width, name=name, reset=initial_value)) + setattr( + self, + name + "_buf", + Signal(width, name=name + "_buf", reset=initial_value), + ) + + # Strobe Register + self.strobe = Signal(reset=0) + + def assign_memory(self): + """ + the memory map is a dict that maps registers (in memory) to their locations (in memory) + as well as their Signals (from Amaranth). This looks like the following: + + { + strobe: + addrs: [0x0000] + signals: [self.strobe] + probe0_buf: + addrs: [0x0001] + signals: [self.probe0_buf] + probe1_buf: + addrs: [0x0002] + signals: [self.probe1_buf] + probe2_buf: + addrs: [0x0003] + signals: [self.probe2_buf] + probe3_buf: + addrs: [0x0004, 0x0005] + signals: [self.probe3_buf[0:15], self.probe3_buf[16:19]] + ... and so on + } + + """ + mmap = {} + + # Add strobe register first + mmap["strobe"] = dict(addrs=[self.base_addr], signals=[self.strobe]) + + # Add all input and output probes + all_probes = {} + if "inputs" in self.config: + all_probes = {**all_probes, **self.config["inputs"]} + + if "outputs" in self.config: + all_probes = {**all_probes, **self.config["outputs"]} + + for name, attrs in all_probes.items(): + # Handle output probes that might have initial value specified in addition to width + if isinstance(attrs, dict): + width = attrs["width"] + else: + width = attrs + + # Assign addresses + last_used_addr = list(mmap.values())[-1]["addrs"][-1] + addrs = [last_used_addr + 1 + i for i in range(ceil(width / 16))] + + # Slice signal into 16-bit chunks + signal = getattr(self, name + "_buf") + signals = [signal[16 * i : 16 * (i + 1)] for i in range(ceil(width / 16))] + + mmap[name + "_buf"] = {"addrs": addrs, "signals": signals} + + # Compute maximum address used by the core + max_addr = list(mmap.values())[-1]["addrs"][-1] + return mmap, max_addr + + def elaborate(self, platform): + m = Module() + + # Shuffle bus transactions along + m.d.sync += self.addr_o.eq(self.addr_i) + m.d.sync += self.data_o.eq(self.data_i) + m.d.sync += self.rw_o.eq(self.rw_i) + m.d.sync += self.valid_o.eq(self.valid_i) + + # Update buffers from probes + with m.If(self.strobe): + # Input buffers + if "inputs" in self.config: + for name in self.config["inputs"]: + input_probe = getattr(self, name) + input_probe_buf = getattr(self, name + "_buf") + m.d.sync += input_probe_buf.eq(input_probe) + + # Output buffers + if "outputs" in self.config: + for name in self.config["outputs"]: + output_probe = getattr(self, name) + output_probe_buf = getattr(self, name + "_buf") + m.d.sync += output_probe.eq(output_probe_buf) + + # Handle register reads and writes + with m.If((self.addr_i >= self.base_addr)): + with m.If((self.addr_o <= self.max_addr)): + for entry in self.mmap.values(): + for addr, signal in zip(entry["addrs"], entry["signals"]): + with m.If(self.rw_i): + with m.If(self.addr_i == addr): + m.d.sync += signal.eq(self.data_i) + + with m.Else(): + with m.If(self.addr_i == addr): + m.d.sync += self.data_o.eq(signal) + + return m + + def get_top_level_ports(self): + ports = [] + for name in self.config["inputs"].keys(): + ports.append(getattr(self, name)) + + for name in self.config["outputs"].keys(): + ports.append(getattr(self, name)) + + return ports + + def get_max_addr(self): + return self.max_addr + + def set_probe(self, probe_name, value): + # set value in buffer + addrs = self.mmap[probe_name + "_buf"]["addrs"] + datas = value_to_words(value, len(addrs)) + self.interface.write(addrs, datas) + + # pulse strobe register + strobe_addr = self.mmap["strobe"]["addrs"][0] + self.interface.write(strobe_addr, 0) + self.interface.write(strobe_addr, 1) + self.interface.write(strobe_addr, 0) + + def get_probe(self, probe_name): + # pulse strobe register + strobe_addr = self.mmap["strobe"]["addrs"][0] + self.interface.write(strobe_addr, 0) + self.interface.write(strobe_addr, 1) + self.interface.write(strobe_addr, 0) + + # get value from buffer + addrs = self.mmap[probe_name + "_buf"]["addrs"] + return words_to_value(self.interface.read(addrs)) diff --git a/src/manta/io_core/__init__.py b/src/manta/io_core/__init__.py deleted file mode 100644 index 8e33562..0000000 --- a/src/manta/io_core/__init__.py +++ /dev/null @@ -1,213 +0,0 @@ -from ..utils import * -from math import ceil - -class InputProbe: - def __init__(self, name, width, base_addr, strobe_addr, interface): - assert isinstance(width, int), f"Probe {name} must have integer width." - assert width > 0, f"Probe {name} must have positive width." - - self.name = name - self.width = width - self.strobe_addr = strobe_addr - self.interface = interface - - n_addrs = ceil(self.width / 16) - self.addrs = list(range(base_addr, base_addr + n_addrs)) - self.brackets = "" if self.width == 1 else f"[{self.width-1}:0] " - - def pulse_strobe_register(self): - # pulse the strobe register - self.interface.write(self.strobe_addr, 1) - self.interface.write(self.strobe_addr, 0) - strobe = self.interface.read(self.strobe_addr) - if strobe != 0: - raise ValueError("Unable to set strobe register to zero!") - - def get(self): - self.pulse_strobe_register() - return pack_16bit_words(self.interface.read(self.addrs)) - -class OutputProbe(InputProbe): - def __init__(self, name, width, base_addr, strobe_addr, interface, initial_value): - super().__init__(name, width, base_addr, strobe_addr, interface) - self.initial_value = initial_value - - def set(self, value): - # check that value is an integer - assert isinstance(value, int), "Value must be an integer." - - # check that value is within range for the width of the probe - if value > 0: - assert value <= (2**self.width) - 1, f"Unsigned value too large for probe of width {self.width}" - - elif value < 0: - assert abs(value) <= (2**(self.width-1))-1, f"Signed value too large for probe of width {self.width}" - - self.interface.write(self.addrs, unpack_16bit_words(value, len(self.addrs))) - self.pulse_strobe_register() - -class IOCore: - def __init__(self, config, name, base_addr, interface): - self.name = name - self.base_addr = base_addr - self.interface = interface - - # make sure we have ports defined - assert ('inputs' in config) or ('outputs' in config), "No input or output ports specified." - - # check for unrecognized options - for option in config: - if option not in ["type", "inputs", "outputs", "user_clock"]: - print(f"Warning: Ignoring unrecognized option '{option}' in IO core '{name}'") - - # add user clock - self.user_clock = False - if "user_clock" in config: - assert isinstance(config["user_clock"], bool), "Option user_clock must be a boolean." - self.user_clock = config["user_clock"] - - # add input probes to core - self.input_probes = [] - last_used_addr = self.base_addr # start at one since strobe register is at BASE_ADDR - if 'inputs' in config: - for name, width in config["inputs"].items(): - probe = InputProbe(name, width, last_used_addr + 1, self.base_addr, interface) - last_used_addr = probe.addrs[-1] - self.input_probes.append(probe) - - # add output probes to core - self.output_probes = [] - if 'outputs' in config: - for name, params in config["outputs"].items(): - # get width and initial value from config - if isinstance(params, int): - width = params - initial_value = 0 - - elif "width" in params and "initial_value" in params: - width = params["width"] - initial_value = params["initial_value"] - - else: - raise ValueError(f"Unable to determine probe width and initial value for {name}") - - # add probe to core - probe = OutputProbe(name, width, last_used_addr + 1, self.base_addr, interface, initial_value) - last_used_addr = probe.addrs[-1] - self.output_probes.append(probe) - - self.max_addr = last_used_addr - - # add friendly names to each probe - # (so users can do io_core.probe.set() and get() for instance) - for probe in self.input_probes + self.output_probes: - setattr(self, probe.name, probe) - - def hdl_top_level_ports(self): - ports = [] - - if self.user_clock: - ports.append(f"input wire {self.name}_user_clock") - - for probe in self.input_probes: - ports.append(f"input wire {probe.brackets}{probe.name}") - - for probe in self.output_probes: - ports.append(f"output reg {probe.brackets}{probe.name}") - - return ports - - def hdl_inst(self): - inst = VerilogManipulator("io_core/io_core_inst_tmpl.v") - inst.sub(self.name, "/* MODULE_NAME */") - inst.sub(self.name + "_inst", "/* INST_NAME */") - - # tie user_clock to bus_clk if external clock is not being used - if not self.user_clock: - inst.sub("clk", "/* USER_CLK */") - - else: - inst.sub(f"{self.name}_user_clk", "/* USER_CLK */") - - probes = {p.name:p.width for p in self.input_probes + self.output_probes} - inst_ports = inst.net_conn(probes, trailing_comma=True) - inst.sub(inst_ports, "/* INST_PORTS */") - - return inst.get_hdl() - - def hdl_def(self): - io_core = VerilogManipulator("io_core/io_core_def_tmpl.v") - io_core.sub(self.name, "/* MODULE_NAME */") - io_core.sub(self.max_addr, "/* MAX_ADDR */") - - # generate declaration - top_level_ports = ',\n'.join(self.hdl_top_level_ports()) - top_level_ports += ',' - io_core.sub(top_level_ports, "/* TOP_LEVEL_PORTS */") - - # generate memory handling - io_core.sub(self.gen_read_case_statement_body(), "/* READ_CASE_STATEMENT_BODY */") - io_core.sub(self.gen_write_case_statement_body(), "/* WRITE_CASE_STATEMENT_BODY */") - - # generate input and output probe buffers with initial values - io_core.sub(self.gen_input_probe_bufs(), "/* INPUT_PROBE_BUFFERS */") - io_core.sub(self.gen_output_probe_bufs(), "/* OUTPUT_PROBE_BUFFERS */") - io_core.sub(self.gen_output_probe_initial_values(), "/* OUTPUT_PROBE_INITIAL_VALUES */") - io_core.sub(self.gen_update_input_buffers(), "/* UPDATE_INPUT_BUFFERS */") - io_core.sub(self.gen_update_output_buffers(), "/* UPDATE_OUTPUT_BUFFERS */") - - return io_core.get_hdl() - - def gen_read_case_statement_body(self): - lines = [] - for probe in self.input_probes + self.output_probes: - if probe.width <= 16: - lines.append(f"BASE_ADDR + {probe.addrs[0]}: data_o <= {probe.name}_buf;") - - # assign 16-bit slices of each probe's buffer to each address taken by the probe - else: - for i in range(ceil(probe.width/16)): - top = ((i + 1) * 16) - 1 - btm = i * 16 - if top > probe.width - 1: - top = probe.width - 1 - lines.append(f"BASE_ADDR + {probe.addrs[i]}: data_o <= {probe.name}_buf[{top}:{btm}];") - - return '\n'.join(lines) - - def gen_write_case_statement_body(self): - lines = [] - for probe in self.output_probes: - if probe.width <= 16: - lines.append(f"BASE_ADDR + {probe.addrs[0]}: {probe.name}_buf <= data_i;") - - else: - for i in range(ceil(probe.width/16)): - top = ((i + 1) * 16) - 1 - btm = i * 16 - if top > probe.width - 1: - top = probe.width - 1 - - lines.append(f"BASE_ADDR + {probe.addrs[i]}: {probe.name}_buf[{top}:{btm}] <= data_i;") - - return '\n'.join(lines) - - def gen_input_probe_bufs(self): - lines = [f"reg {p.brackets}{p.name}_buf = 0;" for p in self.input_probes] - return '\n'.join(lines) - - def gen_output_probe_bufs(self): - lines = [f"reg {p.brackets}{p.name}_buf = {p.initial_value};" for p in self.output_probes] - return '\n'.join(lines) - - def gen_output_probe_initial_values(self): - lines = [f"{p.name} = {p.initial_value};" for p in self.output_probes] - return '\n'.join(lines) - - def gen_update_input_buffers(self): - lines = [f"{p.name}_buf <= {p.name};" for p in self.input_probes] - return '\n'.join(lines) - - def gen_update_output_buffers(self): - lines = [f"{p.name} <= {p.name}_buf;" for p in self.output_probes] - return '\n'.join(lines) diff --git a/src/manta/io_core/io_core_def_tmpl.v b/src/manta/io_core/io_core_def_tmpl.v deleted file mode 100644 index 5803486..0000000 --- a/src/manta/io_core/io_core_def_tmpl.v +++ /dev/null @@ -1,77 +0,0 @@ -module /* MODULE_NAME */ ( - input wire bus_clk, - input wire user_clk, - - // ports - /* TOP_LEVEL_PORTS */ - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o - ); - - parameter BASE_ADDR = 0; - - reg strobe = 0; - - // input probe buffers - /* INPUT_PROBE_BUFFERS */ - - // output probe buffers - /* OUTPUT_PROBE_BUFFERS */ - - // output probe initial values - initial begin - /* OUTPUT_PROBE_INITIAL_VALUES */ - end - - // synchronize buffers and probes on strobe - always @(posedge user_clk) begin - if(strobe) begin - // update input buffers from input probes - /* UPDATE_INPUT_BUFFERS */ - - // update output buffers from output probes - /* UPDATE_OUTPUT_BUFFERS */ - end - end - - // handle bus operations - always @(posedge bus_clk) begin - addr_o <= addr_i; - data_o <= data_i; - rw_o <= rw_i; - valid_o <= valid_i; - - // check if address is valid - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + /* MAX_ADDR */)) begin - - // reads - if(!rw_i) begin - case (addr_i) - BASE_ADDR + 0: data_o <= strobe; - - /* READ_CASE_STATEMENT_BODY */ - endcase - end - - // writes - else begin - case (addr_i) - BASE_ADDR + 0: strobe <= data_i; - - /* WRITE_CASE_STATEMENT_BODY */ - endcase - end - end - end - -endmodule \ No newline at end of file diff --git a/src/manta/io_core/io_core_inst_tmpl.v b/src/manta/io_core/io_core_inst_tmpl.v deleted file mode 100644 index 4568ef0..0000000 --- a/src/manta/io_core/io_core_inst_tmpl.v +++ /dev/null @@ -1,18 +0,0 @@ -/* MODULE_NAME */ /* INST_NAME */ ( - .bus_clk(clk), - .user_clk(/* USER_CLK */), - - // ports - /* INST_PORTS */ - - // input port - .addr_i(), - .data_i(), - .rw_i(), - .valid_i(), - - // output port - .addr_o(), - .data_o(), - .rw_o(), - .valid_o()); \ No newline at end of file diff --git a/src/manta/la_core/__init__.py b/src/manta/la_core/__init__.py deleted file mode 100644 index a33c307..0000000 --- a/src/manta/la_core/__init__.py +++ /dev/null @@ -1,463 +0,0 @@ -from ..utils import * - -from datetime import datetime -from pkg_resources import get_distribution -import math -import os - -class LogicAnalyzerCore: - def __init__(self, config, name, base_addr, interface): - self.name = name - self.base_addr = base_addr - self.interface = interface - - # Warn if unrecognized options have been given - valid_options = ["type", "sample_depth", "probes", "triggers", "trigger_loc", "trigger_mode"] - for option in config: - if option not in valid_options: - print(f"Warning: Ignoring unrecognized option '{option}' in Logic Analyzer core '{self.name}'") - - # Load sample depth - assert "sample_depth" in config, \ - "Sample depth not found for Logic Analyzer core {self.name}." - - assert isinstance(config["sample_depth"], int), \ - "Sample depth must be an integer." - - self.sample_depth = config["sample_depth"] - - # Add probes - assert "probes" in config, "No probe definitions found." - assert len(config["probes"]) > 0, "Must specify at least one probe." - - for probe_name, probe_width in config["probes"].items(): - assert probe_width > 0, f"Probe {probe_name} is of invalid width - it must be of at least width one." - - self.probes = config["probes"] - - # Add triggers - assert "triggers" in config, "No triggers found." - assert len(config["triggers"]) > 0, "Must specify at least one trigger." - self.triggers = config["triggers"] - - # Add trigger location - self.trigger_loc = self.sample_depth // 2 - if "trigger_loc" in config: - assert isinstance(config["trigger_loc"], int), \ - "Trigger location must be an integer." - - assert config["trigger_loc"] >= 0, \ - "Trigger location cannot be negative." - - assert config["trigger_loc"] <= self.sample_depth, \ - "Trigger location cannot exceed sample depth." - - self.trigger_loc = config["trigger_loc"] - - # Add trigger mode - self.SINGLE_SHOT = 0 - self.INCREMENTAL = 1 - self.IMMEDIATE = 2 - - self.trigger_mode = self.SINGLE_SHOT - if "trigger_mode" in config: - assert config["trigger_mode"] in ["single_shot", "incremental", "immediate"], \ - "Unrecognized trigger mode provided." - - if config["trigger_mode"] == "single_shot": - self.trigger_mode = self.SINGLE_SHOT - - elif config["trigger_mode"] == "incremental": - self.trigger_mode = self.INCREMENTAL - - elif config["trigger_mode"] == "immediate": - self.trigger_mode = self.IMMEDIATE - - # compute base addresses - self.fsm_base_addr = self.base_addr - self.trigger_block_base_addr = self.fsm_base_addr + 7 - - self.total_probe_width = sum(self.probes.values()) - self.n_brams = math.ceil(self.total_probe_width / 16) - self.block_memory_base_addr = self.trigger_block_base_addr + (2*len(self.probes)) - self.max_addr = self.block_memory_base_addr + (self.n_brams * self.sample_depth) - - # build out self register map: - # these are also defined in logic_analyzer_fsm_registers.v, and should match - self.state_reg_addr = self.base_addr - self.trigger_mode_reg_addr = self.base_addr + 1 - self.trigger_loc_reg_addr = self.base_addr + 2 - self.request_start_reg_addr = self.base_addr + 3 - self.request_stop_reg_addr = self.base_addr + 4 - self.read_pointer_reg_addr = self.base_addr + 5 - self.write_pointer_reg_addr = self.base_addr + 6 - - self.IDLE = 0 - self.MOVE_TO_POSITION = 1 - self.IN_POSITION = 2 - self.CAPTURING = 3 - self.CAPTURED = 4 - - def hdl_inst(self): - la_inst = VerilogManipulator("la_core/logic_analyzer_inst_tmpl.v") - - # add module name to instantiation - la_inst.sub(self.name, "/* INST_NAME */") - - # add net connections to instantiation - conns = la_inst.net_conn(self.probes, trailing_comma=True) - la_inst.sub(conns, "/* NET_CONNS */") - return la_inst.get_hdl() - - def gen_trigger_block_def(self): - trigger_block = VerilogManipulator("la_core/trigger_block_def_tmpl.v") - - # add probe ports to module declaration - # these ports belong to the logic analyzer, but - # need to be included in the trigger_block module declaration - probe_ports = trigger_block.net_dec(self.probes, "input wire", trailing_comma=True) - trigger_block.sub(probe_ports, "/* PROBE_PORTS */") - - - # add trigger cores to module definition - # these are instances of the trigger module, of which one gets wired - # into each probe - trigger_module_insts = [] - for name, width in self.probes.items(): - trig_inst = VerilogManipulator("la_core/trigger_block_inst_tmpl.v") - trig_inst.sub(width, "/* INPUT_WIDTH */") - trig_inst.sub(f"{name}_trigger", "/* NAME */") - - trig_inst.sub(f"reg [3:0] {name}_op = 0;", "/* OP_DEC */") - trig_inst.sub(f"reg {name}_trig;", "/* TRIG_DEC */") - - if width == 1: - trig_inst.sub(f"reg {name}_arg = 0;", "/* ARG_DEC */") - - else: - trig_inst.sub(f"reg [{width-1}:0] {name}_arg = 0;", "/* ARG_DEC */") - - trig_inst.sub(name, "/* PROBE */") - trig_inst.sub(f"{name}_op", "/* OP */") - trig_inst.sub(f"{name}_arg", "/* ARG */") - trig_inst.sub(f"{name}_trig", "/* TRIG */") - - trigger_module_insts.append(trig_inst.get_hdl()) - - trigger_module_insts = "\n".join(trigger_module_insts) - trigger_block.sub(trigger_module_insts, "/* TRIGGER_MODULE_INSTS */") - - # add combined individual triggers - cit = [f"{name}_trig" for name in self.probes] - cit = " || ".join(cit) - cit = f"assign trig = {cit};" - trigger_block.sub(cit, " /* COMBINE_INDIV_TRIGGERS */") - - # add read and write block case statement bodies - rcsb = "" # read case statement body - wcsb = "" # write case statement body - addr = 0 - for i, name in enumerate(self.probes): - addr = 2 * i - rcsb += f"BASE_ADDR + {addr}: data_o <= {name}_op;\n" - wcsb += f"BASE_ADDR + {addr}: {name}_op <= data_i;\n" - - addr = (2 * i) + 1 - rcsb += f"BASE_ADDR + {addr}: data_o <= {name}_arg;\n" - wcsb += f"BASE_ADDR + {addr}: {name}_arg <= data_i;\n" - - rcsb = rcsb.strip() - wcsb = wcsb.strip() - - trigger_block.sub(rcsb, "/* READ_CASE_STATEMENT_BODY */") - trigger_block.sub(wcsb, "/* WRITE_CASE_STATEMENT_BODY */") - trigger_block.sub(self.trigger_block_base_addr + addr + 1, "/* MAX_ADDR */") - - return trigger_block.get_hdl() - - def gen_logic_analyzer_def(self): - la = VerilogManipulator("la_core/logic_analyzer_def_tmpl.v") - - # add top level probe ports to module declaration - ports = la.net_dec(self.probes, "input wire", trailing_comma=True) - la.sub(ports, "/* TOP_LEVEL_PROBE_PORTS */") - - # assign base addresses to the FSM, trigger block, and sample mem - la.sub(self.fsm_base_addr, "/* FSM_BASE_ADDR */") - la.sub(self.trigger_block_base_addr, "/* TRIGGER_BLOCK_BASE_ADDR */") - la.sub(self.block_memory_base_addr, "/* BLOCK_MEMORY_BASE_ADDR */") - - # set sample depth - la.sub(self.sample_depth, "/* SAMPLE_DEPTH */") - - # set probe ports for the trigger block and sample mem - probe_ports = la.net_conn(self.probes, trailing_comma=True) - la.sub(probe_ports, "/* TRIGGER_BLOCK_PROBE_PORTS */") - - la.sub(self.total_probe_width, "/* TOTAL_PROBE_WIDTH */") - - # concatenate the probes together to make one big register, - # but do so such that the first probe in the config file - # is at the least-significant position in that big register. - # - # this makes part-selecting out from the memory easier to - # implement in python, and because verilog and python conventions - # are different, we would have had to reverse it somwehere anyway - probes_concat = list(self.probes.keys())[::-1] - probes_concat = '{' + ', '.join(probes_concat) + '}' - la.sub(probes_concat, "/* PROBES_CONCAT */") - - return la.get_hdl() - - def hdl_def(self): - # Return an autogenerated verilog module definition for the core. - # load source files - hdl = self.gen_logic_analyzer_def() + "\n" - hdl += VerilogManipulator("la_core/logic_analyzer_controller.v").get_hdl() + "\n" - hdl += VerilogManipulator("la_core/logic_analyzer_fsm_registers.v").get_hdl() + "\n" - hdl += VerilogManipulator("block_mem_core/block_memory.v").get_hdl() + "\n" - hdl += VerilogManipulator("block_mem_core/dual_port_bram.v").get_hdl() + "\n" - hdl += self.gen_trigger_block_def() + "\n" - hdl += VerilogManipulator("la_core/trigger.v").get_hdl() + "\n" - - return hdl - - def hdl_top_level_ports(self): - # the probes that we want as ports on the top-level manta module - ports = [] - for name, width in self.probes.items(): - if width == 1: - ports.append(f"input wire {name}") - - else: - ports.append(f"input wire [{width-1}:0] {name}") - return ports - #return VerilogManipulator().net_dec(self.probes, "input wire") - - def set_trigger_conditions(self): - - operations = { - "DISABLE" : 0, - "RISING" : 1, - "FALLING" : 2, - "CHANGING" : 3, - "GT" : 4, - "LT" : 5, - "GEQ" : 6, - "LEQ" : 7, - "EQ" : 8, - "NEQ" : 9 - } - - ops_with_no_args = ["DISABLE", "RISING" , "FALLING", "CHANGING"] - - # reset all the other triggers - for addr in range(self.trigger_block_base_addr, self.block_memory_base_addr): - self.interface.write(addr, 0) - - for trigger in self.triggers: - # determine if the trigger is good - - # most triggers will have 3 parts - the trigger, the operation, and the argument - # this is true unless the argument is RISING, FALLING, or CHANGING - - statement = trigger.split(' ') - if len(statement) == 2: - assert statement[1] in ops_with_no_args, "Invalid operation in trigger statement." - probe_name, op = statement - - op_register = 2*(list(self.probes.keys()).index(probe_name)) + self.trigger_block_base_addr - - self.interface.write(op_register, operations[op]) - - else: - assert len(statement) == 3, "Missing information in trigger statement." - probe_name, op, arg = statement - - op_register = 2*(list(self.probes.keys()).index(probe_name)) + self.trigger_block_base_addr - arg_register = op_register + 1 - - self.interface.write(op_register, operations[op]) - self.interface.write(arg_register, int(arg)) - - - - # functions for actually using the core: - def capture(self): - # Check state - if it's in anything other than IDLE, - # request to stop the existing capture - - print(" -> Resetting core...") - state = self.interface.read(self.state_reg_addr) - if state != self.IDLE: - self.interface.write(self.request_stop_reg_addr, 0) - self.interface.write(self.request_stop_reg_addr, 1) - self.interface.write(self.request_stop_reg_addr, 0) - - state = self.interface.read(self.state_reg_addr) - assert state == self.IDLE, "Logic analyzer did not reset to correct state when requested to." - - # Configure trigger conditions - print(" -> Set trigger conditions...") - self.set_trigger_conditions() - - # Configure the trigger_mode - print(" -> Setting trigger mode") - self.interface.write(self.trigger_mode_reg_addr, self.trigger_mode) - - # Configure the trigger_loc - print(" -> Setting trigger location...") - self.interface.write(self.trigger_loc_reg_addr, self.trigger_loc) - - # Start the capture by pulsing request_start - print(" -> Starting capture...") - self.interface.write(self.request_start_reg_addr, 1) - self.interface.write(self.request_start_reg_addr, 0) - - # Wait for core to finish capturing data - print(" -> Waiting for capture to complete...") - state = self.interface.read(self.state_reg_addr) - while(state != self.CAPTURED): - state = self.interface.read(self.state_reg_addr) - - # Read out contents from memory - print(" -> Reading sample memory contents...") - addrs = list(range(self.block_memory_base_addr, self.max_addr)) - block_mem_contents = self.interface.read(addrs) - - # Revolve BRAM contents around so the data pointed to by the read_pointer - # is at the beginning - print(" -> Reading read_pointer and revolving memory...") - read_pointer = self.interface.read(self.read_pointer_reg_addr) - - # when the total probe width is >16 bits and multiple BRAMs are used, - # then a single sample is stored across multiple locations in memory, - # so we must combine the data from n_brams addresses to get the value - # of the sample at that time - - # convert the sample number at read_pointer to memory address - read_address = self.n_brams * read_pointer - sample_mem = block_mem_contents[read_address:] + block_mem_contents[:read_address] - - # split sample memory into chunks of size n_brams - chunks = [sample_mem[i: i + self.n_brams] for i in range(0, len(sample_mem), self.n_brams)] - - # concat them in little-endian order (ie, chunk[0] is LSB) - concat = lambda x: int( ''.join([f'{i:016b}' for i in x[::-1]]), 2) - return [concat(c) for c in chunks] - - - def export_vcd(self, capture_data, path): - from vcd import VCDWriter - vcd_file = open(path, "w") - - # Use the same datetime format that iVerilog uses - timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y") - - with VCDWriter(vcd_file, '10 ns', timestamp, "manta") as writer: - - # each probe has a name, width, and writer associated with it - signals = [] - for name, width in self.probes.items(): - signal = { - "name" : name, - "width" : width, - "data" : self.part_select_capture_data(capture_data, name), - "var": writer.register_var("manta", name, "wire", size=width) - } - signals.append(signal) - - clock = writer.register_var("manta", "clk", "wire", size=1) - trigger = writer.register_var("manta", "trigger", "wire", size=1) - - # add the data to each probe in the vcd file - for timestamp in range(0, 2*len(capture_data)): - - # run the clock - writer.change(clock, timestamp, timestamp % 2 == 0) - - # set the trigger - triggered = (timestamp // 2) >= self.trigger_loc - writer.change(trigger, timestamp, triggered) - - # add other signals - for signal in signals: - var = signal["var"] - sample = signal["data"][timestamp // 2] - - writer.change(var, timestamp, sample) - - vcd_file.close() - - def export_mem(self, capture_data, path): - with open(path, "w") as f: - # a wee bit of cursed string formatting, but just - # outputs each sample as binary, padded to a fixed length - w = self.total_probe_width - f.writelines([f'{s:0{w}b}\n' for s in capture_data]) - - def export_playback_module(self, path): - playback = VerilogManipulator("la_core/logic_analyzer_playback_tmpl.v") - - module_name = f"{self.name}_playback" - playback.sub(module_name, "/* MODULE_NAME */") - - version = "v" + get_distribution('mantaray').version - playback.sub(version, "/* VERSION */") - - timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S") - playback.sub(timestamp, "/* TIMESTAMP */") - - user = os.environ.get("USER", os.environ.get("USERNAME")) - playback.sub(user, "/* USER */") - - ports = [f".{name}({name})" for name in self.probes.keys()] - ports = ",\n".join(ports) - playback.sub(ports, "/* PORTS */") - - playback.sub(self.sample_depth, "/* SAMPLE_DEPTH */") - playback.sub(self.total_probe_width, "/* TOTAL_PROBE_WIDTH */") - - # see the note in generate_logic_analyzer_def about why we do this - probes_concat = list(self.probes.keys())[::-1] - probes_concat = '{' + ', '.join(probes_concat) + '}' - playback.sub(probes_concat, "/* PROBES_CONCAT */") - - - probe_dec = playback.net_dec(self.probes, "output reg") - playback.sub(probe_dec, "/* PROBE_DEC */") - - with open(path, "w") as f: - f.write(playback.get_hdl()) - - - def part_select_capture_data(self, capture_data, probe_name): - """Given the name of the probe, part-select the appropriate bits of capture data, - and return as an integer. Accepts capture_data as an integer or a list of integers.""" - - # sum up the widths of the probes below this one - lower = 0 - for name, width in self.probes.items(): - if name == probe_name: - break - - lower += width - - upper = lower + (self.probes[probe_name] - 1) - - # define the part select - mask = 2 ** (upper - lower + 1) - 1 - part_select = lambda x: (x >> lower) & mask - - # apply the part_select function depending on type - if isinstance(capture_data, int): - return part_select(capture_data) - - elif isinstance(capture_data, list): - for i in capture_data: - assert isinstance(i, int), "Can only part select on integers and list of integers." - - return [part_select(sample) for sample in capture_data] - - else: - raise ValueError("Can only part select on integers and lists of integers.") diff --git a/src/manta/la_core/logic_analyzer_controller.v b/src/manta/la_core/logic_analyzer_controller.v deleted file mode 100644 index 50c90bf..0000000 --- a/src/manta/la_core/logic_analyzer_controller.v +++ /dev/null @@ -1,92 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module logic_analyzer_controller ( - input wire clk, - - // from register file - output reg [3:0] state, - input wire [15:0] trigger_loc, - input wire [1:0] trigger_mode, - input wire request_start, - input wire request_stop, - output reg [ADDR_WIDTH-1:0] read_pointer, - output reg [ADDR_WIDTH-1:0] write_pointer, - - // from trigger block - input wire trig, - - // block memory user port - output reg [ADDR_WIDTH-1:0] bram_addr, - output reg bram_we - ); - - assign bram_addr = write_pointer; - - parameter SAMPLE_DEPTH= 0; - localparam ADDR_WIDTH = $clog2(SAMPLE_DEPTH); - - /* ----- FIFO ----- */ - initial read_pointer = 0; - initial write_pointer = 0; - - /* ----- FSM ----- */ - localparam IDLE = 0; - localparam MOVE_TO_POSITION = 1; - localparam IN_POSITION = 2; - localparam CAPTURING = 3; - localparam CAPTURED = 4; - - initial state = IDLE; - - // rising edge detection for start/stop requests - reg prev_request_start; - always @(posedge clk) prev_request_start <= request_start; - - reg prev_request_stop; - always @(posedge clk) prev_request_stop <= request_stop; - - always @(posedge clk) begin - // don't do anything to the FIFO unless told to - - if(state == IDLE) begin - write_pointer <= 0; - read_pointer <= 0; - bram_we <= 0; - - if(request_start && ~prev_request_start) begin - state <= MOVE_TO_POSITION; - end - end - - else if(state == MOVE_TO_POSITION) begin - write_pointer <= write_pointer + 1; - bram_we <= 1; - - if(write_pointer == trigger_loc) begin - if(trig) state <= CAPTURING; - else state <= IN_POSITION; - end - end - - else if(state == IN_POSITION) begin - write_pointer <= (write_pointer + 1) % SAMPLE_DEPTH; - read_pointer <= (read_pointer + 1) % SAMPLE_DEPTH; - bram_we <= 1; - if(trig) state <= CAPTURING; - end - - else if(state == CAPTURING) begin - if(write_pointer == read_pointer) begin - bram_we <= 0; - state <= CAPTURED; - end - - else write_pointer <= (write_pointer + 1) % SAMPLE_DEPTH; - end - - if(request_stop && ~prev_request_stop) state <= IDLE; - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/logic_analyzer_def_tmpl.v b/src/manta/la_core/logic_analyzer_def_tmpl.v deleted file mode 100644 index cbb0ef9..0000000 --- a/src/manta/la_core/logic_analyzer_def_tmpl.v +++ /dev/null @@ -1,142 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module logic_analyzer ( - input wire clk, - - // probes - /* TOP_LEVEL_PROBE_PORTS */ - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o - ); - localparam SAMPLE_DEPTH = /* SAMPLE_DEPTH */; - localparam ADDR_WIDTH = $clog2(SAMPLE_DEPTH); - - reg [3:0] state; - reg [15:0] trigger_loc; - reg [1:0] trigger_mode; - reg request_start; - reg request_stop; - reg [ADDR_WIDTH-1:0] read_pointer; - reg [ADDR_WIDTH-1:0] write_pointer; - - reg trig; - - reg [ADDR_WIDTH-1:0] bram_addr; - reg bram_we; - - localparam TOTAL_PROBE_WIDTH = /* TOTAL_PROBE_WIDTH */; - reg [TOTAL_PROBE_WIDTH-1:0] probes_concat; - assign probes_concat = /* PROBES_CONCAT */; - - logic_analyzer_controller #(.SAMPLE_DEPTH(SAMPLE_DEPTH)) la_controller ( - .clk(clk), - - // from register file - .state(state), - .trigger_loc(trigger_loc), - .trigger_mode(trigger_mode), - .request_start(request_start), - .request_stop(request_stop), - .read_pointer(read_pointer), - .write_pointer(write_pointer), - - // from trigger block - .trig(trig), - - // from block memory user port - .bram_addr(bram_addr), - .bram_we(bram_we) - ); - - logic_analyzer_fsm_registers #( - .BASE_ADDR(/* FSM_BASE_ADDR */), - .SAMPLE_DEPTH(SAMPLE_DEPTH) - ) fsm_registers ( - .clk(clk), - - .addr_i(addr_i), - .data_i(data_i), - .rw_i(rw_i), - .valid_i(valid_i), - - .addr_o(fsm_reg_trig_blk_addr), - .data_o(fsm_reg_trig_blk_data), - .rw_o(fsm_reg_trig_blk_rw), - .valid_o(fsm_reg_trig_blk_valid), - - .state(state), - .trigger_loc(trigger_loc), - .trigger_mode(trigger_mode), - .request_start(request_start), - .request_stop(request_stop), - .read_pointer(read_pointer), - .write_pointer(write_pointer)); - - reg [15:0] fsm_reg_trig_blk_addr; - reg [15:0] fsm_reg_trig_blk_data; - reg fsm_reg_trig_blk_rw; - reg fsm_reg_trig_blk_valid; - - // trigger block - trigger_block #(.BASE_ADDR(/* TRIGGER_BLOCK_BASE_ADDR */)) trig_blk ( - .clk(clk), - - /* TRIGGER_BLOCK_PROBE_PORTS */ - - .trig(trig), - - .addr_i(fsm_reg_trig_blk_addr), - .data_i(fsm_reg_trig_blk_data), - .rw_i(fsm_reg_trig_blk_rw), - .valid_i(fsm_reg_trig_blk_valid), - - .addr_o(trig_blk_block_mem_addr), - .data_o(trig_blk_block_mem_data), - .rw_o(trig_blk_block_mem_rw), - .valid_o(trig_blk_block_mem_valid)); - - reg [15:0] trig_blk_block_mem_addr; - reg [15:0] trig_blk_block_mem_data; - reg trig_blk_block_mem_rw; - reg trig_blk_block_mem_valid; - - // sample memory - block_memory #( - .BASE_ADDR(/* BLOCK_MEMORY_BASE_ADDR */), - .WIDTH(TOTAL_PROBE_WIDTH), - .DEPTH(SAMPLE_DEPTH) - ) block_mem ( - .clk(clk), - - // input port - .addr_i(trig_blk_block_mem_addr), - .data_i(trig_blk_block_mem_data), - .rw_i(trig_blk_block_mem_rw), - .valid_i(trig_blk_block_mem_valid), - - // output port - .addr_o(addr_o), - .data_o(data_o), - .rw_o(rw_o), - .valid_o(valid_o), - - // BRAM itself - .user_clk(clk), - .user_addr(bram_addr), - .user_din(probes_concat), - .user_dout(), - .user_we(bram_we)); -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/logic_analyzer_fsm_registers.v b/src/manta/la_core/logic_analyzer_fsm_registers.v deleted file mode 100644 index d35bcfb..0000000 --- a/src/manta/la_core/logic_analyzer_fsm_registers.v +++ /dev/null @@ -1,75 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module logic_analyzer_fsm_registers( - input wire clk, - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o, - - // registers - input wire [3:0] state, - output reg [15:0] trigger_loc, - output reg [1:0] trigger_mode, - output reg request_start, - output reg request_stop, - input wire [ADDR_WIDTH-1:0] read_pointer, - input wire [ADDR_WIDTH-1:0] write_pointer - ); - - initial trigger_loc = 0; - initial trigger_mode = 0; - initial request_start = 0; - initial request_stop = 0; - - parameter BASE_ADDR = 0; - localparam MAX_ADDR = BASE_ADDR + 5; - parameter SAMPLE_DEPTH = 0; - parameter ADDR_WIDTH = $clog2(SAMPLE_DEPTH); - - always @(posedge clk) begin - addr_o <= addr_i; - data_o <= data_i; - rw_o <= rw_i; - valid_o <= valid_i; - - // check if address is valid - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= MAX_ADDR)) begin - - // reads - if(!rw_i) begin - case (addr_i) - BASE_ADDR + 0: data_o <= state; - BASE_ADDR + 1: data_o <= trigger_mode; - BASE_ADDR + 2: data_o <= trigger_loc; - BASE_ADDR + 3: data_o <= request_start; - BASE_ADDR + 4: data_o <= request_stop; - BASE_ADDR + 5: data_o <= read_pointer; - BASE_ADDR + 6: data_o <= write_pointer; - endcase - end - - // writes - else begin - case (addr_i) - BASE_ADDR + 1: trigger_mode <= data_i; - BASE_ADDR + 2: trigger_loc <= data_i; - BASE_ADDR + 3: request_start <= data_i; - BASE_ADDR + 4: request_stop <= data_i; - endcase - end - end - end - - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/logic_analyzer_inst_tmpl.v b/src/manta/la_core/logic_analyzer_inst_tmpl.v deleted file mode 100644 index eebb872..0000000 --- a/src/manta/la_core/logic_analyzer_inst_tmpl.v +++ /dev/null @@ -1,14 +0,0 @@ -logic_analyzer /* INST_NAME */ ( - .clk(clk), - - .addr_i(), - .data_i(), - .rw_i(), - .valid_i(), - - /* NET_CONNS */ - - .addr_o(), - .data_o(), - .rw_o(), - .valid_o()); \ No newline at end of file diff --git a/src/manta/la_core/logic_analyzer_playback_tmpl.v b/src/manta/la_core/logic_analyzer_playback_tmpl.v deleted file mode 100644 index e87228f..0000000 --- a/src/manta/la_core/logic_analyzer_playback_tmpl.v +++ /dev/null @@ -1,50 +0,0 @@ -/* -This playback module was generated with Manta /* VERSION */ on /* TIMESTAMP */ by /* USER */ - -If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! - -/* MODULE_NAME */ #(.MEM_FILE("capture.mem")) /* MODULE_NAME */_inst ( - .clk(clk), - .enable(1'b1), - - /* PORTS */); - -*/ - - -module /* MODULE_NAME */ ( - input wire clk, - - input wire enable, - output reg done, - - /* PROBE_DEC */); - - parameter MEM_FILE = ""; - localparam SAMPLE_DEPTH = /* SAMPLE_DEPTH */; - localparam TOTAL_PROBE_WIDTH = /* TOTAL_PROBE_WIDTH */; - - reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0]; - reg [$clog2(SAMPLE_DEPTH)-1:0] addr; - reg [TOTAL_PROBE_WIDTH-1:0] sample; - - assign done = (addr >= SAMPLE_DEPTH); - - initial begin - $readmemb(MEM_FILE, capture, 0, SAMPLE_DEPTH-1); - addr = 0; - end - - always @(posedge clk) begin - if (enable && !done) begin - addr = addr + 1; - sample = capture[addr]; - /* PROBES_CONCAT */ = sample; - end - end -endmodule \ No newline at end of file diff --git a/src/manta/la_core/trigger.v b/src/manta/la_core/trigger.v deleted file mode 100644 index 05939e1..0000000 --- a/src/manta/la_core/trigger.v +++ /dev/null @@ -1,45 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module trigger ( - input wire clk, - - input wire [INPUT_WIDTH-1:0] probe, - input wire [3:0] op, - input wire [INPUT_WIDTH-1:0] arg, - - output reg trig); - - parameter INPUT_WIDTH = 0; - - localparam DISABLE = 0; - localparam RISING = 1; - localparam FALLING = 2; - localparam CHANGING = 3; - localparam GT = 4; - localparam LT = 5; - localparam GEQ = 6; - localparam LEQ = 7; - localparam EQ = 8; - localparam NEQ = 9; - - reg [INPUT_WIDTH-1:0] probe_prev = 0; - always @(posedge clk) probe_prev <= probe; - - always @(*) begin - case (op) - RISING : trig = (probe > probe_prev); - FALLING : trig = (probe < probe_prev); - CHANGING : trig = (probe != probe_prev); - GT: trig = (probe > arg); - LT: trig = (probe < arg); - GEQ: trig = (probe >= arg); - LEQ: trig = (probe <= arg); - EQ: trig = (probe == arg); - NEQ: trig = (probe != arg); - default: trig = 0; - endcase - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/trigger_block_def_tmpl.v b/src/manta/la_core/trigger_block_def_tmpl.v deleted file mode 100644 index 39af04f..0000000 --- a/src/manta/la_core/trigger_block_def_tmpl.v +++ /dev/null @@ -1,62 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module trigger_block ( - input wire clk, - - // probes - /* PROBE_PORTS */ - - // trigger - output reg trig, - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o); - - parameter BASE_ADDR = 0; - localparam MAX_ADDR = /* MAX_ADDR */; - - // trigger configuration registers - // - each probe gets an operation and a compare register - // - at the end we OR them all together. along with any custom probes the user specs - - /* TRIGGER_MODULE_INSTS */ - - /* COMBINE_INDIV_TRIGGERS */ - - // perform register operations - always @(posedge clk) begin - addr_o <= addr_i; - data_o <= data_i; - rw_o <= rw_i; - valid_o <= valid_i; - - if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + MAX_ADDR) ) begin - - // reads - if(valid_i && !rw_i) begin - case (addr_i) - /* READ_CASE_STATEMENT_BODY */ - endcase - end - - // writes - else if(valid_i && rw_i) begin - case (addr_i) - /* WRITE_CASE_STATEMENT_BODY */ - endcase - end - end - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/trigger_block_inst_tmpl.v b/src/manta/la_core/trigger_block_inst_tmpl.v deleted file mode 100644 index f796fa2..0000000 --- a/src/manta/la_core/trigger_block_inst_tmpl.v +++ /dev/null @@ -1,11 +0,0 @@ -/* OP_DEC */ -/* ARG_DEC */ -/* TRIG_DEC */ - -trigger #(.INPUT_WIDTH(/* INPUT_WIDTH */)) /* NAME */ ( - .clk(clk), - - .probe(/* PROBE */), - .op(/* OP */), - .arg(/* ARG */), - .trig(/* TRIG */)); diff --git a/src/manta/logic_analyzer_core.py b/src/manta/logic_analyzer_core.py new file mode 100644 index 0000000..4acedd5 --- /dev/null +++ b/src/manta/logic_analyzer_core.py @@ -0,0 +1,558 @@ +from amaranth import * +from warnings import warn +from .utils import * +from .io_core import IOCore +from .memory_core import ReadOnlyMemoryCore +from math import ceil, log2 + + +class LogicAnalyzerCore(Elaboratable): + """ """ + + def __init__(self, config, base_addr, interface): + self.config = config + self.base_addr = base_addr + self.interface = interface + + self.check_config(config) + + # State Machine Values + self.states = { + "IDLE": 0, + "MOVE_TO_POSITION": 1, + "IN_POSITION": 2, + "CAPTURING": 3, + "CAPTURED": 4, + } + + # Trigger Modes + self.trigger_modes = {"SINGLE_SHOT": 0, "INCREMENTAL": 1, "IMMEDIATE": 2} + + # Trigger operations + self.operations = { + "DISABLE": 0, + "RISING": 1, + "FALLING": 2, + "CHANGING": 3, + "GT": 4, + "LT": 5, + "GEQ": 6, + "LEQ": 7, + "EQ": 8, + "NEQ": 9, + } + + self.registers = self.make_registers(self.base_addr) + self.sample_mem = self.make_sample_mem(self.registers.max_addr) + self.define_signals() + + def check_config(self, config): + # Check for unrecognized options + valid_options = [ + "type", + "sample_depth", + "probes", + "triggers", + "trigger_loc", + "trigger_mode", + ] + for option in config: + if option not in valid_options: + warn(f"Ignoring unrecognized option '{option}' in Logic Analyzer.") + + # Check sample depth is provided and positive + if "sample_depth" not in config: + raise ValueError("Logic Analyzer must have sample_depth specified.") + + if not isinstance(config["sample_depth"], int): + raise ValueError("Logic Analyzer sample_depth must be an integer.") + + if config["sample_depth"] <= 0: + raise ValueError("Logic Analyzer sample_depth must be positive.") + + # Check probes + if "probes" not in config: + raise ValueError("Logic Analyzer must have at least one probe specified.") + + if len(config["probes"]) == 0: + raise ValueError("Logic Analyzer must have at least one probe specified.") + + for name, width in config["probes"].items(): + if width < 0: + raise ValueError(f"Width of probe {name} must be positive.") + + # Check triggers + if "triggers" not in config: + raise ValueError("Logic Analyzer must have at least one trigger specified.") + + if len(config["triggers"]) == 0: + raise ValueError("Logic Analyzer must have at least one trigger specified.") + + # Check trigger location + if "trigger_loc" in config: + if not isinstance(config["trigger_loc"], int): + raise ValueError("Trigger location must be an integer.") + + if config["trigger_loc"] < 0: + raise ValueError("Trigger location must be positive.") + + if config["trigger_loc"] > config["sample_depth"]: + raise ValueError("Trigger location cannot exceed sample depth.") + + # Check trigger mode + if "trigger_mode" in config: + valid_modes = ["single_shot", "incremental", "immediate"] + if config["trigger_mode"] not in valid_modes: + raise ValueError( + f"Unrecognized trigger mode {config['trigger_mode']} provided." + ) + + # Check triggers themselves + for trigger in config["triggers"]: + if not isinstance(trigger, str): + raise ValueError("Trigger must be specified with a string.") + + # Trigger conditions may be composed of either two or three components, + # depending on the operation specified. In the case of operations that + # don't need an argument (like DISABLE, RISING, FALLING, CHANGING) or + # three statements in + + # Check the trigger operations + components = trigger.strip().split(" ") + if len(components) == 2: + name, op = components + if op not in ["DISABLE", "RISING", "FALLING", "CHANGING"]: + raise ValueError( + f"Unable to interpret trigger condition '{trigger}'." + ) + + elif len(components) == 3: + name, op, arg = components + if op not in ["GT", "LT", "GEQ", "LEQ", "EQ", "NEQ"]: + raise ValueError( + f"Unable to interpret trigger condition '{trigger}'." + ) + + else: + raise ValueError(f"Unable to interpret trigger condition '{trigger}'.") + + # Check probe names + if components[0] not in config["probes"]: + raise ValueError(f"Unknown probe name '{components[0]}' specified.") + + def define_signals(self): + # Bus Input + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal(1) + self.valid_i = Signal(1) + + # Bus Output + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal(1) + self.valid_o = Signal(1) + + # Probes + self.probe_signals = {} + for name, width in self.config["probes"].items(): + self.probe_signals[name] = { + "top_level": Signal(width), + "prev": Signal(width), + "trigger_arg": getattr(self.registers, f"{name}_arg"), + "trigger_op": getattr(self.registers, f"{name}_op"), + "triggered": Signal(1), + } + + # Global trigger. High if any probe is triggered. + self.trig = Signal(1) + + def make_registers(self, base_addr): + # The logic analyzer uses an IO core to handle inputs to the FSM and trigger comparators + register_config = { + "inputs": { + "state": 4, + "read_pointer": ceil(log2(self.config["sample_depth"])), + "write_pointer": ceil(log2(self.config["sample_depth"])), + }, + "outputs": { + "trigger_loc": ceil(log2(self.config["sample_depth"])), + "trigger_mode": 2, + "request_start": 1, + "request_stop": 1, + }, + } + + for name, width in self.config["probes"].items(): + register_config["outputs"][name + "_arg"] = width + register_config["outputs"][name + "_op"] = 4 + + return IOCore(register_config, base_addr, self.interface) + + def make_sample_mem(self, base_addr): + sample_mem_config = { + "width": sum(self.config["probes"].values()), + "depth": self.config["sample_depth"], + } + + return ReadOnlyMemoryCore(sample_mem_config, base_addr, self.interface) + + def run_triggers(self, m): + # Run the trigger for each individual probe + for name, attrs in self.probe_signals.items(): + top_level = attrs["top_level"] + prev = attrs["prev"] + trigger_arg = attrs["trigger_arg"] + trigger_op = attrs["trigger_op"] + triggered = attrs["triggered"] + + # Save the previous value to a register so we can do rising/falling edge detection later! + m.d.sync += prev.eq(top_level) + + with m.If(trigger_op == self.operations["DISABLE"]): + m.d.comb += triggered.eq(0) + + with m.Elif(trigger_op == self.operations["RISING"]): + m.d.comb += triggered.eq((top_level) & (~prev)) + + with m.Elif(trigger_op == self.operations["FALLING"]): + m.d.comb += triggered.eq((~top_level) & (prev)) + + with m.Elif(trigger_op == self.operations["CHANGING"]): + m.d.comb += triggered.eq(top_level != prev) + + with m.Elif(trigger_op == self.operations["GT"]): + m.d.comb += triggered.eq(top_level > trigger_arg) + + with m.Elif(trigger_op == self.operations["LT"]): + m.d.comb += triggered.eq(top_level < trigger_arg) + + with m.Elif(trigger_op == self.operations["GEQ"]): + m.d.comb += triggered.eq(top_level >= trigger_arg) + + with m.Elif(trigger_op == self.operations["LEQ"]): + m.d.comb += triggered.eq(top_level <= trigger_arg) + + with m.Elif(trigger_op == self.operations["EQ"]): + m.d.comb += triggered.eq(top_level == trigger_arg) + + with m.Elif(trigger_op == self.operations["NEQ"]): + m.d.comb += triggered.eq(top_level != trigger_arg) + + with m.Else(): + m.d.comb += triggered.eq(0) + + # Combine all the triggers + m.d.comb += self.trig.eq( + Cat(attrs["triggered"] for attrs in self.probe_signals.values()).any() + ) + + def run_state_machine(self, m): + self.prev_request_start = Signal(1) + self.prev_request_stop = Signal(1) + + # Rising edge detection for start/stop requests + m.d.sync += self.prev_request_start.eq(self.registers.request_start) + m.d.sync += self.prev_request_stop.eq(self.registers.request_stop) + + m.d.comb += self.sample_mem.user_addr.eq(self.registers.write_pointer) + + with m.If(self.registers.state == self.states["IDLE"]): + m.d.sync += self.registers.write_pointer.eq(0) + m.d.sync += self.registers.read_pointer.eq(0) + m.d.sync += self.sample_mem.user_we.eq(0) # or something like this + + with m.If((self.registers.request_start) & (~self.prev_request_start)): + m.d.sync += self.registers.state.eq(self.states["MOVE_TO_POSITION"]) + + with m.Elif(self.registers.state == self.states["MOVE_TO_POSITION"]): + m.d.sync += self.registers.write_pointer.eq( + self.registers.write_pointer + 1 + ) + m.d.sync += self.sample_mem.user_we.eq(1) + + with m.If(self.registers.write_pointer == self.registers.trigger_loc): + with m.If(self.trig): + m.d.sync += self.registers.state.eq(self.states["CAPTURING"]) + + with m.Else(): + m.d.sync += self.registers.state.eq(self.states["IN_POSITION"]) + + with m.Elif(self.registers.state == self.states["IN_POSITION"]): + m.d.sync += self.registers.write_pointer.eq( + (self.registers.write_pointer + 1) % self.config["sample_depth"] + ) + m.d.sync += self.registers.read_pointer.eq( + (self.registers.read_pointer + 1) % self.config["sample_depth"] + ) + m.d.sync += self.sample_mem.user_we.eq(1) + + with m.If(self.trig): + m.d.sync += self.registers.state.eq(self.states["CAPTURING"]) + + with m.Elif(self.registers.state == self.states["CAPTURING"]): + with m.If(self.registers.write_pointer == self.registers.read_pointer): + m.d.sync += self.sample_mem.user_we.eq(0) + m.d.sync += self.registers.state.eq(self.states["CAPTURED"]) + + with m.Else(): + m.d.sync += self.registers.write_pointer.eq( + (self.registers.write_pointer + 1) % self.config["sample_depth"] + ) + + with m.If((self.registers.request_stop) & (~self.prev_request_stop)): + m.d.sync += self.registers.state.eq(self.states["IDLE"]) + + def elaborate(self, platform): + m = Module() + + # Add registers and sample memory as submodules + m.submodules["registers"] = self.registers + m.submodules["sample_mem"] = self.sample_mem + + # Concat all the probes together, and feed to input of sample memory + # (it is necessary to reverse the order such that first probe occupies + # the lowest location in memory) + m.d.comb += self.sample_mem.user_data.eq( + Cat([p["top_level"] for p in self.probe_signals.values()][::-1]) + ) + + self.run_state_machine(m) + self.run_triggers(m) + + # Wire internal modules + m.d.comb += [ + self.registers.addr_i.eq(self.addr_i), + self.registers.data_i.eq(self.data_i), + self.registers.rw_i.eq(self.rw_i), + self.registers.valid_i.eq(self.valid_i), + self.sample_mem.addr_i.eq(self.registers.addr_o), + self.sample_mem.data_i.eq(self.registers.data_o), + self.sample_mem.rw_i.eq(self.registers.rw_o), + self.sample_mem.valid_i.eq(self.registers.valid_o), + self.addr_o.eq(self.sample_mem.addr_o), + self.data_o.eq(self.sample_mem.data_o), + self.rw_o.eq(self.sample_mem.rw_o), + self.valid_o.eq(self.sample_mem.valid_o), + ] + + return m + + def get_top_level_ports(self): + return [p["top_level"] for p in self.probe_signals.values()] + + def get_max_addr(self): + return self.sample_mem.get_max_addr() + + def set_triggers(self): + # reset all triggers to zero + for name in self.probe_signals.keys(): + self.registers.set_probe(name + "_op", 0) + self.registers.set_probe(name + "_arg", 0) + + # set triggers + for trigger in self.config["triggers"]: + components = trigger.strip().split(" ") + + # Handle triggers that don't need an argument + if len(components) == 2: + name, op = components + self.registers.set_probe(name + "_op", self.operations[op]) + + # Handle triggers that do need an argument + elif len(components) == 3: + name, op, arg = components + self.registers.set_probe(name + "_op", self.operations[op]) + self.registers.set_probe(name + "_arg", int(arg)) + + def capture(self, verbose=False): + print_if_verbose = lambda x: print(x) if verbose else None + + # If core is not in IDLE state, request that it return to IDLE + print_if_verbose(" -> Resetting core...") + state = self.registers.get_probe("state") + if state != self.states["IDLE"]: + self.registers.set_probe("request_stop", 0) + self.registers.set_probe("request_stop", 1) + self.registers.set_probe("request_stop", 0) + + if self.registers.get_probe("state") != self.states["IDLE"]: + raise ValueError("Logic analyzer did not reset to IDLE state.") + + # Set triggers + print_if_verbose(" -> Setting triggers...") + self.set_triggers() + + # Set trigger mode, default to single-shot if user didn't specify a mode + print_if_verbose(" -> Setting trigger mode...") + if "trigger_mode" in self.config: + self.registers.set_probe("trigger_mode", self.config["trigger_mode"]) + + else: + self.registers.set_probe("trigger_mode", self.trigger_modes["SINGLE_SHOT"]) + + # Set trigger location + print_if_verbose(" -> Setting trigger location...") + self.registers.set_probe("trigger_loc", self.config["trigger_loc"]) + + # Send a start request to the state machine + print_if_verbose(" -> Starting capture...") + self.registers.set_probe("request_start", 1) + self.registers.set_probe("request_start", 0) + + # Poll the state machine's state, and wait for the capture to complete + print_if_verbose(" -> Waiting for capture to complete...") + while self.registers.get_probe("state") != self.states["CAPTURED"]: + pass + + # Read out the entirety of the sample memory + print_if_verbose(" -> Reading sample memory contents...") + addrs = list(range(self.config["sample_depth"])) + raw_capture = self.sample_mem.read_from_user_addr(addrs) + + # Revolve the memory around the read_pointer, such that all the beginning + # of the caputure is at the first element + print_if_verbose(" -> Checking read pointer and revolving memory...") + read_pointer = self.registers.get_probe("read_pointer") + + data = raw_capture[read_pointer:] + raw_capture[:read_pointer] + return LogicAnalyzerCapture(data, self.config) + + +class LogicAnalyzerCapture: + def __init__(self, data, config): + self.data = data + self.config = config + + def get_trigger_loc(self): + return self.config["trigger_loc"] + + def get_trace(self, probe_name): + # sum up the widths of all the probes below this one + lower = 0 + for name, width in self.config["probes"].items(): + if name == probe_name: + break + + lower += width + + # add the width of the probe we'd like + upper = lower + self.config["probes"][probe_name] + + total_probe_width = sum(self.config["probes"].values()) + binary = [f"{d:0{total_probe_width}b}" for d in self.data] + return [int(b[lower:upper], 2) for b in binary] + + def export_vcd(self, path): + from vcd import VCDWriter + from datetime import datetime + + # Use the same datetime format that iVerilog uses + timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y") + vcd_file = open(path, "w") + + with VCDWriter(vcd_file, "10 ns", timestamp, "manta") as writer: + # each probe has a name, width, and writer associated with it + signals = [] + for name, width in self.config["probes"].items(): + signal = { + "name": name, + "width": width, + "data": self.get_trace(name), + "var": writer.register_var("manta", name, "wire", size=width), + } + signals.append(signal) + + clock = writer.register_var("manta", "clk", "wire", size=1) + trigger = writer.register_var("manta", "trigger", "wire", size=1) + + # add the data to each probe in the vcd file + for timestamp in range(0, 2 * len(self.data)): + # run the clock + writer.change(clock, timestamp, timestamp % 2 == 0) + + # set the trigger + triggered = (timestamp // 2) >= self.get_trigger_loc() + writer.change(trigger, timestamp, triggered) + + # add other signals + for signal in signals: + var = signal["var"] + sample = signal["data"][timestamp // 2] + + writer.change(var, timestamp, sample) + + vcd_file.close() + + def export_playback_module(self, path): + return LogicAnalyzerPlayback(self.data, self.config) + + def export_playback_verilog(self, path): + la = LogicAnalyzerPlayback(self.data, self.config) + from amaranth.back import verilog + + with open(path, "w") as f: + f.write( + verilog.convert( + la, + name="logic_analyzer_playback", + ports=la.get_top_level_ports(), + strip_internal_attrs=True, + ) + ) + + +class LogicAnalyzerPlayback(Elaboratable): + def __init__(self, data, config): + self.data = data + self.config = config + + # State Machine + self.enable = Signal(1) + self.done = Signal(1) + + # Top-Level Probe signals + self.top_level_probes = {} + for name, width in self.config["probes"].items(): + self.top_level_probes[name] = Signal(width, name=name) + + # Instantiate memory + self.mem = Memory( + depth=self.config["sample_depth"], + width=sum(self.config["probes"].values()), + init=self.data, + ) + + self.read_port = self.mem.read_port() + + def elaborate(self, platform): + m = Module() + m.submodules["mem"] = self.mem + m.d.comb += self.read_port.en.eq(1) + + # Assign the probe values by part-selecting from the data port + lower = 0 + for name, width in reversed(self.config["probes"].items()): + signal = self.top_level_probes[name] + + # Set output probe to zero if we're not + with m.If(~self.done): + m.d.comb += signal.eq(self.read_port.data[lower : lower + width]) + + with m.Else(): + m.d.comb += signal.eq(0) + + lower += width + + # Iterate through the samples if saved + with m.If((self.enable) & (~self.done)): + with m.If(self.read_port.addr < (self.config["sample_depth"] - 1)): + m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1) + + with m.Else(): + m.d.sync += self.done.eq(1) + + return m + + def get_top_level_ports(self): + return [self.enable, self.done] + list(self.top_level_probes.values()) diff --git a/src/manta/manta.py b/src/manta/manta.py new file mode 100644 index 0000000..073f55a --- /dev/null +++ b/src/manta/manta.py @@ -0,0 +1,170 @@ +from amaranth import * +from warnings import warn +from .uart import UARTInterface + +# from .ethernet import EthernetInterface +from .io_core import IOCore +from .memory_core import ReadOnlyMemoryCore +from .logic_analyzer_core import LogicAnalyzerCore + + +class Manta(Elaboratable): + def __init__(self, config): + # load config from either a configuration file or a dictionary. Users primarily use the + # config file, but the dictionary is included for internal tests. + + if isinstance(config, str): + self.config = self.read_config_file(config) + + if isinstance(config, dict): + self.config = config + + self.check_config() + + self.interface = self.get_interface() + self.cores = self.get_cores() + self.add_friendly_core_names() + + def read_config_file(self, path): + """ + Take path to configuration file, and retun the configuration as a python list/dict object. + """ + + extension = path.split(".")[-1] + + if "json" in extension: + with open(path, "r") as f: + import json + + return json.load(f) + + elif "yaml" in extension or "yml" in extension: + with open(path, "r") as f: + import yaml + + return yaml.safe_load(f) + + else: + raise ValueError("Unable to recognize configuration file extension.") + + def check_config(self): + if "cores" not in self.config: + raise ValueError("No cores specified in configuration file.") + + if not len(self.config["cores"]) > 0: + raise ValueError("Must specify at least one core.") + + for name, attrs in self.config["cores"].items(): + # make sure core type is specified + if "type" not in attrs: + raise ValueError(f"No type specified for core {name}.") + + if attrs["type"] not in ["logic_analyzer", "io", "memory_read_only"]: + raise ValueError(f"Unrecognized core type specified for {name}.") + + def get_interface(self): + if "uart" in self.config: + return UARTInterface(self.config["uart"]) + + elif "ethernet" in self.config: + return EthernetInterface(self.config["ethernet"]) + + else: + raise ValueError("Unrecognized interface specified.") + + def get_cores(self): + """ """ + + cores = {} + base_addr = 0 + for name, attrs in self.config["cores"].items(): + if attrs["type"] == "io": + core = IOCore(attrs, base_addr, self.interface) + + elif attrs["type"] == "logic_analyzer": + core = LogicAnalyzerCore(attrs, base_addr, self.interface) + + elif attrs["type"] == "memory_read_only": + core = ReadOnlyMemoryCore(attrs, base_addr, self.interface) + + # make sure we're not out of address space + if core.get_max_addr() > (2**16) - 1: + raise ValueError( + f"Ran out of address space to allocate to core {name}." + ) + + # Make the next core's base address start one address after the previous one's + base_addr = core.get_max_addr() + 1 + cores[name] = core + + return cores + + def add_friendly_core_names(self): + """ + Add cores to the instance under a friendly name - ie, a core named `my_core` belonging + to a Manta instance `m` could be obtained with `m.cores["my_core"]`, but this allows + it to be obtained with `m.my_core`. Which is way nicer. + """ + + for name, instance in self.cores.items(): + if not hasattr(self, name): + setattr(self, name, instance) + + else: + raise ValueError( + "Cannot add object to Manta instance - name is already taken!" + ) + + def elaborate(self, platform): + # make a module object + # add all the submodules + # connect them together, which consists of: + # connect interface to first core + # connect cores to each other + # connect interface to last core + + m = Module() + + # Add interface as submodule + m.submodules["interface"] = self.interface + + # Add all cores as submodules + for name, instance in self.cores.items(): + m.submodules[name] = instance + + # Connect first/last cores to interface output/input respectively + core_instances = list(self.cores.values()) + first_core = core_instances[0] + last_core = core_instances[-1] + m.d.comb += [ + first_core.addr_i.eq(self.interface.addr_o), + first_core.data_i.eq(self.interface.data_o), + first_core.rw_i.eq(self.interface.rw_o), + first_core.valid_i.eq(self.interface.valid_o), + self.interface.addr_i.eq(last_core.addr_o), + self.interface.data_i.eq(last_core.data_o), + self.interface.rw_i.eq(last_core.rw_o), + self.interface.valid_i.eq(last_core.valid_o), + ] + + # Connect output of ith core to input of (i+1)th core + for i in range(len(core_instances) - 1): + ith_core = core_instances[i] + i_plus_oneth_core = core_instances[i + 1] + + m.d.comb += [ + i_plus_oneth_core.addr_i.eq(ith_core.addr_o), + i_plus_oneth_core.data_i.eq(ith_core.data_o), + i_plus_oneth_core.rw_i.eq(ith_core.rw_o), + i_plus_oneth_core.valid_i.eq(ith_core.valid_o), + ] + + return m + + def get_top_level_ports(self): + ports = self.interface.get_top_level_ports() + + for name, instance in self.cores.items(): + ports += instance.get_top_level_ports() + + return ports diff --git a/src/manta/manta_def_tmpl.v b/src/manta/manta_def_tmpl.v deleted file mode 100644 index 252a858..0000000 --- a/src/manta/manta_def_tmpl.v +++ /dev/null @@ -1,34 +0,0 @@ -/* -This module was generated with Manta /* VERSION */ on /* TIMESTAMP */ by /* USER */ - -If this breaks or if you've got spicy formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! - -manta manta_inst ( - .clk(clk), - - /* EX_INST_PORTS */); - -*/ - -module manta ( - input wire clk, - - /* TOP_LEVEL_PORTS */); - - - /* INTERFACE_RX */ - - /* CORE_CHAIN */ - - /* INTERFACE_TX */ - -endmodule - -/* ---- Module Definitions ---- */ - -/* MODULE_DEFS */ \ No newline at end of file diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py new file mode 100644 index 0000000..cf4d9ae --- /dev/null +++ b/src/manta/memory_core.py @@ -0,0 +1,205 @@ +from amaranth import * +from warnings import warn +from .utils import * +from math import ceil + + +class ReadOnlyMemoryCore(Elaboratable): + def __init__(self, config, base_addr, interface): + self.config = config + self.base_addr = base_addr + self.interface = interface + + self.check_config(config) + + self.depth = self.config["depth"] + self.width = self.config["width"] + self.max_addr = self.base_addr + (self.depth * ceil(self.width / 16)) + + self.define_signals() + self.define_mems() + + def check_config(self, config): + # Check for unrecognized options + valid_options = ["type", "depth", "width"] + for option in config: + if option not in valid_options: + warn(f"Ignoring unrecognized option '{option}' in memory core.") + + # Check depth is provided and positive + if "depth" not in config: + raise ValueError("Depth of memory core must be specified.") + + if not isinstance(config["depth"], int): + raise ValueError("Depth of memory core must be an integer.") + + if config["depth"] <= 0: + raise ValueError("Depth of memory core must be positive. ") + + # Check width is provided and positive + if "width" not in config: + raise ValueError("Width of memory core must be specified.") + + if not isinstance(config["width"], int): + raise ValueError("Width of memory core must be an integer.") + + if config["width"] <= 0: + raise ValueError("Width of memory core must be positive. ") + + def define_signals(self): + # Bus Input + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal(1) + self.valid_i = Signal(1) + + # Bus Pipelining + self.addr_pipe = [Signal(16) for _ in range(3)] + self.data_pipe = [Signal(16) for _ in range(3)] + self.rw_pipe = [Signal(1) for _ in range(3)] + self.valid_pipe = [Signal(1) for _ in range(3)] + + # Bus Output + self.addr_o = Signal(16, reset=0) + self.data_o = Signal(16, reset=0) + self.rw_o = Signal(1, reset=0) + self.valid_o = Signal(1, reset=0) + + # User Port + self.user_addr = Signal(range(self.depth)) + self.user_data = Signal(self.width) + self.user_we = Signal(1) + + def pipeline_bus(self, m): + # Pipelining + m.d.sync += self.addr_pipe[0].eq(self.addr_i) + m.d.sync += self.data_pipe[0].eq(self.data_i) + m.d.sync += self.rw_pipe[0].eq(self.rw_i) + m.d.sync += self.valid_pipe[0].eq(self.valid_i) + + for i in range(1, 3): + m.d.sync += self.addr_pipe[i].eq(self.addr_pipe[i - 1]) + m.d.sync += self.data_pipe[i].eq(self.data_pipe[i - 1]) + m.d.sync += self.rw_pipe[i].eq(self.rw_pipe[i - 1]) + m.d.sync += self.valid_pipe[i].eq(self.valid_pipe[i - 1]) + + m.d.sync += self.addr_o.eq(self.addr_pipe[2]) + m.d.sync += self.data_o.eq(self.data_pipe[2]) + m.d.sync += self.rw_o.eq(self.rw_pipe[2]) + m.d.sync += self.valid_o.eq(self.valid_pipe[2]) + + def define_mems(self): + # ok there's three cases: + # 1. integer number of 16 bit mems + # 2. integer number of 16 bit mems + partial mem + # 3. just the partial mem (width < 16) + + # Only one, partial-width memory is needed + if self.width < 16: + self.mems = [Memory(depth=self.depth, width=self.width)] + + # Only full-width memories are needed + elif self.width % 16 == 0: + self.mems = [ + Memory(depth=self.depth, width=16) for _ in range(self.width // 16) + ] + + # Both full-width and partial memories are needed + else: + self.mems = [ + Memory(depth=self.depth, width=16) for i in range(self.width // 16) + ] + self.mems += [Memory(depth=self.depth, width=self.width % 16)] + + def handle_read_ports(self, m): + # These are tied to the bus + for i, mem in enumerate(self.mems): + read_port = mem.read_port() + m.d.comb += read_port.en.eq(1) + + start_addr = self.base_addr + (i * self.depth) + stop_addr = start_addr + self.depth - 1 + + # Throw BRAM operations into the front of the pipeline + with m.If( + (self.valid_i) + & (~self.rw_i) + & (self.addr_i >= start_addr) + & (self.addr_i <= stop_addr) + ): + m.d.sync += read_port.addr.eq(self.addr_i - start_addr) + + # Pull BRAM reads from the back of the pipeline + with m.If( + (self.valid_pipe[2]) + & (~self.rw_pipe[2]) + & (self.addr_pipe[2] >= start_addr) + & (self.addr_pipe[2] <= stop_addr) + ): + m.d.sync += self.data_o.eq(read_port.data) + + def handle_write_ports(self, m): + # These are given to the user + for i, mem in enumerate(self.mems): + write_port = mem.write_port() + + m.d.comb += write_port.addr.eq(self.user_addr) + m.d.comb += write_port.data.eq(self.user_data[16 * i : 16 * (i + 1)]) + m.d.comb += write_port.en.eq(self.user_we) + + def elaborate(self, platform): + m = Module() + + # Add memories as submodules + for i, mem in enumerate(self.mems): + m.submodules[f"mem_{i}"] = mem + + self.pipeline_bus(m) + self.handle_read_ports(m) + self.handle_write_ports(m) + return m + + def get_top_level_ports(self): + return [self.user_addr, self.user_data, self.user_we] + + def get_max_addr(self): + return self.max_addr + + def read_from_user_addr(self, addrs): + """ + Read the memory stored at the provided address, as seen from the user side. + """ + + # Convert user address space to bus address space + # (for instance, for a core with base address 10 and width 33, + # reading from address 4 is actually a read from address 14 and address 14 + depth, and address 14 + 2*depth) + + if isinstance(addrs, int): + return self.read_from_user_addr([addrs])[0] + + bus_addrs = [] + for addr in addrs: + bus_addrs += [ + addr + self.base_addr + i * self.depth for i in range(len(self.mems)) + ] + + datas = self.interface.read(bus_addrs) + data_chunks = split_into_chunks(datas, len(self.mems)) + return [words_to_value(chunk) for chunk in data_chunks] + + # def write_to_user_addr(self, addrs, datas): + # """ + # Read from the address + # """ + + # bus_addrs = [] + # for addr in addrs: + # bus_addrs += [ + # addr + self.base_addr + i * self.depth for i in range(len(self.mems)) + # ] + + # bus_datas = [] + # for data in datas: + # bus_datas += value_to_words(data) + + # self.interface.write(bus_addrs, bus_datas) diff --git a/src/manta/uart.py b/src/manta/uart.py new file mode 100644 index 0000000..cba6337 --- /dev/null +++ b/src/manta/uart.py @@ -0,0 +1,583 @@ +from amaranth import * +from amaranth.lib.data import ArrayLayout +from warnings import warn +from .utils import * +from serial import Serial + + +class UARTInterface(Elaboratable): + def __init__(self, config): + self.config = config + self.check_config(self.config) + + self.port = config["port"] + self.clock_freq = config["clock_freq"] + self.baudrate = config["baudrate"] + self.clocks_per_baud = int(self.clock_freq // self.baudrate) + + self.define_signals() + + # Set chunk_size, which is the max amount of bytes that the core will + # dump to the OS driver at a time. Since the FPGA will return bytes + # almost instantaneously, this prevents the OS's input buffer from + # overflowing, and dropping bytes. + self.chunk_size = 256 # in bytes + if "chunk_size" in config: + self.chunk_size = config["chunk_size"] + + def check_config(self, config): + # Warn if unrecognized options have been given + recognized_options = ["port", "clock_freq", "baudrate", "chunk_size"] + for option in config: + if option not in recognized_options: + warn( + f"Ignoring unrecognized option '{option}' in UART interface config." + ) + + # Ensure a serial port has been given + if "port" not in config: + raise ValueError("No serial port provided to UART interface.") + + # Ensure clock frequency is provided and positive + if "clock_freq" not in config: + raise ValueError("No clock frequency provided to UART interface.") + + if config["clock_freq"] <= 0: + raise ValueError("Non-positive clock frequency provided to UART interface.") + + # Check that baudrate is provided and positive + if "baudrate" not in config: + raise ValueError("No baudrate provided to UART interface.") + + if config["baudrate"] <= 0: + raise ValueError("Non-positive baudrate provided to UART interface.") + + # Confirm the actual baudrate is within 5% of the target baudrate + clock_freq = config["clock_freq"] + baudrate = config["baudrate"] + clocks_per_baud = clock_freq // baudrate + actual_baudrate = clock_freq / clocks_per_baud + error = 100 * abs(actual_baudrate - baudrate) / baudrate + + if error > 5: + raise ValueError( + "UART interface is unable to match targeted baudrate with specified clock frequency." + ) + + def get_serial_device(self): + """ + Return an open PySerial serial device if one exists, otherwise, open one. + """ + if hasattr(self, "serial_device"): + return self.serial_device + + else: + if self.port != "auto": + self.serial_device = Serial(self.port, self.baudrate, timeout=1) + return self.serial_device + + else: + # Try to autodetect which port to use based on the PID/VID of the device attached. + # This looks for the PID/VID of the FT2232, the primary chip used on the icestick + # and Digilent dev boards. However, folks will likely want to connect other things + # in the future, so in the future we'll probably want to look for other chips as + # well. + + # The FT2232 exposes two serial ports - and for whatever reason it usually has the + # 0th device used for JTAG programming, and the 1st used for UART. So we'll grab + # the 1st. + + import serial.tools.list_ports + + ports = [] + for port in serial.tools.list_ports.comports(): + if (port.vid == 0x403) and (port.pid == 0x6010): + ports.append(port) + + if len(ports) != 2: + raise ValueError( + f"Expected to see two serial ports for FT2232 device, but instead see {len(ports)}." + ) + + if ports[0].serial_number != ports[1].serial_number: + raise ValueError( + f"Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices." + ) + + if ports[0].location > ports[1].location: + chosen_port = ports[0].device + + else: + chosen_port = ports[1].device + + self.serial_device = Serial(chosen_port, self.baudrate, timeout=1) + return self.serial_device + + def get_top_level_ports(self): + return [self.rx, self.tx] + + def read(self, addrs): + """ + Read the data stored in a set of address on Manta's internal memory. Addresses + must be specified as either integers or a list of integers. + """ + + # Handle a single integer address + if isinstance(addrs, int): + return self.read([addrs])[0] + + # Make sure all list elements are integers + if not all(isinstance(a, int) for a in addrs): + raise ValueError("Read address must be an integer or list of integers.") + + # Send read requests, and get responses + ser = self.get_serial_device() + addr_chunks = split_into_chunks(addrs, self.chunk_size) + datas = [] + + for addr_chunk in addr_chunks: + # Encode addrs into read requests + bytes_out = b"".join([f"R{a:04X}\r\n".encode("ascii") for a in addr_chunk]) + ser.write(bytes_out) + + # Read responses have the same length as read requests + bytes_in = ser.read(len(bytes_out)) + + if len(bytes_in) != len(bytes_out): + raise ValueError( + f"Only got {len(bytes_in)} out of {len(bytes_out)} bytes." + ) + + # Split received bytes into individual responses and decode + responses = split_into_chunks(bytes_in, 7) + data_chunk = [self.decode_read_response(r) for r in responses] + datas += data_chunk + + return datas + + def write(self, addrs, datas): + """ + Write the provided data into the provided addresses in Manta's internal memory. + Addresses and data must be specified as either integers or a list of integers. + """ + + # Handle a single integer address and data + if isinstance(addrs, int) and isinstance(datas, int): + return self.write([addrs], [datas]) + + # Make sure address and datas are all integers + if not isinstance(addrs, list) or not isinstance(datas, list): + raise ValueError( + "Write addresses and data must be an integer or list of integers." + ) + + if not all(isinstance(a, int) for a in addrs): + raise ValueError("Write addresses must be all be integers.") + + if not all(isinstance(d, int) for d in datas): + raise ValueError("Write data must all be integers.") + + # I'm not sure if it's necessary to split outputs into chunks + # I think the output buffer doesn't really drop stuff, just the input buffer + + # Encode addrs and datas into write requests + bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, datas)]) + bytes_out = bytes_out.encode("ascii") + ser = self.get_serial_device() + ser.write(bytes_out) + + def decode_read_response(self, response_bytes): + """ + Check that read response is formatted properly, and extract the encoded data if so. + """ + + # Make sure response is not empty + if response_bytes is None: + raise ValueError("Unable to decode read response - no bytes received.") + + # Make sure response is properly encoded + response_ascii = response_bytes.decode("ascii") + + if len(response_ascii) != 7: + raise ValueError( + "Unable to decode read response - wrong number of bytes received." + ) + + if response_ascii[0] != "D": + raise ValueError("Unable to decode read response - incorrect preamble.") + + for i in range(1, 5): + if response_ascii[i] not in "0123456789ABCDEF": + raise ValueError("Unable to decode read response - invalid data byte.") + + if response_ascii[5] != "\r": + raise ValueError("Unable to decode read response - incorrect EOL.") + + if response_ascii[6] != "\n": + raise ValueError("Unable to decode read response - incorrect EOL.") + + return int(response_ascii[1:5], 16) + + def define_signals(self): + self.rx = Signal() + self.tx = Signal() + + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal() + self.valid_o = Signal() + + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + def elaborate(self, platform): + # fancy submoduling and such goes in here + m = Module() + + m.submodules["uart_rx"] = uart_rx = UARTReceiver(self.clocks_per_baud) + m.submodules["bridge_rx"] = bridge_rx = RecieveBridge() + m.submodules["bridge_tx"] = bridge_tx = TransmitBridge() + m.submodules["uart_tx"] = uart_tx = UARTTransmitter(self.clocks_per_baud) + + m.d.comb += [ + # UART RX -> Internal Bus + uart_rx.rx.eq(self.rx), + bridge_rx.data_i.eq(uart_rx.data_o), + bridge_rx.valid_i.eq(uart_rx.valid_o), + self.data_o.eq(bridge_rx.data_o), + self.addr_o.eq(bridge_rx.addr_o), + self.rw_o.eq(bridge_rx.rw_o), + self.valid_o.eq(bridge_rx.valid_o), + # Internal Bus -> UART TX + bridge_tx.data_i.eq(self.data_i), + bridge_tx.rw_i.eq(self.rw_i), + bridge_tx.valid_i.eq(self.valid_i), + uart_tx.data_i.eq(bridge_tx.data_o), + uart_tx.start_i.eq(bridge_tx.start_o), + bridge_tx.done_i.eq(uart_tx.done_o), + self.tx.eq(uart_tx.tx), + ] + return m + + +class UARTReceiver(Elaboratable): + def __init__(self, clocks_per_baud): + self.clocks_per_baud = clocks_per_baud + + # Top-Level Ports + self.rx = Signal() + self.data_o = Signal(8, reset=0) + self.valid_o = Signal(1, reset=0) + + # Internal Signals + self.busy = Signal() + self.bit_index = Signal(range(10)) + self.baud_counter = Signal(range(2 * clocks_per_baud)) + + self.rx_d = Signal() + self.rx_q = Signal() + self.rx_q_prev = Signal() + + def elaborate(self, platform): + m = Module() + + # Two Flip-Flop Synchronizer + m.d.sync += [ + self.rx_d.eq(self.rx), + self.rx_q.eq(self.rx_d), + self.rx_q_prev.eq(self.rx_q), + ] + + m.d.sync += self.valid_o.eq(0) + + with m.If(~self.busy): + with m.If((~self.rx_q) & (self.rx_q_prev)): + m.d.sync += self.busy.eq(1) + m.d.sync += self.bit_index.eq(8) + m.d.sync += self.baud_counter.eq( + self.clocks_per_baud + (self.clocks_per_baud // 2) - 2 + ) + + with m.Else(): + with m.If(self.baud_counter == 0): + with m.If(self.bit_index == 0): + m.d.sync += self.valid_o.eq(1) + m.d.sync += self.busy.eq(0) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.baud_counter.eq(0) + + with m.Else(): + # m.d.sync += self.data_o.eq(Cat(self.rx_q, self.data_o[0:7])) + m.d.sync += self.data_o.eq(Cat(self.data_o[1:8], self.rx_q)) + m.d.sync += self.bit_index.eq(self.bit_index - 1) + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + + with m.Else(): + m.d.sync += self.baud_counter.eq(self.baud_counter - 1) + + return m + + +class RecieveBridge(Elaboratable): + def __init__(self): + # Top-Level Ports + self.data_i = Signal(8) + self.valid_i = Signal() + + self.addr_o = Signal(16, reset=0) + self.data_o = Signal(16, reset=0) + self.rw_o = Signal(1, reset=0) + self.valid_o = Signal(1, reset=0) + + # State Machine + self.IDLE_STATE = 0 + self.READ_STATE = 1 + self.WRITE_STATE = 2 + + # Internal Signals + self.buffer = Signal(ArrayLayout(4, 8), reset_less=True) + self.state = Signal(2, reset=self.IDLE_STATE) + self.byte_num = Signal(4, reset=0) + self.is_eol = Signal() + self.is_ascii_hex = Signal() + self.from_ascii_hex = Signal(8) + + def drive_ascii_signals(self, m): + # Decode 0-9 + with m.If((self.data_i >= 0x30) & (self.data_i <= 0x39)): + m.d.comb += self.is_ascii_hex.eq(1) + m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x30) + + # Decode A-F + with m.Elif((self.data_i >= 0x41) & (self.data_i <= 0x46)): + m.d.comb += self.is_ascii_hex.eq(1) + m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x41 + 10) + + with m.Else(): + m.d.comb += self.is_ascii_hex.eq(0) + m.d.comb += self.from_ascii_hex.eq(0) + + with m.If((self.data_i == ord("\r")) | (self.data_i == ord("\n"))): + m.d.comb += self.is_eol.eq(1) + + with m.Else(): + m.d.comb += self.is_eol.eq(0) + + def drive_output_bus(self, m): + with m.If( + (self.state == self.READ_STATE) & (self.byte_num == 4) & (self.is_eol) + ): + m.d.comb += self.addr_o.eq( + Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) + ) + m.d.comb += self.data_o.eq(0) + m.d.comb += self.valid_o.eq(1) + m.d.comb += self.rw_o.eq(0) + + with m.Elif( + (self.state == self.WRITE_STATE) & (self.byte_num == 8) & (self.is_eol) + ): + m.d.comb += self.addr_o.eq( + Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) + ) + m.d.comb += self.data_o.eq( + Cat(self.buffer[7], self.buffer[6], self.buffer[5], self.buffer[4]) + ) + m.d.comb += self.valid_o.eq(1) + m.d.comb += self.rw_o.eq(1) + + with m.Else(): + m.d.comb += self.addr_o.eq(0) + m.d.comb += self.data_o.eq(0) + m.d.comb += self.rw_o.eq(0) + m.d.comb += self.valid_o.eq(0) + + def drive_fsm(self, m): + with m.If(self.valid_i): + with m.If(self.state == self.IDLE_STATE): + m.d.sync += self.byte_num.eq(0) + + with m.If(self.data_i == ord("R")): + m.d.sync += self.state.eq(self.READ_STATE) + + with m.Elif(self.data_i == ord("W")): + m.d.sync += self.state.eq(self.WRITE_STATE) + + with m.If(self.state == self.READ_STATE): + # buffer bytes if we don't have enough + with m.If(self.byte_num < 4): + # if bytes aren't valid ASCII then return to IDLE state + with m.If(self.is_ascii_hex == 0): + m.d.sync += self.state.eq(self.IDLE_STATE) + + # otherwise buffer them + with m.Else(): + m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) + m.d.sync += self.byte_num.eq(self.byte_num + 1) + + with m.Else(): + m.d.sync += self.state.eq(self.IDLE_STATE) + + with m.If(self.state == self.WRITE_STATE): + # buffer bytes if we don't have enough + with m.If(self.byte_num < 8): + # if bytes aren't valid ASCII then return to IDLE state + with m.If(self.is_ascii_hex == 0): + m.d.sync += self.state.eq(self.IDLE_STATE) + + # otherwise buffer them + with m.Else(): + m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) + m.d.sync += self.byte_num.eq(self.byte_num + 1) + + with m.Else(): + m.d.sync += self.state.eq(self.IDLE_STATE) + pass + + def elaborate(self, platform): + m = Module() + + self.drive_ascii_signals(m) + self.drive_output_bus(m) + self.drive_fsm(m) + + return m + + +class UARTTransmitter(Elaboratable): + def __init__(self, clocks_per_baud): + self.clocks_per_baud = clocks_per_baud + + # Top-Level Ports + self.data_i = Signal(8) + self.start_i = Signal() + self.done_o = Signal(reset=1) + + self.tx = Signal(reset=1) + + # Internal Signals + self.baud_counter = Signal(range(clocks_per_baud)) + self.buffer = Signal(9) + self.bit_index = Signal(4) + + def elaborate(self, platform): + m = Module() + + with m.If((self.start_i) & (self.done_o)): + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.done_o.eq(0) + m.d.sync += self.tx.eq(0) + + with m.Elif(~self.done_o): + m.d.sync += self.baud_counter.eq(self.baud_counter - 1) + m.d.sync += self.done_o.eq((self.baud_counter == 1) & (self.bit_index == 9)) + + # A baud period has elapsed + with m.If(self.baud_counter == 0): + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + + # Clock out another bit if there are any left + with m.If(self.bit_index < 9): + m.d.sync += self.tx.eq(self.buffer.bit_select(self.bit_index, 1)) + m.d.sync += self.bit_index.eq(self.bit_index + 1) + + # Byte has been sent, send out next one or go to idle + with m.Else(): + with m.If(self.start_i): + m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.tx.eq(0) + + with m.Else(): + m.d.sync += self.done_o.eq(1) + return m + + +class TransmitBridge(Elaboratable): + def __init__(self): + # Top-Level Ports + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + self.data_o = Signal(8, reset=0) + self.start_o = Signal(1) + self.done_i = Signal() + + # Internal Signals + self.buffer = Signal(16, reset=0) + self.count = Signal(4, reset=0) + self.busy = Signal(1, reset=0) + self.to_ascii_hex = Signal(8) + self.n = Signal(4) + + def elaborate(self, platform): + m = Module() + + m.d.comb += self.start_o.eq(self.busy) + + with m.If(~self.busy): + with m.If((self.valid_i) & (~self.rw_i)): + m.d.sync += self.busy.eq(1) + m.d.sync += self.buffer.eq(self.data_i) + + with m.Else(): + # uart_tx is transmitting a byte: + with m.If(self.done_i): + m.d.sync += self.count.eq(self.count + 1) + + # Message has been transmitted + with m.If(self.count > 5): + m.d.sync += self.count.eq(0) + + # Go back to idle, or transmit next message + with m.If((self.valid_i) & (~self.rw_i)): + m.d.sync += self.buffer.eq(self.data_i) + + with m.Else(): + m.d.sync += self.busy.eq(0) + + # define to_ascii_hex + with m.If(self.n < 10): + m.d.comb += self.to_ascii_hex.eq(self.n + 0x30) + with m.Else(): + m.d.comb += self.to_ascii_hex.eq(self.n + 0x41 - 10) + + # run the sequence + with m.If(self.count == 0): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("D")) + + with m.Elif(self.count == 1): + m.d.comb += self.n.eq(self.buffer[12:16]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 2): + m.d.comb += self.n.eq(self.buffer[8:12]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 3): + m.d.comb += self.n.eq(self.buffer[4:8]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 4): + m.d.comb += self.n.eq(self.buffer[0:4]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 5): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("\r")) + + with m.Elif(self.count == 6): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("\n")) + + with m.Else(): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(0) + + return m diff --git a/src/manta/uart_iface/__init__.py b/src/manta/uart_iface/__init__.py deleted file mode 100644 index 98f2ffc..0000000 --- a/src/manta/uart_iface/__init__.py +++ /dev/null @@ -1,186 +0,0 @@ -from ..utils import * - -class UARTInterface: - def __init__(self, config): - # Warn if unrecognized options have been given - for option in config: - if option not in ["port", "clock_freq", "baudrate", "chunk_size", "verbose"]: - print(f"Warning: Ignoring unrecognized option '{option}' in UART interface.") - - # Obtain port. Try to automatically detect port if "auto" is specified - assert "port" in config, "No serial port provided to UART core." - self.port = config["port"] - - # Check that clock frequency is provided and positive - assert "clock_freq" in config, "Clock frequency not provided to UART core." - assert config["clock_freq"] > 0, "Clock frequency must be positive." - self.clock_freq = config["clock_freq"] - - # Check that baudrate is provided and positive - assert "baudrate" in config, "Baudrate not provided to UART core." - assert config["baudrate"] > 0, "Baudrate must be positive." - self.baudrate = config["baudrate"] - - # Confirm core clock is sufficiently fast - clocks_per_baud = self.clock_freq // self.baudrate - assert clocks_per_baud >= 2 - self.clocks_per_baud = clocks_per_baud - - # Confirm we can match baudrate suffeciently well - actual_baudrate = self.clock_freq / clocks_per_baud - baudrate_error = 100 * abs(actual_baudrate - self.baudrate) / self.baudrate - assert baudrate_error <= 5, \ - "Unable to match target baudrate - they differ by {baudrate_error}%" - - # Set chunk_size, which is the max amount of bytes that get dumped - # to the OS driver at a time - self.chunk_size = 256 - if "chunk_size" in config: - self.chunk_size = config["chunk_size"] - - # Set verbosity - self.verbose = False - if "verbose" in config: - self.verbose = config["verbose"] - - def open_port_if_not_alredy_open(self): - if self.port == "auto": - self.port = self.autodetect_port() - - if not hasattr(self, "ser"): - import serial - self.ser = serial.Serial(self.port, self.baudrate) - - def autodetect_port(self): - # as far as I know the FT2232 is the only chip used on the icestick/digilent boards, so just look for that - import serial.tools.list_ports - - recognized_devices = [] - for port in serial.tools.list_ports.comports(): - if (port.vid == 0x403) and (port.pid == 0x6010): - recognized_devices.append(port) - - # board manufacturers seem to always make the 0th serial - # interface on the FT2232 be for programming over JTAG, - # and then the 1st to be for UART. as a result, we always - # grab the device with the larger location - - rd = recognized_devices - assert len(recognized_devices) == 2, f"Expected to see two serial ports for FT2232 device, but instead see {len(recognized_devices)}." - assert rd[0].serial_number == rd[1].serial_number, "Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices." - return rd[0].device if rd[0].location > rd[1].location else rd[1].device - - def decode_response(self, response): - """Make sure reponse from FPGA has the correct format, and return data contained within if so.""" - assert response is not None, "No reponse received." - - response_str = response.decode('ascii') - assert response_str[0] == 'D', "Bad message recieved, incorrect preamble." - assert response_str[-2] == '\r', "Bad message received, incorrect EOL." - assert response_str[-1] == '\n', "Bad message received, incorrect EOL." - assert len(response_str) == 7, f"Wrong number of bytes received, expecting 7 but got {len(response)}." - - return int(response_str[1:5], 16) - - - def read(self, addr): - # Perform type checks, output list of addresses - if isinstance(addr, int): - addrs = [addr] - - elif isinstance(addr, list): - assert all(isinstance(a, int) for a in addr), \ - "Read addresses must be integer or list of integers." - addrs = addr - - else: - raise ValueError("Read addresses must be integer or list of integers.") - - # send data in chunks because the reponses will fill up the OS's - # input buffer in no time flat - self.open_port_if_not_alredy_open() - - inbound_bytes = b"" - for i in range(0, len(addrs), self.chunk_size): - addr_chunk = addrs[i:i+self.chunk_size] - - outbound_bytes = [f"R{addr:04X}\r\n".encode('ascii') for addr in addr_chunk] - outbound_bytes = b"".join(outbound_bytes) - - self.ser.write(outbound_bytes) - - inbound_bytes += self.ser.read(len(outbound_bytes)) - - data = [] - for i in range(0, len(inbound_bytes), 7): - response = inbound_bytes[i:i+7] - data.append(self.decode_response(response)) - - if isinstance(addr, int): - return data[0] - - else: - return data - - def write(self, addr, data): - # Perform type checks, output list of addresses - if isinstance(addr, int): - assert isinstance(data, int), \ - "Data must also be integer if address is integer." - addrs = [addr] - datas = [data] - - elif isinstance(addr, list): - assert all(isinstance(a, int) for a in addr), \ - "Write addresses must be integer or list of integers." - - assert all(isinstance(d, int) for d in data), \ - "Write data must be integer or list of integers." - - assert len(addr) == len(data), \ - "There must be equal number of write addresses and data." - - addrs = addr - datas = data - - else: - raise ValueError("Write addresses and data must be integer or list of integers.") - - # send data in chunks because the reponses will fill up the OS's - # input buffer in no time flat - self.open_port_if_not_alredy_open() - - for i in range(0, len(addrs), self.chunk_size): - addr_chunk = addrs[i:i+self.chunk_size] - data_chunk = datas[i:i+self.chunk_size] - - - outbound_bytes = [f"W{a:04X}{d:04X}\r\n" for a, d in zip(addr_chunk, data_chunk)] - outbound_bytes = [ob.encode('ascii') for ob in outbound_bytes] - outbound_bytes = b"".join(outbound_bytes) - - self.ser.write(outbound_bytes) - - def hdl_top_level_ports(self): - # this should return the probes that we want to connect to top-level, but like as a string of verilog - return ["input wire rx", "output reg tx"] - - def rx_hdl_def(self): - uart_rx_def = VerilogManipulator("uart_iface/uart_rx.v").get_hdl() - bridge_rx_def = VerilogManipulator("uart_iface/bridge_rx.v").get_hdl() - return uart_rx_def + '\n' + bridge_rx_def - - def tx_hdl_def(self): - uart_tx_def = VerilogManipulator("uart_iface/uart_tx.v").get_hdl() - bridge_tx_def = VerilogManipulator("uart_iface/bridge_tx.v").get_hdl() - return bridge_tx_def + '\n' + uart_tx_def - - def rx_hdl_inst(self): - rx = VerilogManipulator("uart_iface/uart_rx_bridge_rx_inst_tmpl.v") - rx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */") - return rx.get_hdl() - - def tx_hdl_inst(self): - tx = VerilogManipulator("uart_iface/uart_tx_bridge_tx_inst_tmpl.v") - tx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */") - return tx.get_hdl() \ No newline at end of file diff --git a/src/manta/uart_iface/bridge_rx.v b/src/manta/uart_iface/bridge_rx.v deleted file mode 100644 index 995b1ab..0000000 --- a/src/manta/uart_iface/bridge_rx.v +++ /dev/null @@ -1,150 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module bridge_rx ( - input wire clk, - - input wire [7:0] data_i, - input wire valid_i, - - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o); - - initial addr_o = 0; - initial data_o = 0; - initial rw_o = 0; - initial valid_o = 0; - - function [3:0] from_ascii_hex; - // convert an ascii char encoding a hex value to - // the corresponding hex value - input [7:0] c; - - if ((c >= 8'h30) && (c <= 8'h39)) from_ascii_hex = c - 8'h30; - else if ((c >= 8'h41) && (c <= 8'h46)) from_ascii_hex = c - 8'h41 + 'd10; - else from_ascii_hex = 0; - endfunction - - function is_ascii_hex; - // checks if a byte is an ascii char encoding a hex digit - input [7:0] c; - - if ((c >= 8'h30) && (c <= 8'h39)) is_ascii_hex = 1; // 0-9 - else if ((c >= 8'h41) && (c <= 8'h46)) is_ascii_hex = 1; // A-F - else is_ascii_hex = 0; - endfunction - - reg [7:0] buffer [7:0]; // = 0; // todo: see if sby will tolerate packed arrays? - - localparam IDLE = 0; - localparam READ = 1; - localparam WRITE = 2; - reg [1:0] state = 0; - reg [3:0] byte_num = 0; - - always @(posedge clk) begin - addr_o <= 0; - data_o <= 0; - rw_o <= 0; - valid_o <= 0; - - if (state == IDLE) begin - byte_num <= 0; - if (valid_i) begin - if (data_i == "R") state <= READ; - if (data_i == "W") state <= WRITE; - end - end - - else begin - if (valid_i) begin - // buffer bytes regardless of if they're good - byte_num <= byte_num + 1; - buffer[byte_num] <= data_i; - - // current transaction specifies a read operation - if(state == READ) begin - - // go to idle if anything doesn't make sense - if(byte_num < 4) begin - if(!is_ascii_hex(data_i)) state <= IDLE; - end - - else if(byte_num == 4) begin - state <= IDLE; - - // put data on the bus if the last byte looks good - if((data_i == 8'h0D) || (data_i == 8'h0A)) begin - addr_o <= (from_ascii_hex(buffer[0]) << 12) | - (from_ascii_hex(buffer[1]) << 8) | - (from_ascii_hex(buffer[2]) << 4) | - (from_ascii_hex(buffer[3])); - data_o <= 0; - rw_o <= 0; - valid_o <= 1; - end - end - end - - // current transaction specifies a write transaction - if(state == WRITE) begin - - // go to idle if anything doesn't make sense - if(byte_num < 8) begin - if(!is_ascii_hex(data_i)) state <= IDLE; - end - - else if(byte_num == 8) begin - state <= IDLE; - - // put data on the bus if the last byte looks good - if((data_i == 8'h0A) || (data_i == 8'h0D)) begin - addr_o <= (from_ascii_hex(buffer[0]) << 12) | - (from_ascii_hex(buffer[1]) << 8) | - (from_ascii_hex(buffer[2]) << 4) | - (from_ascii_hex(buffer[3])); - data_o <= (from_ascii_hex(buffer[4]) << 12) | - (from_ascii_hex(buffer[5]) << 8) | - (from_ascii_hex(buffer[6]) << 4) | - (from_ascii_hex(buffer[7])); - rw_o <= 1; - valid_o <= 1; - end - end - end - end - end - end - -`ifdef FORMAL - always @(posedge clk) begin - // covers - find_any_write_transaction: cover(rw_o == 1); - find_any_read_transaction: cover(rw_o == 0); - - find_specific_write_transaction: - cover(data_o == 16'h1234 && addr_o == 16'h5678 && rw_o == 1 && valid_o == 1); - - find_specific_read_transaction: - cover(addr_o == 16'h1234 && rw_o == 0 && valid_o == 1); - - find_spacey_write_transaction: - cover((rw_o == 1) && ($past(valid_i, 3) == 0)); - - // asserts - no_back_to_back_transactions: - assert( ~(valid_o && $past(valid_o)) ); - - no_invalid_states: - assert(state == IDLE || state == READ || state == WRITE); - - byte_counter_only_increases: - assert(byte_num == $past(byte_num) || byte_num == $past(byte_num) + 1 || byte_num == 0); - end -`endif // FORMAL -endmodule - - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/uart_iface/bridge_tx.v b/src/manta/uart_iface/bridge_tx.v deleted file mode 100644 index 70bbf0d..0000000 --- a/src/manta/uart_iface/bridge_tx.v +++ /dev/null @@ -1,70 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module bridge_tx ( - input wire clk, - - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - output reg [7:0] data_o, - output reg start_o, - input wire done_i); - - function [7:0] to_ascii_hex; - // convert a number from 0-15 into the corresponding ascii char - input [3:0] n; - to_ascii_hex = (n < 10) ? (n + 8'h30) : (n + 8'h41 - 'd10); - endfunction - - localparam PREAMBLE = "D"; - localparam CR = 8'h0D; - localparam LF = 8'h0A; - - reg busy = 0; - reg [15:0] buffer = 0; - reg [3:0] count = 0; - - assign start_o = busy; - - always @(posedge clk) begin - // idle until valid read transaction arrives on bus - if (!busy) begin - if (valid_i && !rw_i) begin - busy <= 1; - buffer <= data_i; - end - end - - if (busy) begin - // uart module is done transmitting a byte - if(done_i) begin - count <= count + 1; - - // message has been transmitted - if (count > 5) begin - count <= 0; - - // go back to idle or transmit next message - if (valid_i && !rw_i) buffer <= data_i; - else busy <= 0; - end - end - end - end - - always @(*) begin - case (count) - 0: data_o = PREAMBLE; - 1: data_o = to_ascii_hex(buffer[15:12]); - 2: data_o = to_ascii_hex(buffer[11:8]); - 3: data_o = to_ascii_hex(buffer[7:4]); - 4: data_o = to_ascii_hex(buffer[3:0]); - 5: data_o = CR; - 6: data_o = LF; - default: data_o = 0; - endcase - end -endmodule -`default_nettype wire \ No newline at end of file diff --git a/src/manta/uart_iface/uart_rx.v b/src/manta/uart_iface/uart_rx.v deleted file mode 100644 index a4e8abb..0000000 --- a/src/manta/uart_iface/uart_rx.v +++ /dev/null @@ -1,62 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -// Modified from Dan Gisselquist's rx_uart module, -// available at https://zipcpu.com/tutorial/ex-09-uartrx.zip - -module uart_rx ( - input wire clk, - - input wire rx, - - output reg [7:0] data_o, - output reg valid_o); - - parameter CLOCKS_PER_BAUD = 0; - localparam IDLE = 0; - localparam BIT_ZERO = 1; - localparam STOP_BIT = 9; - - reg [3:0] state = IDLE; - reg [15:0] baud_counter = 0; - reg zero_baud_counter; - assign zero_baud_counter = (baud_counter == 0); - - // 2FF Synchronizer - reg ck_uart = 1; - reg q_uart = 1; - always @(posedge clk) - { ck_uart, q_uart } <= { q_uart, rx }; - - always @(posedge clk) - if (state == IDLE) begin - state <= IDLE; - baud_counter <= 0; - if (!ck_uart) begin - state <= BIT_ZERO; - baud_counter <= CLOCKS_PER_BAUD+CLOCKS_PER_BAUD/2-1'b1; - end - end - - else if (zero_baud_counter) begin - state <= state + 1; - baud_counter <= CLOCKS_PER_BAUD-1'b1; - if (state == STOP_BIT) begin - state <= IDLE; - baud_counter <= 0; - end - end - - else baud_counter <= baud_counter - 1'b1; - - always @(posedge clk) - if ( (zero_baud_counter) && (state != STOP_BIT) ) - data_o <= {ck_uart, data_o[7:1]}; - - initial valid_o = 1'b0; - always @(posedge clk) - valid_o <= ( (zero_baud_counter) && (state == STOP_BIT) ); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v b/src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v deleted file mode 100644 index 8ff8dec..0000000 --- a/src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v +++ /dev/null @@ -1,20 +0,0 @@ -uart_rx #(.CLOCKS_PER_BAUD(/* CLOCKS_PER_BAUD */)) urx ( - .clk(clk), - .rx(rx), - - .data_o(urx_brx_data), - .valid_o(urx_brx_valid)); - -reg [7:0] urx_brx_data; -reg urx_brx_valid; - -bridge_rx brx ( - .clk(clk), - - .data_i(urx_brx_data), - .valid_i(urx_brx_valid), - - .addr_o(), - .data_o(), - .rw_o(), - .valid_o()); \ No newline at end of file diff --git a/src/manta/uart_iface/uart_tx.v b/src/manta/uart_iface/uart_tx.v deleted file mode 100644 index ea249a7..0000000 --- a/src/manta/uart_iface/uart_tx.v +++ /dev/null @@ -1,61 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module uart_tx ( - input wire clk, - - input wire [7:0] data_i, - input wire start_i, - output reg done_o, - - output reg tx); - - // this module supports only 8N1 serial at a configurable baudrate - parameter CLOCKS_PER_BAUD = 0; - reg [$clog2(CLOCKS_PER_BAUD)-1:0] baud_counter = 0; - - reg [8:0] buffer = 0; - reg [3:0] bit_index = 0; - - initial done_o = 1; - initial tx = 1; - - always @(posedge clk) begin - if (start_i && done_o) begin - baud_counter <= CLOCKS_PER_BAUD - 1; - buffer <= {1'b1, data_i}; - bit_index <= 0; - done_o <= 0; - tx <= 0; - end - - else if (!done_o) begin - baud_counter <= baud_counter - 1; - done_o <= (baud_counter == 1) && (bit_index == 9); - - // a baud period has elapsed - if (baud_counter == 0) begin - baud_counter <= CLOCKS_PER_BAUD - 1; - - // clock out another bit if there are any left - if (bit_index < 9) begin - tx <= buffer[bit_index]; - bit_index <= bit_index + 1; - end - - // byte has been sent, send out next one or go to idle - else begin - if(start_i) begin - buffer <= {1'b1, data_i}; - bit_index <= 0; - tx <= 0; - end - - else done_o <= 1; - end - end - end - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v b/src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v deleted file mode 100644 index bfe68b6..0000000 --- a/src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v +++ /dev/null @@ -1,23 +0,0 @@ -bridge_tx btx ( - .clk(clk), - - .data_i(), - .rw_i(), - .valid_i(), - - .data_o(btx_utx_data), - .start_o(btx_utx_start), - .done_i(utx_btx_done)); - -reg [7:0] btx_utx_data; -reg btx_utx_start; -reg utx_btx_done; - -uart_tx #(.CLOCKS_PER_BAUD(/* CLOCKS_PER_BAUD */)) utx ( - .clk(clk), - - .data_i(btx_utx_data), - .start_i(btx_utx_start), - .done_o(utx_btx_done), - - .tx(tx)); \ No newline at end of file diff --git a/src/manta/utils.py b/src/manta/utils.py index 67decc5..a40fa0a 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,124 +1,129 @@ -import pkgutil +from amaranth.sim import Simulator from math import ceil +import os -def pack_16bit_words(data): - """Takes a list of integers, interprets them as 16-bit integers, and - concatenates them together in little-endian order.""" + +def words_to_value(data): + """ + Takes a list of integers, interprets them as 16-bit integers, and + concatenates them together in little-endian order. + """ for d in data: - if d > 0: assert d < 2**16, "Unsigned integer too large." - if d < 0: assert d < 2**15, "Signed integer too large." + if d > 0 and d > 2**16 - 1: + raise ValueError("Unsigned integer too large.") - return int(''.join([f'{i:016b}' for i in data[::-1]]), 2) + if d < 0 and d < -(2**15 - 1): + raise ValueError("Signed integer too large.") -def unpack_16bit_words(data, n_words): - """Takes a integer, interprets it as a set of 16-bit integers - concatenated together, and splits it into a list of 16-bit numbers""" + return int("".join([f"{i:016b}" for i in data[::-1]]), 2) - assert isinstance(data, int), "Behavior is only defined for nonnegative integers." - assert data >= 0, "Behavior is only defined for nonnegative integers." + +def value_to_words(data, n_words): + """ + Takes a integer, interprets it as a set of 16-bit integers + concatenated together, and splits it into a list of 16-bit numbers. + """ + + if not isinstance(data, int) or data < 0: + raise ValueError("Behavior is only defined for nonnegative integers.") # convert to binary, split into 16-bit chunks, and then convert back to list of int - binary = f'{data:0b}'.zfill(n_words * 16) - return [int(binary[i:i+16], 2) for i in range(0, 16 * n_words, 16)][::-1] - -class VerilogManipulator: - def __init__(self, filepath=None): - if filepath is not None: - self.hdl = pkgutil.get_data(__name__, filepath).decode() - - # scrub any default_nettype or timescale directives from the source - self.hdl = self.hdl.replace("`default_nettype none", "") - self.hdl = self.hdl.replace("`default_nettype wire", "") - self.hdl = self.hdl.replace("`timescale 1ns/1ps", "") - self.hdl = self.hdl.strip() - - # python tries to be cute and automatically convert - # line endings on Windows, but Manta's source comes - # with (and injects) UNIX line endings, so Python - # ends up adding way too many line breaks, so we just - # undo anything it's done when we load the file - self.hdl = self.hdl.replace("\r\n", "\n") - - else: - self.hdl = None - - def sub(self, replace, find): - # sometimes we have integer inputs, want to accomodate - if isinstance(replace, str): - replace_str = replace - - elif isinstance(replace, int): - replace_str = str(replace) - - else: - raise ValueError("Only string and integer arguments supported.") + binary = f"{data:0b}".zfill(n_words * 16) + return [int(binary[i : i + 16], 2) for i in range(0, 16 * n_words, 16)][::-1] - # if the string being subbed in isn't multiline, just - # find-and-replace like normal: - if "\n" not in replace_str: - self.hdl = self.hdl.replace(find, replace_str) +def split_into_chunks(data, chunk_size): + """ + Split a list into a list of lists, where each sublist has length `chunk_size`. + If the list can't be evenly divided into chunks, then the last entry in the + returned list will have length less than `chunk_size`. + """ - # if the string being substituted in is multiline, - # make sure the replace text gets put at the same - # indentation level by adding whitespace to left - # of the line. - else: - for line in self.hdl.split("\n"): - if find in line: - # get whitespace that's on the left side of the line - whitespace = line.rstrip().replace(line.lstrip(), "") - - # add it to every line, except the first - replace_as_lines = replace_str.split("\n") - replace_with_whitespace = f"\n{whitespace}".join(replace_as_lines) - - # replace the first occurance in the HDL with it - self.hdl = self.hdl.replace(find, replace_with_whitespace, 1) - - def get_hdl(self): - return self.hdl - - def net_dec(self, nets, net_type, trailing_comma = False): - """Takes a dictonary of nets in the format {probe: width}, and generates - the net declarations that would go in a Verilog module definition. - - For example, calling net_dec({foo : 1, bar : 4}, "input wire") would produce: - - input wire foo, - input [3:0] wire bar - - Which you'd then slap into your module declaration, along with all the other - inputs and outputs the module needs.""" - - dec = [] - for name, width in nets.items(): - if width == 1: - dec.append(f"{net_type} {name}") - - else: - dec.append(f"{net_type} [{width-1}:0] {name}") - - dec = ",\n".join(dec) - dec = dec + "," if trailing_comma else dec - return dec - - def net_conn(self, nets, trailing_comma = False): - """Takes a dictionary of nets in the format {probe: width}, and generates - the net connections that would go in the Verilog module instantiation. - - For example, calling net_conn({foo: 1, bar: 4}) would produce: - - .foo(foo), - .bar(bar) - - Which you'd then slap into your module instantiation, along with all the other - module inputs and outputs that get connected elsewhere.""" + return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)] - conn = [f".{name}({name})" for name in nets] - conn = ",\n".join(conn) - conn = conn + "," if trailing_comma else conn +def simulate(top, testbench, vcd_path=None): + """ + Run a behavior simulation using Amaranth's built-in simulator `pysim`. Takes + the top-level module to simulate, the testbench process to run, and an optional + path to export a VCD file to. + """ + sim = Simulator(top) + sim.add_clock(1e-6) # 1 MHz + sim.add_sync_process(testbench) - return conn + if vcd_path is None: + sim.run() + + else: + with sim.write_vcd(vcd_path): + sim.run() + + +def verify_register(module, addr, expected_data): + """ + Read the contents of a register out over a module's bus connection, and verify + that it contains the expected data. + + Unfortunately because Amaranth uses generator functions to define processes, + this must be a generator function and thus cannot return a value - it must + yield the next timestep. This means that the comparision with the expected + value must occur inside this function and not somewhere else, it's not + possible to return a value from here, and compare it in the calling function. + """ + + # place read transaction on the bus + yield module.addr_i.eq(addr) + yield module.data_i.eq(0) + yield module.rw_i.eq(0) + yield module.valid_i.eq(1) + yield + yield module.addr_i.eq(0) + yield module.valid_i.eq(0) + + # wait for output to be valid + while not (yield module.valid_o): + yield + + # compare returned value with expected + data = yield (module.data_o) + if data != expected_data: + raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") + + +def write_register(module, addr, data): + """ + Write to a register over a module's bus connection, placing the contents of `data` + at `addr`. + """ + + yield module.addr_i.eq(addr) + yield module.data_i.eq(data) + yield module.rw_i.eq(1) + yield module.valid_i.eq(1) + yield + yield module.valid_i.eq(0) + yield + + +def xilinx_tools_installed(): + """ + Return whether Vivado is installed, by checking if the VIVADO environment variable is set. + + This variable should point to the binary itself, not just the folder it's located in + (ie, /tools/Xilinx/Vivado/2023.1/bin/vivado, not /tools/Xilinx/Vivado/2023.1/bin) + """ + return "VIVADO" in os.environ + + +def ice40_tools_installed(): + """ + Return whether the ice40 tools are installed, by checking if the YOSYS, NEXTPNR_ICE40, + ICEPACK, and ICEPROG environment variables are defined. + + # These variables should point to the binaries themselves, not just the folder it's located in + # (ie, /tools/oss-cad-suite/bin/yosys, not /tools/oss-cad-suite/bin/) + """ + tools = ["YOSYS", "NEXTPNR_ICE40", "ICEPACK", "ICEPROG"] + return all(tool in os.environ for tool in tools) diff --git a/test/auto_gen/invalid_configs/0_mangled_yaml.yaml b/test/auto_gen/invalid_configs/0_mangled_yaml.yaml deleted file mode 100644 index 866e678..0000000 --- a/test/auto_gen/invalid_configs/0_mangled_yaml.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: Q - btnr: 1 - btnc: 1 - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/auto_gen/invalid_configs/1_mangled_yaml.yaml b/test/auto_gen/invalid_configs/1_mangled_yaml.yaml deleted file mode 100644 index c786cdb..0000000 --- a/test/auto_gen/invalid_configs/1_mangled_yaml.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/auto_gen/invalid_configs/2_mangled_yaml.yaml b/test/auto_gen/invalid_configs/2_mangled_yaml.yaml deleted file mode 100644 index 9386d37..0000000 --- a/test/auto_gen/invalid_configs/2_mangled_yaml.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: randomstringthatsnotaninteger - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/auto_gen/run_tests.py b/test/auto_gen/run_tests.py deleted file mode 100644 index 3e5ec4c..0000000 --- a/test/auto_gen/run_tests.py +++ /dev/null @@ -1,56 +0,0 @@ -# try to build manta instances from valid and invalid configuration files - -from os import listdir -from os.path import isfile -from manta import Manta - - -# Valid Configurations - -# test that they make a python API without errors -# TODO: test that their verilog passes lint - -print(" ==== Testing valid configurations ====") -valid_configs_path = "test/auto_gen/valid_configs/" -for config_file in sorted(listdir(valid_configs_path)): - caught_exception = None - try: - m = Manta(valid_configs_path + config_file) - - except Exception as e: - caught_exception = e - - if caught_exception is None: - print(f" -> no exceptions correctly raised by config file {config_file}") - - else: - raise RuntimeError( - f"Configuration {config_file} shouldn't have raised an exception, but raised {caught_exception}" - ) - - -print("\n") - -# Invalid Configurations - -# test that they throw errors when generating a python API - -print(" ==== Testing invalid configurations ====") -invalid_configs_path = "test/auto_gen/invalid_configs/" -for config_file in sorted(listdir(invalid_configs_path)): - caught_exception = None - try: - m = Manta(invalid_configs_path + config_file) - - except Exception as e: - caught_exception = e - - if caught_exception is not None: - print( - f" -> exception correctly raised by config file {config_file}: {caught_exception}" - ) - - else: - raise RuntimeError( - f"Configuration {config_file} should have raised an exception, but did not!" - ) diff --git a/test/auto_gen/valid_configs/0_io_core.yaml b/test/auto_gen/valid_configs/0_io_core.yaml deleted file mode 100644 index 867efbe..0000000 --- a/test/auto_gen/valid_configs/0_io_core.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: 1 - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/auto_gen/valid_configs/1_logic_analyzer.yaml b/test/auto_gen/valid_configs/1_logic_analyzer.yaml deleted file mode 100644 index 107efa8..0000000 --- a/test/auto_gen/valid_configs/1_logic_analyzer.yaml +++ /dev/null @@ -1,19 +0,0 @@ ---- -cores: - my_logic_analyzer: - type: logic_analyzer - sample_depth: 4096 - - probes: - larry: 1 - curly: 1 - moe: 1 - shemp: 4 - - triggers: - - larry && curly && ~moe - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/formal_verification/bridge_rx.sby b/test/formal_verification/bridge_rx.sby deleted file mode 100644 index 93a9ed9..0000000 --- a/test/formal_verification/bridge_rx.sby +++ /dev/null @@ -1,29 +0,0 @@ -[tasks] -basic bmc -nofullskip prove -cover -noverific cover -basic cover : default - -[options] -cover: -mode cover --- -prove: -mode prove --- -bmc: -mode bmc --- - -[engines] -smtbmc boolector - -[script] -nofullskip: read -define NO_FULL_SKIP=1 -noverific: read -noverific -read -formal bridge_rx.v -prep -top bridge_rx - -[files] -src/manta/uart_iface/bridge_rx.v \ No newline at end of file diff --git a/test/functional_sim/block_memory_tb.sv b/test/functional_sim/block_memory_tb.sv deleted file mode 100644 index 818ca3b..0000000 --- a/test/functional_sim/block_memory_tb.sv +++ /dev/null @@ -1,182 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -`define BRAM_DEPTH 256 -`define BRAM_WIDTH 33 -`define ADDR_WIDTH $clog2(`BRAM_DEPTH) - -task read_reg_bus_side ( - input [15:0] addr, - output [15:0] data - ); - - block_memory_tb.tb_bc_addr = addr; - block_memory_tb.tb_bc_rw = 0; - block_memory_tb.tb_bc_valid = 1; - #`CP - block_memory_tb.tb_bc_rw = 0; - block_memory_tb.tb_bc_valid = 0; - while (!block_memory_tb.bc_tb_valid) #`CP; - data = block_memory_tb.bc_tb_data; - - $display(" -> bus read 0x%h from addr 0x%h", data, addr); -endtask - -task write_reg_bus_side( - input [15:0] addr, - input [15:0] data - ); - - block_memory_tb.tb_bc_addr = addr; - block_memory_tb.tb_bc_data = data; - block_memory_tb.tb_bc_rw = 1; - block_memory_tb.tb_bc_valid = 1; - #`CP - block_memory_tb.tb_bc_rw = 0; - block_memory_tb.tb_bc_valid = 0; - while (!block_memory_tb.bc_tb_valid) #`CP; - - $display(" -> bus wrote 0x%h to addr 0x%h", data, addr); -endtask - -task write_and_verify_bus_side( - input [15:0] addr, - input [15:0] write_data - ); - - reg [15:0] read_data; - - write_reg_bus_side(addr, write_data); - read_reg_bus_side(addr, read_data); - assert(read_data == write_data) else $fatal(0, "data read does not match data written!"); -endtask - -task read_user_side( - input [`ADDR_WIDTH-1:0] addr - ); - - block_memory_tb.bram_user_we = 0; - block_memory_tb.bram_user_addr = addr; - #(2*`CP); - $display("user read 0x%h from addr 0x%h", block_memory_tb.bram_user_dout, addr); -endtask - -task write_user_side( - input [`ADDR_WIDTH-1:0] addr, - input [`BRAM_WIDTH-1:0] data - ); - - block_memory_tb.bram_user_we = 1; - block_memory_tb.bram_user_addr = addr; - block_memory_tb.bram_user_din = data; - #(2*`CP); - $display("user wrote 0x%h to addr 0x%h", data, addr); -endtask - - -module block_memory_tb; - - // boilerplate - logic clk; - integer test_num; - reg [15:0] read_value; - - // tb -> bram_core bus - logic [15:0] tb_bc_addr; - logic [15:0] tb_bc_data; - logic tb_bc_rw; - logic tb_bc_valid; - - // bram_core -> tb bus - logic [15:0] bc_tb_addr; - logic [15:0] bc_tb_data; - logic bc_tb_rw; - logic bc_tb_valid; - - // bram itself - localparam BRAM_DEPTH = `BRAM_DEPTH; - localparam BRAM_WIDTH = `BRAM_WIDTH; - localparam ADDR_WIDTH = $clog2(BRAM_DEPTH); - logic [ADDR_WIDTH-1:0] bram_user_addr = 0; - logic [BRAM_WIDTH-1:0] bram_user_din = 0; - logic [BRAM_WIDTH-1:0] bram_user_dout; - logic bram_user_we = 0; - - block_memory #(.DEPTH(BRAM_DEPTH), .WIDTH(BRAM_WIDTH)) block_mem ( - .clk(clk), - - .addr_i(tb_bc_addr), - .data_i(tb_bc_data), - .rw_i(tb_bc_rw), - .valid_i(tb_bc_valid), - - .addr_o(bc_tb_addr), - .data_o(bc_tb_data), - .rw_o(bc_tb_rw), - .valid_o(bc_tb_valid), - - .user_clk(clk), - .user_addr(bram_user_addr), - .user_din(bram_user_din), - .user_dout(bram_user_dout), - .user_we(bram_user_we)); - - always begin - #`HCP - clk = !clk; - end - - initial begin - $dumpfile("block_memory_tb.vcd"); - $dumpvars(0, block_memory_tb); - - // setup and reset - clk = 0; - test_num = 0; - - tb_bc_addr = 0; - tb_bc_data = 0; - tb_bc_rw = 0; - tb_bc_valid = 0; - - bram_user_addr = 0; - bram_user_din = 0; - bram_user_we = 0; - - #`HCP - - - - #(10*`CP); - - /* ==== Test 1 Begin ==== */ - $display("\n=== test 1: read/write from BRAM, verify ==="); - test_num = 1; - write_and_verify_bus_side(0, 'h6789); - write_and_verify_bus_side(1, 'h2345); - write_and_verify_bus_side(2, 'h0001); - - // now query what's on the the user side at address 0 - read_user_side(0); - - write_and_verify_bus_side(3, 'h1111); - write_and_verify_bus_side(4, 'h1111); - write_and_verify_bus_side(5, 'h0001); - - // now query what's on the the user side at address 0 - read_user_side(1); - - write_user_side(1, 0); - read_user_side(1); - - #(10*`CP); - - /* ==== Test 1 End ==== */ - - $finish(); - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/bridge_rx_tb.sv b/test/functional_sim/bridge_rx_tb.sv deleted file mode 100644 index 78b4049..0000000 --- a/test/functional_sim/bridge_rx_tb.sv +++ /dev/null @@ -1,185 +0,0 @@ -`default_nettype none -// `timescale 1ns/1ps - -`define CP 10 -`define HCP 5 - -task test_good_read_msg ( - input string message, - input [15:0] addr - ); - - bridge_rx_tb.tb_brx_valid = 1; - for(int i=0; i < $size(message); i++) begin - bridge_rx_tb.tb_brx_data = message [i]; - if(bridge_rx_tb.brx_tb_valid) begin - assert(bridge_rx_tb.brx_tb_addr == addr) else $fatal(0, "wrong addr!"); - assert(bridge_rx_tb.brx_tb_rw == 0) else $fatal(0, "wrong rw!"); - assert(bridge_rx_tb.brx_tb_data == 0) else $fatal(0, "wrong data!"); - end - #`CP; - end - bridge_rx_tb.tb_brx_valid = 0; -endtask - -task test_good_write_msg ( - input string message, - input [15:0] addr, - input [15:0] data - ); - - bridge_rx_tb.tb_brx_valid = 1; - for(int i=0; i < $size(message); i++) begin - bridge_rx_tb.tb_brx_data = message[i]; - if(bridge_rx_tb.brx_tb_valid) begin - assert(bridge_rx_tb.brx_tb_addr == addr) else $fatal(0, "wrong addr!"); - assert(bridge_rx_tb.brx_tb_rw == 1) else $fatal(0, "wrong rw!"); - assert(bridge_rx_tb.brx_tb_data == data) else $fatal(0, "wrong data!"); - end - #`CP; - end - bridge_rx_tb.tb_brx_valid = 0; -endtask - -task test_bad_msg ( - input string message - ); - - bridge_rx_tb.tb_brx_valid = 1; - for(int i=0; i < $size(message); i++) begin - bridge_rx_tb.tb_brx_data = message[i]; - assert(bridge_rx_tb.brx_tb_valid == 0) else $fatal(0, "wrong valid!"); - #`CP; - end - bridge_rx_tb.tb_brx_valid = 0; -endtask - - -module bridge_rx_tb; -// https://www.youtube.com/watch?v=WCOAr-96bGc - -//boilerplate -logic clk; -integer test_num; - -// uart inputs and outputs -logic [7:0] tb_brx_data; -logic tb_brx_valid; - -logic [15:0] brx_tb_addr; -logic [15:0] brx_tb_data; -logic brx_tb_rw; -logic brx_tb_valid; - -bridge_rx bridge_rx_uut( - .clk(clk), - - .data_i(tb_brx_data), - .valid_i(tb_brx_valid), - - .addr_o(brx_tb_addr), - .data_o(brx_tb_data), - .rw_o(brx_tb_rw), - .valid_o(brx_tb_valid)); - -always begin - #`HCP - clk = !clk; -end - -initial begin - $dumpfile("bridge_rx.vcd"); - $dumpvars(0, bridge_rx_tb); - - // setup and reset - clk = 0; - tb_brx_data = 0; - tb_brx_valid = 0; - test_num = 0; - #`CP - #`HCP - - test_num = test_num + 1; - $display("\n=== test %2d: transmit W12345678(CR)(LF) for baseline functionality ===", test_num); - test_good_write_msg("W12345678\r\n", 16'h1234, 16'h5678); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit WDEADBEEF(CR)(LF) for proper state reset ===", test_num); - test_good_write_msg("WDEADBEEF\r\n", 16'hDEAD, 16'hBEEF); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit RBABE(CR)(LF) for baseline functionality ===", test_num); - test_good_read_msg("RBABE\r\n", 16'hBABE); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R0000(CR) for EOL insensitivity ===", test_num); - test_good_read_msg("R0000\r", 16'hBABE); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R1234(LF) for EOL insensitivity ===", test_num); - test_good_read_msg("R1234\n", 16'h1234); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit WF00DBEEF(CR) for EOL insensitivity ===", test_num); - test_good_write_msg("WF00DBEEF\r", 16'hF00D, 16'hBEEF); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit WB0BACAFE(LF) for EOL insensitivity ===", test_num); - test_good_write_msg("WB0BACAFE\r", 16'hB0BA, 16'hCAFE); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R1234(LF)R5678 for back-to-back messages ===", test_num); - test_good_read_msg("R1234\r\n", 16'h1234); - test_good_read_msg("R5678\r\n", 16'h5678); - #(10*`CP); - - $display("\n\nIntentionally bad messages:"); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit RABC(CR)(LF) for message length ===", test_num); - test_bad_msg("RABC\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R12345(CR)(LF) for message length ===", test_num); - test_bad_msg("R12345\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit M(CR)(LF) for message length ===", test_num); - test_bad_msg("WABC\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit W123456789101112131415161718191201222(CR)(LF) for message length ===", test_num); - test_bad_msg("W123456789101112131415161718191201222\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit RABCG(CR)(LF) for invalid characters ===", test_num); - test_bad_msg("RABCG\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit WABC[]()##*@(CR)(LF) for invalid characters and message length ===", test_num); - test_bad_msg("WABC[]()##*@\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R(CR)(LF) for message length ===", test_num); - test_bad_msg("R\r\n"); - #(10*`CP); - - $finish(); -end - - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/bridge_tx_tb.sv b/test/functional_sim/bridge_tx_tb.sv deleted file mode 100644 index b55e6d2..0000000 --- a/test/functional_sim/bridge_tx_tb.sv +++ /dev/null @@ -1,116 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -`define CP 10 -`define HCP 5 - -module bridge_tx_tb; -// https://www.youtube.com/watch?v=WCOAr-96bGc - -// boilerplate -logic clk; -integer test_num; - -// tb -> bridge_tx signals -logic [15:0] tb_btx_data; -logic tb_btx_valid; - -// uart_tx -> tb signals -logic utx_tb_tx; - -bridge_tx btx ( - .clk(clk), - - .data_i(tb_btx_data), - .rw_i(1'b0), - .valid_i(tb_btx_valid), - - .data_o(btx_utx_data), - .start_o(btx_utx_start), - .done_i(utx_btx_done)); - -reg [7:0] btx_utx_data; -reg btx_utx_start; -reg utx_btx_done; - -uart_tx #(.CLOCKS_PER_BAUD(10)) utx ( - .clk(clk), - - .data_i(btx_utx_data), - .start_i(btx_utx_start), - .done_o(utx_btx_done), - - .tx(utx_tb_tx)); - -always begin - #`HCP - clk = !clk; -end - -initial begin - $dumpfile("bridge_tx.vcd"); - $dumpvars(0, bridge_tx_tb); - - // setup and reset - clk = 0; - test_num = 0; - - tb_btx_valid = 0; - tb_btx_data = 0; - #(10*`CP); - - /* ==== Test 1 Begin ==== */ - $display("\n=== test 1: receive 0x0123 for baseline functionality ==="); - test_num = 1; - tb_btx_data = 16'h0123; - tb_btx_valid = 1; - - #`CP; - tb_btx_valid = 0; - - #(100000*`CP); - /* ==== Test 1 End ==== */ - - /* ==== Test 2 Begin ==== */ - $display("\n=== test 2: receive 0x4567 for baseline functionality ==="); - test_num = 2; - tb_btx_data = 16'h4567; - tb_btx_valid = 1; - - #`CP; - tb_btx_valid = 0; - - #(100000*`CP); - /* ==== Test 2 End ==== */ - - /* ==== Test 3 Begin ==== */ - $display("\n=== test 3: receive 0x89AB for baseline functionality ==="); - test_num = 3; - tb_btx_data = 16'h89AB; - tb_btx_valid = 1; - - #`CP; - tb_btx_valid = 0; - - #(100000*`CP); - /* ==== Test 3 End ==== */ - - /* ==== Test 4 Begin ==== */ - $display("\n=== test 4: receive 0xCDEF for baseline functionality ==="); - test_num = 4; - tb_btx_data = 16'hCDEF; - tb_btx_valid = 1; - - #`CP; - tb_btx_valid = 0; - - #(100000*`CP); - /* ==== Test 4 End ==== */ - - $finish(); -end - - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/ethernet_rx_tb.sv b/test/functional_sim/ethernet_rx_tb.sv deleted file mode 100644 index 89ee8d4..0000000 --- a/test/functional_sim/ethernet_rx_tb.sv +++ /dev/null @@ -1,98 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -`define FPGA_MAC 48'h69_69_5A_06_54_91 -`define HOST_MAC 48'h00_E0_4C_68_1E_0C -`define ETHERTYPE 16'h88_B5 - -module ethernet_rx_tb(); - - // https://www.youtube.com/watch?v=K35qOTQLNpA - logic clk; - - always begin - #5; - clk = !clk; - end - - logic crsdv; - logic [1:0] rxd; - - logic txen; - logic [1:0] txd; - - logic [39:0] mtx_payload; - logic mtx_start; - - mac_tx #( - .SRC_MAC(`HOST_MAC), - .DST_MAC(`FPGA_MAC), - .ETHERTYPE(`ETHERTYPE), - .PAYLOAD_LENGTH_BYTES(5) - ) mtx ( - .clk(clk), - - .payload(mtx_payload), - .start(mtx_start), - - .txen(txen), - .txd(txd)); - - assign rxd = txd; - assign crsdv = txen; - - logic [15:0] erx_addr; - logic [15:0] erx_data; - logic erx_rw; - logic erx_valid; - - ethernet_rx #( - .FPGA_MAC(`FPGA_MAC), - .ETHERTYPE(`ETHERTYPE) - ) erx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .addr_o(erx_addr), - .data_o(erx_data), - .rw_o(erx_rw), - .valid_o(erx_valid)); - - initial begin - $dumpfile("ethernet_rx_tb.vcd"); - $dumpvars(0, ethernet_rx_tb); - clk = 0; - mtx_payload = 0; - mtx_start = 0; - #50; - - // try to send a read request to the bus: - mtx_payload = 40'h01_0002_0001; - mtx_start = 1; - #10; - mtx_start = 0; - #10000; - - - - - // for (int i=0; i<32; i=i+1) begin - // mtx_payload = i; - // mtx_start = 0; - // #10; - // mtx_start = 1; - // #10; - // mtx_start = 0; - // while(!mrx_valid) #10; - - // #1000; - - // assert(mrx_payload == i) else $fatal(0, "data mismatch!"); - // end - $finish(); - end - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/ethernet_tx_tb.sv b/test/functional_sim/ethernet_tx_tb.sv deleted file mode 100644 index 0146753..0000000 --- a/test/functional_sim/ethernet_tx_tb.sv +++ /dev/null @@ -1,121 +0,0 @@ -`default_nettype none -//`timescale 1ns/1ps - -`define FPGA_MAC 48'h69_69_5A_06_54_91 -`define HOST_MAC 48'h00_E0_4C_68_1E_0C -`define ETHERTYPE 16'h88_B5 - -task send_on_etx_receive_on_mrx ( - input [15:0] data - ); - - ethernet_tx_tb.etx_data = data; - ethernet_tx_tb.etx_rw = 0; - ethernet_tx_tb.etx_valid = 0; - #10; - ethernet_tx_tb.etx_valid = 1; - #10; - ethernet_tx_tb.etx_valid = 0; - - while(!ethernet_tx_tb.mrx_valid) #10; - - $display(ethernet_tx_tb.mrx_payload); -endtask - -module ethernet_tx_tb(); - - // https://www.youtube.com/watch?v=K35qOTQLNpA - logic clk; - - always begin - #5; - clk = !clk; - end - - logic txen; - logic [1:0] txd; - - // ethernet tx - reg [15:0] etx_data; - reg etx_rw; - reg etx_valid; - - ethernet_tx #( - .FPGA_MAC(`FPGA_MAC), - .HOST_MAC(`HOST_MAC), - .ETHERTYPE(`ETHERTYPE) - ) etx ( - .clk(clk), - - .data_i(etx_data), - .rw_i(etx_rw), - .valid_i(etx_valid), - - .txen(txen), - .txd(txd)); - - // mac_rx, for decoding - logic crsdv; - logic [1:0] rxd; - - reg [55:0] mrx_payload; - reg mrx_valid; - - mac_rx #( - // this is the host mac since we're using mac_rx to impersonate - // the host computer, to which packets are currently addressed. - - .FPGA_MAC(`HOST_MAC), - .ETHERTYPE(`ETHERTYPE) - ) mrx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .payload(mrx_payload), - .valid(mrx_valid)); - - logic [15:0] where_ethertype_should_be; - logic [7:0] where_rw_should_be; - logic [15:0] where_addr_should_be; - logic [15:0] where_data_should_be; - assign {where_ethertype_should_be, where_rw_should_be, where_addr_should_be, where_data_should_be} = mrx_payload; - - assign rxd = txd; - assign crsdv = txen; - - initial begin - $dumpfile("ethernet_tx_tb.vcd"); - $dumpvars(0, ethernet_tx_tb); - clk = 0; - etx_data = 16'h6970; - etx_rw = 0; - etx_valid = 0; - #50; - - send_on_etx_receive_on_mrx(16'h6970); - - #10000; - - - - - // for (int i=0; i<32; i=i+1) begin - // mtx_payload = i; - // mtx_start = 0; - // #10; - // mtx_start = 1; - // #10; - // mtx_start = 0; - // while(!mrx_valid) #10; - - // #1000; - - // assert(mrx_payload == i) else $fatal(0, "data mismatch!"); - // end - $finish(); - end - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/io_core_tb/io_core.v b/test/functional_sim/io_core_tb/io_core.v deleted file mode 100644 index 8f8daa7..0000000 --- a/test/functional_sim/io_core_tb/io_core.v +++ /dev/null @@ -1,118 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module io_core( - input wire bus_clk, - input wire user_clk, - - // inputs - input wire probe0, - input wire [1:0] probe1, - input wire [7:0] probe2, - input wire [19:0] probe3, - - // outputs - output reg probe4, - output reg [1:0] probe5, - output reg [7:0] probe6, - output reg [19:0] probe7, - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o - ); - - parameter BASE_ADDR = 0; - - reg strobe = 0; - - // configure buffers - // inputs - reg probe0_buf = 0; - reg [1:0] probe1_buf = 0; - reg [7:0] probe2_buf = 0; - reg [19:0] probe3_buf = 0; - - // outputs - reg probe4_buf = 1; // PROBE4_INITIAL_VALUE; - reg [1:0] probe5_buf = 3; // PROBE5_INITIAL_VALUE; - reg [7:0] probe6_buf = 6; // PROBE6_INITIAL_VALUE; - reg [19:0] probe7_buf = 7; // PROBE7_INITIAL_VALUE; - - initial begin - probe4 = 1; // PROBE4_INITIAL_VALUE; - probe5 = 3; // PROBE5_INITIAL_VALUE; - probe6 = 6; // PROBE6_INITIAL_VALUE; - probe7 = 7; // PROBE7_INITIAL_VALUE; - end - - // synchronize buffers and probes on strobe - always @(posedge user_clk) begin - if(strobe) begin - // update input buffers from input probes - probe0_buf <= probe0; - probe1_buf <= probe1; - probe2_buf <= probe2; - probe3_buf <= probe3; - - // update output buffers from output probes - probe4 <= probe4_buf; - probe5 <= probe5_buf; - probe6 <= probe6_buf; - probe7 <= probe7_buf; - end - end - - - // handle bus operations - always @(posedge bus_clk) begin - addr_o <= addr_i; - data_o <= data_i; - rw_o <= rw_i; - valid_o <= valid_i; - - // check if address is valid - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + 10)) begin - - if(!rw_i) begin // reads - case (addr_i) - BASE_ADDR + 0: data_o <= strobe; - - BASE_ADDR + 1: data_o <= probe0_buf; // width 1 - BASE_ADDR + 2: data_o <= probe1_buf; // width 2 - BASE_ADDR + 3: data_o <= probe2_buf; // width 8 - BASE_ADDR + 4: data_o <= probe3_buf[15:0]; // width 20 - BASE_ADDR + 5: data_o <= probe3_buf[19:16]; - - BASE_ADDR + 6: data_o <= probe4_buf; // width 1 - BASE_ADDR + 7: data_o <= probe5_buf; // width 2 - BASE_ADDR + 8: data_o <= probe6_buf; // width 8 - BASE_ADDR + 9: data_o <= probe7_buf[15:0]; // width 20 - BASE_ADDR + 10: data_o <= probe7_buf[19:16]; - endcase - end - - else begin // writes - case (addr_i) - BASE_ADDR + 0: strobe <= data_i[0]; - - BASE_ADDR + 6: probe4_buf <= data_i[0]; - BASE_ADDR + 7: probe5_buf <= data_i[1:0]; - BASE_ADDR + 8: probe6_buf <= data_i[7:0]; - BASE_ADDR + 9: probe7_buf[15:0] <= data_i; - BASE_ADDR + 10: probe7_buf[19:16] <= data_i[3:0]; - endcase - end - end - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/io_core_tb/io_core_tb.sv b/test/functional_sim/io_core_tb/io_core_tb.sv deleted file mode 100644 index 3a1caef..0000000 --- a/test/functional_sim/io_core_tb/io_core_tb.sv +++ /dev/null @@ -1,277 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -task read_reg ( - input [15:0] addr, - output [15:0] data, - input string desc - ); - - io_core_tb.tb_io_addr = addr; - io_core_tb.tb_io_rw = 0; - io_core_tb.tb_io_valid = 1; - #`CP - io_core_tb.tb_io_valid = 0; - while (!io_core_tb.io_tb_valid) #`CP; - data = io_core_tb.io_tb_data; - - $display(" -> read 0x%h from addr 0x%h (%s)", data, addr, desc); -endtask - -task write_reg( - input [15:0] addr, - input [15:0] data, - input string desc - ); - - io_core_tb.tb_io_addr = addr; - io_core_tb.tb_io_data = data; - io_core_tb.tb_io_rw = 1; - io_core_tb.tb_io_valid = 1; - #`CP - io_core_tb.tb_io_valid = 0; - while (!io_core_tb.io_tb_valid) #`CP; - - $display(" -> wrote 0x%h to addr 0x%h (%s)", data, addr, desc); -endtask - -task write_and_verify( - input [15:0] addr, - input [15:0] write_data, - input string desc - ); - - reg [15:0] read_data; - - write_reg(addr, write_data, desc); - read_reg(addr, read_data, desc); - assert(read_data == write_data) else $fatal(0, "data read does not match data written!"); -endtask - -// task read_all_reg(); -// string desc; -// for(int i = 0; i < (io_core_tb.la.block_mem.MAX_ADDR); i++) begin - -// if(i == io_core_tb.la.fsm_registers.BASE_ADDR) desc = "FSM"; -// if(i == io_core_tb.la.trig_blk.BASE_ADDR) desc = "TRIG BLK"; -// if(i == io_core_tb.la.block_mem.BASE_ADDR) desc = "SAMPLE MEM"; - -// read_reg(i, io_core_tb.read_value, desc); -// end -// endtask - -module io_core_tb; - - // boilerplate - logic clk; - integer test_num; - - // inputs - logic probe0; - logic [1:0] probe1; - logic [7:0] probe2; - logic [19:0] probe3; - - // outputs - logic probe4; - logic [1:0] probe5; - logic [7:0] probe6; - logic [19:0] probe7; - - // tb -> io bus - logic [15:0] tb_io_addr; - logic [15:0] tb_io_data; - logic tb_io_rw; - logic tb_io_valid; - - // la -> io bus - logic [15:0] io_tb_addr; - logic [15:0] io_tb_data; - logic io_tb_rw; - logic io_tb_valid; - - - io_core #(.BASE_ADDR(0)) io( - .bus_clk(clk), - .user_clk(clk), - - // inputs - .probe0(probe0), - .probe1(probe1), - .probe2(probe2), - .probe3(probe3), - - // outputs - .probe4(probe4), - .probe5(probe5), - .probe6(probe6), - .probe7(probe7), - - // input port - .addr_i(tb_io_addr), - .data_i(tb_io_data), - .rw_i(tb_io_rw), - .valid_i(tb_io_valid), - - // output port - .addr_o(io_tb_addr), - .data_o(io_tb_data), - .rw_o(io_tb_rw), - .valid_o(io_tb_valid)); - - always begin - #`HCP - clk = !clk; - end - - logic [15:0] read_data; - - initial begin - $dumpfile("io_core_tb.vcd"); - $dumpvars(0, io_core_tb); - - // setup and reset - clk = 0; - test_num = 0; - - tb_io_addr = 0; - tb_io_data = 0; - tb_io_rw = 0; - tb_io_valid = 0; - - probe0 = 0; - probe1 = 1; - probe2 = 2; - probe3 = 3; - - // #`HCP - #(10*`CP); - - /* ==== Test 1 Begin ==== */ - $display("\n=== test 1: read initial register states ==="); - test_num = 1; - read_reg(0, read_data, "strobe"); - read_reg(1, read_data, "probe0"); - read_reg(2, read_data, "probe1"); - read_reg(3, read_data, "probe2"); - read_reg(4, read_data, "probe3[15:0]"); - read_reg(5, read_data, "probe3[19:16]"); - - read_reg(6, read_data, "probe4"); - read_reg(7, read_data, "probe5"); - read_reg(8, read_data, "probe6"); - read_reg(9, read_data, "probe7[15:0]"); - read_reg(10, read_data, "probe7[19:16]"); - #(10*`CP); - /* ==== Test 1 End ==== */ - - /* ==== Test 2 Begin ==== */ - $display("\n=== test 2: assert input buffers initialized correctly ==="); - test_num = 2; - read_reg(0, read_data, "strobe"); - assert(read_data == 0) else $fatal(0, "strobe does not initialize to zero!"); - assert(io.strobe == 0) else $fatal(0, "strobe does not initialize to zero!"); - - read_reg(1, read_data, "probe0"); - assert(read_data == 0) else $fatal(0, "probe0_buf does not initialize to zero!"); - assert(io.probe0_buf == 0) else $fatal(0, "probe0_buf does not initialize to zero!"); - - read_reg(2, read_data, "probe1"); - assert(read_data == 0) else $fatal(0, "probe1_buf does not initialize to zero!"); - assert(io.probe1_buf == 0) else $fatal(0, "probe1_buf does not initialize to zero!"); - - read_reg(3, read_data, "probe2"); - assert(read_data == 0) else $fatal(0, "probe2_buf does not initialize to zero!"); - assert(io.probe2_buf == 0) else $fatal(0, "probe2_buf does not initialize to zero!"); - - read_reg(4, read_data, "probe3[15:0]"); - assert(read_data == 0) else $fatal(0, "probe3_buf does not initialize to zero!"); - read_reg(5, read_data, "probe3[19:16]"); - assert(read_data == 0) else $fatal(0, "probe3_buf does not initialize to zero!"); - assert(io.probe3_buf == 0) else $fatal(0, "probe3_buf does not initialize to zero!"); - - #(10*`CP); - /* ==== Test 2 End ==== */ - - - /* ==== Test 3 Begin ==== */ - $display("\n=== test 3: assert outputs and output buffers initialized correctly ==="); - test_num = 3; - read_reg(6, read_data, "probe4"); - assert(read_data == 1) else $fatal(0, "probe4 does not initialize correctly!"); - assert(io.probe4_buf == 1) else $fatal(0, "probe4_buf does not initialize correctly!"); - assert(io.probe4 == 1) else $fatal(0, "probe4 does not initialize correctly!"); - - read_reg(7, read_data, "probe5"); - assert(read_data == 3) else $fatal(0, "probe5 does not initialize correctly!"); - assert(io.probe5_buf == 3) else $fatal(0, "probe5_buf does not initialize correctly!"); - assert(io.probe5 == 3) else $fatal(0, "probe5 does not initialize correctly!"); - - read_reg(8, read_data, "probe6"); - assert(read_data == 6) else $fatal(0, "probe6 does not initialize correctly!"); - assert(io.probe6_buf == 6) else $fatal(0, "probe6_buf does not initialize correctly!"); - assert(io.probe6 == 6) else $fatal(0, "probe6 does not initialize correctly!"); - - read_reg(9, read_data, "probe7[15:0]"); - assert(read_data == 7) else $fatal(0, "probe7 does not initialize correctly!"); - read_reg(10, read_data, "probe7[19:16]"); - assert(read_data == 0) else $fatal(0, "probe7 does not initialize correctly!"); - assert(io.probe7_buf == 7) else $fatal(0, "probe7_buf does not initialize correctly!"); - assert(io.probe7 == 7) else $fatal(0, "probe7 does not initialize correctly!"); - - - #(10*`CP); - /* ==== Test 3 End ==== */ - - /* ==== Test 4 Begin ==== */ - $display("\n=== test 4: write new output value to each output probe==="); - test_num = 4; - write_reg(6, 0, "probe4"); - assert(io.probe4_buf == 0) else $fatal(0, "probe4_buf does not update correctly!"); - assert(io.probe4 != 0) else $fatal(0, "probe4 updated without strobing!"); - - write_reg(7, 0, "probe5"); - assert(io.probe5_buf == 0) else $fatal(0, "probe5_buf does not update correctly!"); - assert(io.probe5 != 0) else $fatal(0, "probe5 updated without strobing!"); - - write_reg(8, 0, "probe6"); - assert(io.probe6_buf == 0) else $fatal(0, "probe6_buf does not update correctly!"); - assert(io.probe6 != 0) else $fatal(0, "probe6 updated without strobing!"); - - write_reg(9, 0, "probe7[15:0]"); - write_reg(10, 0, "probe7[19:16]"); - assert(io.probe7_buf == 0) else $fatal(0, "probe7_buf does not update correctly!"); - assert(io.probe7 != 0) else $fatal(0, "probe7 updated without strobing!"); - #(10*`CP); - /* ==== Test 4 End ==== */ - - /* ==== Test 5 Begin ==== */ - $display("\n=== test 5: strobe core, check that inputs and outputs updated ==="); - test_num = 5; - - write_reg(0, 1, "strobe"); - write_reg(0, 0, "strobe"); - - assert(io.probe4 == 0) else $fatal(0, "probe4 did not update correctly!"); - assert(io.probe5 == 0) else $fatal(0, "probe5 did not update correctly!"); - assert(io.probe6 == 0) else $fatal(0, "probe6 did not update correctly!"); - assert(io.probe7 == 0) else $fatal(0, "probe7 did not update correctly!"); - - assert(io.probe0_buf == 0) else $fatal(0, "probe0_buf did not update correctly!"); - assert(io.probe1_buf == 1) else $fatal(0, "probe1_buf did not update correctly!"); - assert(io.probe2_buf == 2) else $fatal(0, "probe2_buf did not update correctly!"); - assert(io.probe3_buf == 3) else $fatal(0, "probe3_buf did not update correctly!"); - assert(io.probe4_buf == 0) else $fatal(0, "probe4_buf did not update correctly!"); - assert(io.probe5_buf == 0) else $fatal(0, "probe5_buf did not update correctly!"); - assert(io.probe6_buf == 0) else $fatal(0, "probe6_buf did not update correctly!"); - assert(io.probe7_buf == 0) else $fatal(0, "probe7_buf did not update correctly!"); - /* ==== Test 5 End ==== */ - - - $finish(); - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv deleted file mode 100644 index 36288de..0000000 --- a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv +++ /dev/null @@ -1,257 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -task read_reg ( - input [15:0] addr, - output [15:0] data, - input string desc - ); - - logic_analyzer_tb.tb_la_addr = addr; - logic_analyzer_tb.tb_la_rw = 0; - logic_analyzer_tb.tb_la_valid = 1; - #`CP - logic_analyzer_tb.tb_la_valid = 0; - while (!logic_analyzer_tb.la_tb_valid) #`CP; - data = logic_analyzer_tb.la_tb_data; - - $display(" -> read 0x%h from addr 0x%h (%s)", data, addr, desc); -endtask - -task write_reg( - input [15:0] addr, - input [15:0] data, - input string desc - ); - - logic_analyzer_tb.tb_la_addr = addr; - logic_analyzer_tb.tb_la_data = data; - logic_analyzer_tb.tb_la_rw = 1; - logic_analyzer_tb.tb_la_valid = 1; - #`CP - logic_analyzer_tb.tb_la_valid = 0; - while (!logic_analyzer_tb.la_tb_valid) #`CP; - - $display(" -> wrote 0x%h to addr 0x%h (%s)", data, addr, desc); -endtask - -task write_and_verify( - input [15:0] addr, - input [15:0] write_data, - input string desc - ); - - reg [15:0] read_data; - - write_reg(addr, write_data, desc); - read_reg(addr, read_data, desc); - assert(read_data == write_data) else $fatal(0, "data read does not match data written!"); -endtask - -task read_all_reg(); - string desc; - for(int i = 0; i < (logic_analyzer_tb.la.block_mem.MAX_ADDR); i++) begin - - if(i == logic_analyzer_tb.la.fsm_registers.BASE_ADDR) desc = "FSM"; - if(i == logic_analyzer_tb.la.trig_blk.BASE_ADDR) desc = "TRIG BLK"; - if(i == logic_analyzer_tb.la.block_mem.BASE_ADDR) desc = "SAMPLE MEM"; - - read_reg(i, logic_analyzer_tb.read_value, desc); - end -endtask - -module logic_analyzer_tb; - - // boilerplate - logic clk; - integer test_num; - - // signal generator - logic larry; - logic curly; - logic moe; - logic [3:0] shemp; - - // tb -> la bus - logic [15:0] tb_la_addr; - logic [15:0] tb_la_data; - logic tb_la_rw; - logic tb_la_valid; - - // la -> tb bus - logic [15:0] la_tb_addr; - logic [15:0] la_tb_data; - logic la_tb_rw; - logic la_tb_valid; - - - logic_analyzer la( - .clk(clk), - - // probes - .larry(larry), - .curly(curly), - .moe(moe), - .shemp(shemp), - - // input port - .addr_i(tb_la_addr), - .data_i(tb_la_data), - .rw_i(tb_la_rw), - .valid_i(tb_la_valid), - - // output port - .addr_o(la_tb_addr), - .data_o(la_tb_data), - .rw_o(la_tb_rw), - .valid_o(la_tb_valid)); - - always begin - #`HCP - clk = !clk; - end - - reg [15:0] read_value; - - initial begin - $dumpfile("logic_analyzer_tb.vcd"); - $dumpvars(0, logic_analyzer_tb); - - // setup and reset - clk = 0; - test_num = 0; - - tb_la_addr = 0; - tb_la_data = 0; - tb_la_rw = 0; - tb_la_valid = 0; - - larry = 0; - curly = 0; - moe = 0; - shemp = 0; - #`HCP - #(10*`CP); - - - // /* ==== Test 2 Begin ==== */ - // $display("\n=== test 2: read/write to trigger block registers, verify ==="); - // test_num = 2; - - // // larry - // write_and_verify(3, 0, "larry_op"); - // write_and_verify(3, 2, "larry_op"); - // write_and_verify(3, 0, "larry_op"); - - // write_and_verify(4, 0, "larry_arg"); - // write_and_verify(4, 1, "larry_arg"); - // write_and_verify(4, 0, "larry_arg"); - - // // curly - // write_and_verify(5, 0, "curly_op"); - // write_and_verify(5, 3, "curly_op"); - // write_and_verify(5, 0, "curly_op"); - - // write_and_verify(6, 0, "curly_arg"); - // write_and_verify(6, 1, "curly_arg"); - // write_and_verify(6, 0, "curly_arg"); - - // // moe - // write_and_verify(7, 0, "moe_op"); - // write_and_verify(7, 5, "moe_op"); - // write_and_verify(7, 0, "moe_op"); - - // write_and_verify(8, 0, "moe_arg"); - // write_and_verify(8, 1, "moe_arg"); - // write_and_verify(8, 0, "moe_arg"); - - // // shemp - // write_and_verify(9, 0, "shemp_op"); - // write_and_verify(9, 7, "shemp_op"); - // write_and_verify(9, 0, "shemp_op"); - - // write_and_verify(10, 0, "shemp_arg"); - // write_and_verify(10, 7, "shemp_arg"); - // write_and_verify(10, 0, "shemp_arg"); - - // #(10*`CP); - - // /* ==== Test 2 End ==== */ - - - /* ==== Test 4 Begin ==== */ - $display("\n=== test 4: verify FSM does move out of IDLE when running ==="); - test_num = 4; - - $display(" -> setting up trigger (larry == 1)"); - write_reg(la.trig_blk.BASE_ADDR + 0, 8, "larry_op"); - write_reg(la.trig_blk.BASE_ADDR + 1, 1, "larry_arg"); - - $display(" -> requesting start"); - write_reg(3, 1, "request_start"); - write_reg(3, 0, "request_start"); - #`CP - - $display(" -> set larry = 1"); - larry = 1; - - // read - $display(" -> la core is in state 0x%h", la.fsm_registers.state); - $display(" -> wait a clock cycle"); - #`CP - $display(" -> la core is in state 0x%h", la.fsm_registers.state); - - // run until the FILLED state is reached - $display(" -> wait until FILLED state is reached"); - while (la.fsm_registers.state != la.la_controller.CAPTURED) begin - {larry, curly, moe, shemp} = {larry, curly, moe, shemp} + 1; - #`CP; - end - - $display(" -> read from sample memory:"); - read_all_reg(); - - #(200*`CP); - /* ==== Test 4 End ==== */ - - // /* ==== Test 5 Begin ==== */ - // $display("\n=== test 5: change trigger to fire on shemp > 3, and verify ==="); - // test_num = 5; - - // write_and_verify(9, 6, "shemp_op"); // set operation to GT - // write_and_verify(10, 3, "shemp_arg"); // set argument to 3 - - // assert( (la.fsm_registers.state == la.la_controller.IDLE) || (la.fsm_registers.state == la.la_controller.CAPTURED) ) - // else $fatal(0, "core is running when it shouldn't be!"); - - // larry = 0; - // curly = 0; - // moe = 0; - // shemp = 0; - - // // start the core - // // TODO: start the core - - // shemp = 4; - // $display(" -> set shemp = 4"); - - // // run until the FILLED state is reached - // $display(" -> wait until FILLED state is reached"); - // while (la.fsm_registers.state != la.la_controller.CAPTURED) begin - // {larry, curly, moe, shemp} = {larry, curly, moe, shemp} + 2; - // #`CP; - // end - - // $display(" -> read from sample memory:"); - // read_all_reg(); - - // #(10*`CP); - // /* ==== Test 5 End ==== */ - - $finish(); - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/logic_analyzer_tb/manta.yaml b/test/functional_sim/logic_analyzer_tb/manta.yaml deleted file mode 100644 index cbd04c1..0000000 --- a/test/functional_sim/logic_analyzer_tb/manta.yaml +++ /dev/null @@ -1,19 +0,0 @@ ---- -cores: - logic_analyzer: - type: logic_analyzer - sample_depth: 128 - - probes: - larry: 1 - curly: 1 - moe: 1 - shemp: 4 - - triggers: - - larry && curly && ~moe - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/functional_sim/mac_tb.sv b/test/functional_sim/mac_tb.sv deleted file mode 100644 index c812fc2..0000000 --- a/test/functional_sim/mac_tb.sv +++ /dev/null @@ -1,86 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -`define FPGA_MAC 48'h69_69_5A_06_54_91 -`define HOST_MAC 48'h00_E0_4C_68_1E_0C -`define ETHERTYPE 16'h88_B5 - - -module mac_tb(); - logic clk; - - always begin - #5; - clk = !clk; - end - - logic crsdv; - logic [1:0] rxd; - - logic txen; - logic [1:0] txd; - - // this testbench makes sure that our rx pipeline is good, - // so we'll have mtx simulate the host machine and blast - // 5 bytes (plus padding) onto our fake RMII - logic [39:0] mtx_payload; - logic mtx_start; - - logic [39:0] mrx_payload; - logic mrx_valid; - - mac_tx #( - .SRC_MAC(`HOST_MAC), - .DST_MAC(`FPGA_MAC), - .ETHERTYPE(`ETHERTYPE), - .PAYLOAD_LENGTH_BYTES(5) - ) mtx ( - .clk(clk), - - .payload(mtx_payload), - .start(mtx_start), - - .txen(txen), - .txd(txd)); - - assign rxd = txd; - assign crsdv = txen; - - mac_rx #( - .FPGA_MAC(`FPGA_MAC), - .ETHERTYPE(`ETHERTYPE) - ) mrx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .payload(mrx_payload), - .valid(mrx_valid)); - - initial begin - $dumpfile("mac_tb.vcd"); - $dumpvars(0, mac_tb); - clk = 0; - mtx_payload = 0; - mtx_start = 0; - #10; - - for (int i=0; i<32; i=i+1) begin - mtx_payload = i; - mtx_start = 0; - #10; - mtx_start = 1; - #10; - mtx_start = 0; - while(!mrx_valid) #10; - - #1000; - - assert(mrx_payload == i) else $fatal(0, "data mismatch!"); - end - $finish(); - end - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/uart_rx_tb.sv b/test/functional_sim/uart_rx_tb.sv deleted file mode 100644 index 9993eb3..0000000 --- a/test/functional_sim/uart_rx_tb.sv +++ /dev/null @@ -1,94 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -task automatic test_receive ( - input [7:0] data, - input integer CLOCKS_PER_BAUD - ); - - // send a byte to uart_rx, and check that it receives properly - - integer data_bit = 0; - logic valid_has_been_asserted = 0; - - for(int i=0; i < (10*CLOCKS_PER_BAUD); i++) begin - - // clock out data bits on each baud period - data_bit = i / CLOCKS_PER_BAUD; - if (data_bit == 0) uart_rx_tb.tb_urx_rx = 0; - else if ((data_bit > 0) && (data_bit < 9)) uart_rx_tb.tb_urx_rx = data[data_bit-1]; - else uart_rx_tb.tb_urx_rx = 1; - - - // every cycle, run checks on uart_rx: - - // make sure valid isn't asserted before end of byte - if (data_bit < 9) begin - assert(uart_rx_tb.urx_tb_valid == 0) else $fatal(0, "valid asserted before end of byte!"); - end - - // make sure valid is only asserted once - if (valid_has_been_asserted) begin - assert(uart_rx_tb.urx_tb_valid == 0) else $fatal(0, "valid asserted more than once!"); - end - - // make sure byte is presented once last bit has been clocked out - if (uart_rx_tb.urx_tb_valid) begin - assert(data_bit == 9) else $fatal(0, "byte presented before it is complete"); - assert(uart_rx_tb.urx_tb_data == data) else $fatal(0, "wrong data!"); - valid_has_been_asserted = 1; - end - - #`CP; - end - - // make sure valid was asserted at some point - assert (valid_has_been_asserted) else $fatal(0, "valid not asserted!"); -endtask - -module uart_rx_tb(); - logic clk; - integer test_num; - - logic tb_urx_rx; - logic [7:0] urx_tb_data; - logic urx_tb_valid; - uart_rx #(.CLOCKS_PER_BAUD(10)) urx ( - .clk(clk), - .rx(tb_urx_rx), - .data_o(urx_tb_data), - .valid_o(urx_tb_valid)); - - always begin - #`HCP - clk = !clk; - end - - initial begin - $dumpfile("uart_rx_tb.vcd"); - $dumpvars(0, uart_rx_tb); - clk = 0; - test_num = 0; - tb_urx_rx = 1; - #`HCP; - - // test all possible bytes - test_num = test_num + 1; - for(int i=0; i < 256; i++) begin - test_receive(i, 10); - #(100*`CP); - end - - // test all possible bytes (no delay between them) - test_num = test_num + 1; - for(int i=0; i < 256; i++) begin - test_receive(i, 10); - end - - $finish(); - end -endmodule - -`default_nettype wire diff --git a/test/functional_sim/uart_tx_tb.sv b/test/functional_sim/uart_tx_tb.sv deleted file mode 100644 index 308069e..0000000 --- a/test/functional_sim/uart_tx_tb.sv +++ /dev/null @@ -1,99 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -task automatic transmit_byte ( - input [7:0] data, - input integer CLOCKS_PER_BAUD - ); - - // send a byte from uart_tx, and check that it transmits properly - - integer data_bit = 0; - for(int i=0; i < (10*CLOCKS_PER_BAUD)-1; i++) begin - - // check that data bit is correct on every baud period - data_bit = i / CLOCKS_PER_BAUD; - if (data_bit == 0) begin - assert(uart_tx_tb.utx_tb_tx == 0) else $fatal(0, "wrong start bit!"); - end - - else if ((data_bit > 0) && (data_bit < 9)) begin - assert(uart_tx_tb.utx_tb_tx == data[data_bit-1]) else $fatal(0, "wrong data bit!"); - end - - else begin - assert(uart_tx_tb.utx_tb_tx == 1) else $fatal(0, "wrong stop bit!"); - end - - - // check that done is not asserted during transmisison - assert(!uart_tx_tb.utx_tb_done) else $fatal(0, "wrong done!"); - #`CP; - end - - // assert that done is asserted at end of transmission - assert(uart_tx_tb.utx_tb_done) else $fatal(0, "wrong done!"); -endtask - -module uart_tx_tb(); - logic clk; - integer test_num; - - logic [7:0] tb_utx_data; - logic tb_utx_start; - logic utx_tb_done; - logic utx_tb_tx; - - uart_tx #(.CLOCKS_PER_BAUD(10)) utx ( - .clk(clk), - - .data_i(tb_utx_data), - .start_i(tb_utx_start), - .done_o(utx_tb_done), - - .tx(utx_tb_tx)); - - always begin - #`HCP - clk = !clk; - end - - initial begin - $dumpfile("uart_tx_tb.vcd"); - $dumpvars(0, uart_tx_tb); - clk = 0; - test_num = 0; - - tb_utx_data = 0; - tb_utx_start = 0; - #`HCP; - - // test all possible bytes - test_num = test_num + 1; - for(int i=0; i < 256; i++) begin - tb_utx_start = 1; - tb_utx_data = i; - #`CP; - tb_utx_start = 0; - tb_utx_data = 0; - transmit_byte(i, 10); - #(100*`CP); - end - - // test all possible bytes (no delay between them) - test_num = test_num + 1; - for(int i=0; i < 256; i++) begin - tb_utx_start = 1; - tb_utx_data = i; - #`CP; - tb_utx_data = 0; - transmit_byte(i, 10); - end - - $finish(); - end -endmodule - -`default_nettype wire diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py new file mode 100644 index 0000000..89c3d4d --- /dev/null +++ b/test/test_bridge_rx_sim.py @@ -0,0 +1,120 @@ +from amaranth.sim import Simulator +from manta.uart import RecieveBridge +from manta.utils import * + + +bridge_rx = RecieveBridge() + + +def verify_read_decoding(bytes, addr): + """ + Send a series of bytes to the receive bridge, and verify that the bridge places + a read request with the appropriate address on the internal bus. + """ + valid_asserted = False + yield bridge_rx.valid_i.eq(1) + + for i, byte in enumerate(bytes): + yield bridge_rx.data_i.eq(byte) + + if (yield bridge_rx.valid_o) and (i > 0): + valid_asserted = True + if (yield bridge_rx.addr_o) != addr: + raise ValueError("wrong addr!") + + if (yield bridge_rx.rw_o) != 0: + raise ValueError("wrong rw!") + + if (yield bridge_rx.data_o) != 0: + raise ValueError("wrong data!") + + yield + + yield bridge_rx.valid_i.eq(0) + yield bridge_rx.data_i.eq(0) + + if not valid_asserted and not (yield bridge_rx.valid_o): + raise ValueError("Bridge failed to output valid message.") + + +def verify_write_decoding(bytes, addr, data): + """ + Send a series of bytes to the receive bridge, and verify that the bridge places + a write request with the appropriate address and data on the internal bus. + """ + valid_asserted = False + yield bridge_rx.valid_i.eq(1) + + for i, byte in enumerate(bytes): + yield bridge_rx.data_i.eq(byte) + + if (yield bridge_rx.valid_o) and (i > 0): + valid_asserted = True + if (yield bridge_rx.addr_o) != addr: + raise ValueError("wrong addr!") + + if (yield bridge_rx.rw_o) != 1: + raise ValueError("wrong rw!") + + if (yield bridge_rx.data_o) != data: + raise ValueError("wrong data!") + + yield + + yield bridge_rx.valid_i.eq(0) + yield bridge_rx.data_i.eq(0) + + if not valid_asserted and not (yield bridge_rx.valid_o): + raise ValueError("Bridge failed to output valid message.") + + +def verify_bad_bytes(bytes): + """ + Send a series of bytes to the receive bridge, and verify that the bridge does not + place any transaction on the internal bus. + """ + yield bridge_rx.valid_i.eq(1) + + for byte in bytes: + yield bridge_rx.data_i.eq(byte) + + if (yield bridge_rx.valid_o): + raise ValueError("Bridge decoded invalid message.") + + yield + + yield bridge_rx.valid_i.eq(0) + + +def test_read_decode(): + def testbench(): + yield from verify_read_decoding(b"R0000\r\n", 0x0000) + yield from verify_read_decoding(b"R1234\r\n", 0x1234) + yield from verify_read_decoding(b"RBABE\r\n", 0xBABE) + yield from verify_read_decoding(b"R5678\n", 0x5678) + yield from verify_read_decoding(b"R9ABC\r", 0x9ABC) + + simulate(bridge_rx, testbench) + + +def test_write_decode(): + def testbench(): + yield from verify_write_decoding(b"W12345678\r\n", 0x1234, 0x5678) + yield from verify_write_decoding(b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF) + yield from verify_write_decoding(b"WDEADBEEF\r", 0xDEAD, 0xBEEF) + yield from verify_write_decoding(b"WB0BACAFE\n", 0xB0BA, 0xCAFE) + + simulate(bridge_rx, testbench) + + +def test_no_decode(): + def testbench(): + yield from verify_bad_bytes(b"RABC\r\n") + yield from verify_bad_bytes(b"R12345\r\n") + yield from verify_bad_bytes(b"M\r\n") + yield from verify_bad_bytes(b"W123456789101112131415161718191201222\r\n") + yield from verify_bad_bytes(b"RABCG\r\n") + yield from verify_bad_bytes(b"WABC[]()##*@\r\n") + yield from verify_bad_bytes(b"R\r\n") + + simulate(bridge_rx, testbench) diff --git a/test/test_bridge_tx_sim.py b/test/test_bridge_tx_sim.py new file mode 100644 index 0000000..9a1568d --- /dev/null +++ b/test/test_bridge_tx_sim.py @@ -0,0 +1,67 @@ +from amaranth.sim import Simulator +from manta.uart import TransmitBridge +from manta.utils import * +from random import randint, sample + + +bridge_tx = TransmitBridge() + + +def verify_encoding(data, bytes): + """ + Place a read response on the internal bus, and verify that the sequence of bytes + sent from TransmitBridge matches the provided bytestring `bytes`. + + This function also models an ideal UARTTransmitter module, which begins transmitting + bytes when `start` is asserted, and reports when it is done by asserting `done`. + """ + + # Place a read response on the internal bus + yield bridge_tx.data_i.eq(data) + yield bridge_tx.valid_i.eq(1) + yield bridge_tx.rw_i.eq(0) + yield bridge_tx.done_i.eq(1) + + yield + + yield bridge_tx.data_i.eq(0) + yield bridge_tx.valid_i.eq(0) + yield bridge_tx.rw_i.eq(0) + + yield + + # Model the UARTTransmitter + sent_bytes = b"" + iters = 0 + + while len(sent_bytes) < len(bytes): + # If start_o is asserted, set done_i to zero, then delay, then set it back to one + if (yield bridge_tx.start_o): + yield bridge_tx.done_i.eq(0) + sent_bytes += (yield bridge_tx.data_o).to_bytes(1, "big") + + yield bridge_tx.done_i.eq(0) + for _ in range(10): + yield + + yield bridge_tx.done_i.eq(1) + yield + + # Time out if not enough bytes after trying to get bytes 15 times + iters += 1 + if iters > 15: + raise ValueError("Timed out waiting for bytes.") + + # Verify bytes sent from ReceiveBridge match expected_bytes + if sent_bytes != bytes: + raise ValueError(f"Received {sent_bytes} instead of {bytes}.") + + +def test_some_random_values(): + def testbench(): + for i in sample(range(0xFFFF), k=5000): + expected = f"D{i:04X}\r\n".encode("ascii") + print(i) + yield from verify_encoding(i, expected) + + simulate(bridge_tx, testbench) diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py new file mode 100644 index 0000000..25f0b2c --- /dev/null +++ b/test/test_io_core_hw.py @@ -0,0 +1,129 @@ +from amaranth import * +from amaranth_boards.nexys4ddr import Nexys4DDRPlatform +from amaranth_boards.icestick import ICEStickPlatform +from manta import Manta +from manta.utils import * +import pytest +from random import randint + + +class IOCoreLoopbackTest(Elaboratable): + def __init__(self, platform, port): + self.platform = platform + self.port = port + + self.config = self.platform_specific_config() + self.m = Manta(self.config) + + def platform_specific_config(self): + return { + "cores": { + "io_core": { + "type": "io", + "inputs": {"probe0": 1, "probe1": 2, "probe2": 8, "probe3": 20}, + "outputs": { + "probe4": {"width": 1, "initial_value": 1}, + "probe5": { + "width": 2, + "initial_value": 2, + }, + "probe6": 8, + "probe7": {"width": 20, "initial_value": 65538}, + }, + } + }, + "uart": { + "port": self.port, + "baudrate": 3e6, + "clock_freq": self.platform.default_clk_frequency, + }, + } + + def elaborate(self, platform): + m = Module() + m.submodules["manta"] = self.m + + uart_pins = platform.request("uart") + + m.d.comb += [ + self.m.io_core.probe0.eq(self.m.io_core.probe4), + self.m.io_core.probe1.eq(self.m.io_core.probe5), + self.m.io_core.probe2.eq(self.m.io_core.probe6), + self.m.io_core.probe3.eq(self.m.io_core.probe7), + self.m.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.m.interface.tx), + ] + + return m + + def build_and_program(self): + self.platform.build(self, do_program=True) + + def verify_output_probe_initial_values(self): + """ + Test that all output probes take their expected initial values. + We can't really test for the same of input probes, since the + strobe register pulses every time the get_probe() method is called. + """ + + # Test that all output probes take their initial values + inputs = self.config["cores"]["io_core"]["inputs"] + outputs = self.config["cores"]["io_core"]["outputs"] + + for name, attrs in outputs.items(): + actual = self.m.io_core.get_probe(name) + + if isinstance(attrs, dict): + if "initial_value" in attrs: + expected = attrs["initial_value"] + + else: + expected = 0 + + if actual != expected: + raise ValueError( + f"Output probe {name} took initial value of {actual} instead of {expected}." + ) + + def verify_probes_update(self): + """ + This design ties all the output probes to input probes, so this + test sets the outputs to random values, and verifies the inputs match + """ + inputs = self.config["cores"]["io_core"]["inputs"] + outputs = self.config["cores"]["io_core"]["outputs"] + + # The config is specified in such a way that the first output is + # connected to the first output, the second output is connected + # to the second input, and so on... + for input, output in zip(inputs, outputs): + width = self.config["cores"]["io_core"]["inputs"][input] + value = randint(0, 2**width - 1) + + self.m.io_core.set_probe(output, value) + readback = self.m.io_core.get_probe(input) + + if readback != value: + raise ValueError( + f"Reading {output} through {input} yielded {readback} instead of {value}!" + ) + + else: + print( + f"Reading {output} through {input} yielded {readback} as expected." + ) + + def verify(self): + self.build_and_program() + self.verify_output_probe_initial_values() + self.verify_probes_update() + + +@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") +def test_output_probe_initial_values_xilinx(): + IOCoreLoopbackTest(Nexys4DDRPlatform(), "/dev/ttyUSB2").verify() + + +@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") +def test_output_probe_initial_values_ice40(): + IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB1").verify() diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py new file mode 100644 index 0000000..5ef1405 --- /dev/null +++ b/test/test_io_core_sim.py @@ -0,0 +1,155 @@ +from amaranth.sim import Simulator +from manta.io_core import IOCore +from manta.utils import * +from random import randint + +config = { + "type": "io", + "inputs": {"probe0": 1, "probe1": 2, "probe2": 8, "probe3": 20}, + "outputs": { + "probe4": {"width": 1, "initial_value": 1}, + "probe5": {"width": 2, "initial_value": 2}, + "probe6": 8, + "probe7": {"width": 20, "initial_value": 65538}, + }, +} + +io_core = IOCore(config, base_addr=0, interface=None) + + +def pulse_strobe_register(): + strobe_addr = io_core.mmap["strobe"]["addrs"][0] + yield from write_register(io_core, strobe_addr, 0) + yield from write_register(io_core, strobe_addr, 1) + yield from write_register(io_core, strobe_addr, 0) + + +def test_output_probe_initial_values(): + def testbench(): + # Verify all output probes initialize to the values in the config + for name, attrs in config["outputs"].items(): + initial_value = 0 + if isinstance(attrs, dict): + if "initial_value" in attrs: + initial_value = attrs["initial_value"] + + output_probe = getattr(io_core, name) + value = yield output_probe + + if value != initial_value: + raise ValueError( + f"Output probe {name} initialized to {value} instead of {initial_value}" + ) + + else: + print(f"Output probe {name} initialized to {value} as expected.") + + simulate(io_core, testbench) + + +def test_input_probe_buffer_initial_value(): + def testbench(): + # Verify all input probe buffers initialize to zero + for name, width in config["inputs"].items(): + addrs = io_core.mmap[name + "_buf"]["addrs"] + + for addr in addrs: + yield from verify_register(io_core, addr, 0) + + simulate(io_core, testbench) + + +def test_output_probe_buffer_initial_value(): + def testbench(): + # Verify all output probe buffers initialize to the values in the config + for name, attrs in config["outputs"].items(): + addrs = io_core.mmap[name + "_buf"]["addrs"] + + datas = [0] * len(addrs) + if isinstance(attrs, dict): + if "initial_value" in attrs: + datas = value_to_words(attrs["initial_value"], len(addrs)) + + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) + + simulate(io_core, testbench) + + +def test_output_probes_are_writeable(): + def testbench(): + for name, attrs in config["outputs"].items(): + if isinstance(attrs, dict): + width = attrs["width"] + else: + width = attrs + + addrs = io_core.mmap[name + "_buf"]["addrs"] + test_value = randint(0, (2**width) - 1) + datas = value_to_words(test_value, len(addrs)) + + # write value to registers + for addr, data in zip(addrs, datas): + yield from write_register(io_core, addr, data) + + # read value back from registers + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) + + simulate(io_core, testbench) + + +def test_output_probes_update(): + def testbench(): + for name, attrs in config["outputs"].items(): + if isinstance(attrs, dict): + width = attrs["width"] + else: + width = attrs + + addrs = io_core.mmap[name + "_buf"]["addrs"] + test_value = randint(0, (2**width) - 1) + datas = value_to_words(test_value, len(addrs)) + + # write value to registers + for addr, data in zip(addrs, datas): + yield from write_register(io_core, addr, data) + + # pulse strobe register + yield from pulse_strobe_register() + + # check that outputs took updated value + output_probe = getattr(io_core, name) + value = yield (output_probe) + + if value != test_value: + raise ValueError( + f"Output probe {name} took value {value} instead of {test_value} after pulsing strobe." + ) + + else: + print(f"Output probe {name} took value {value} after pulsing strobe.") + + simulate(io_core, testbench) + + +def test_input_probes_update(): + def testbench(): + for name, width in config["inputs"].items(): + test_value = randint(0, (2**width) - 1) + + # set input probe value + input_probe = getattr(io_core, name) + yield input_probe.eq(test_value) + + # pulse strobe register + yield from pulse_strobe_register() + + # check that values are as expected once read back + addrs = io_core.mmap[name + "_buf"]["addrs"] + datas = value_to_words(test_value, len(addrs)) + + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) + + simulate(io_core, testbench) diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py new file mode 100644 index 0000000..1b6b063 --- /dev/null +++ b/test/test_logic_analyzer_hw.py @@ -0,0 +1,84 @@ +from amaranth import * +from amaranth_boards.nexys4ddr import Nexys4DDRPlatform +from amaranth_boards.icestick import ICEStickPlatform +from manta import Manta +from manta.utils import * +import pytest + + +class LogicAnalyzerCounterTest(Elaboratable): + def __init__(self, platform, port): + self.platform = platform + self.port = port + + self.config = self.platform_specific_config() + self.m = Manta(self.config) + + def platform_specific_config(self): + return { + "cores": { + "la": { + "type": "logic_analyzer", + "sample_depth": 1024, + "trigger_loc": 500, + "probes": {"larry": 1, "curly": 3, "moe": 9}, + "triggers": ["moe RISING"], + }, + }, + "uart": { + "port": self.port, + "baudrate": 3e6, + "clock_freq": self.platform.default_clk_frequency, + }, + } + + def elaborate(self, platform): + m = Module() + m.submodules["manta"] = self.m + uart_pins = platform.request("uart") + + larry = self.m.la.probe_signals["larry"]["top_level"] + curly = self.m.la.probe_signals["curly"]["top_level"] + moe = self.m.la.probe_signals["moe"]["top_level"] + + m.d.sync += larry.eq(larry + 1) + m.d.sync += curly.eq(curly + 1) + m.d.sync += moe.eq(moe + 1) + + m.d.comb += [ + self.m.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.m.interface.tx), + ] + + return m + + def build_and_program(self): + self.platform.build(self, do_program=True) + + def verify(self): + self.build_and_program() + cap = self.m.la.capture() + + # check that VCD export works + cap.export_vcd("out.vcd") + + # check that Verilog export works + cap.export_playback_verilog("out.v") + + # verify that each signal is just a counter modulo the width of the signal + for name, width in self.m.la.config["probes"].items(): + trace = cap.get_trace(name) + + for i in range(len(trace) - 1): + if trace[i + 1] != (trace[i] + 1) % (2**width): + raise ValueError("Bad counter!") + + +@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") +def test_mem_core_xilinx(): + LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB2").verify() + + +@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") +def test_mem_core_ice40(): + LogicAnalyzerCounterTest(ICEStickPlatform(), "/dev/ttyUSB1").verify() diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py new file mode 100644 index 0000000..b35e682 --- /dev/null +++ b/test/test_logic_analyzer_sim.py @@ -0,0 +1,140 @@ +from amaranth.sim import Simulator +from manta.logic_analyzer_core import LogicAnalyzerCore +from manta.utils import * +from random import sample + +config = { + "type": "logic_analyzer", + "sample_depth": 1024, + "trigger_loc": 500, + "probes": {"larry": 1, "curly": 3, "moe": 9}, + "triggers": ["moe RISING"], +} + +# class SimulatedBusInterface(): +# def __init__(self, core): +# self.core = core + +# def write(self, addrs, datas): +# # Handle a single integer address and data +# if isinstance(addrs, int) and isinstance(datas, int): +# return self.write([addrs], [datas]) + +# # Make sure address and datas are all integers +# if not isinstance(addrs, list) or not isinstance(datas, list): +# raise ValueError( +# "Write addresses and data must be an integer or list of integers." +# ) + +# if not all(isinstance(a, int) for a in addrs): +# raise ValueError("Write addresses must be all be integers.") + +# if not all(isinstance(d, int) for d in datas): +# raise ValueError("Write data must all be integers.") + +# # I'm not sure if it's necessary to split outputs into chunks +# # I think the output buffer doesn't really drop stuff, just the input buffer + +# for addr, data in zip(addrs, datas): +# yield from write_register(self.core, addr, data) + +# def read(self, addrs): +# # Handle a single integer address +# if isinstance(addrs, int): +# return self.read([addrs])[0] + +# # Make sure all list elements are integers +# if not all(isinstance(a, int) for a in addrs): +# raise ValueError("Read address must be an integer or list of integers.") + +# datas = [] +# for addr in addrs: +# yield la.addr_i.eq(addr) +# yield la.data_i.eq(0) +# yield la.rw_i.eq(0) +# yield la.valid_i.eq(1) +# yield +# yield la.addr_i.eq(0) +# yield la.valid_i.eq(0) + +# # wait for output to be valid +# while not (yield la.valid_o): +# yield + +# datas.append( (yield la.data_o) ) + +# return datas + +la = LogicAnalyzerCore(config, base_addr=0, interface=None) +# interface = SimulatedBusInterface(la) +# la.registers.interface = interface # unironically the least cursed part of this +# la.sample_mem.interface = interface # unironically the least cursed part of this + + +def print_data_at_addr(addr): + # place read transaction on the bus + yield la.addr_i.eq(addr) + yield la.data_i.eq(0) + yield la.rw_i.eq(0) + yield la.valid_i.eq(1) + yield + yield la.addr_i.eq(0) + yield la.valid_i.eq(0) + + # wait for output to be valid + while not (yield la.valid_o): + yield + + print(f"addr: {hex(addr)} data: {hex((yield la.data_o))}") + + +def set_logic_analyzer_register(name, data): + addr = la.registers.mmap[f"{name}_buf"]["addrs"][0] + + yield from write_register(la, 0, 0) + yield from write_register(la, addr, data) + yield from write_register(la, 0, 1) + yield from write_register(la, 0, 0) + + +def test_do_you_fucking_work(): + def testbench(): + # # ok nice what happens if we try to run the core, which includes: + yield from set_logic_analyzer_register("request_stop", 1) + yield from set_logic_analyzer_register("request_stop", 0) + + # setting triggers + yield from set_logic_analyzer_register("curly_op", la.operations["EQ"]) + yield from set_logic_analyzer_register("curly_arg", 4) + + # setting trigger mode + yield from set_logic_analyzer_register( + "trigger_mode", 0 + ) # right now this is not actually respected...oops + + # setting trigger location + yield from set_logic_analyzer_register("trigger_loc", 500) + + # starting capture + yield from set_logic_analyzer_register("request_start", 1) + yield from set_logic_analyzer_register("request_start", 0) + + # wait a few hundred clock cycles, see what happens + for _ in range(700): + yield + + # provide the trigger condition + yield la.probe_signals["curly"]["top_level"].eq(4) + + for _ in range(700): + yield + + # dump sample memory contents + yield from write_register(la, 0, 0) + yield from write_register(la, 0, 1) + yield from write_register(la, 0, 0) + + for addr in range(la.get_max_addr()): + yield from print_data_at_addr(addr) + + simulate(la, testbench, "la_core.vcd") diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py new file mode 100644 index 0000000..cb3c1de --- /dev/null +++ b/test/test_mem_core_hw.py @@ -0,0 +1,114 @@ +from amaranth import * +from amaranth_boards.nexys4ddr import Nexys4DDRPlatform +from amaranth_boards.icestick import ICEStickPlatform +from manta import Manta +from manta.utils import * +import pytest +from random import randint, sample +from math import ceil, log2 + +""" +Fundamentally we want a function to generate a configuration (as a dictionary) +for a memory core given the width, depth, and platform. This could be a random +configuration, or a standard one. +""" + + +class MemoryCoreLoopbackTest(Elaboratable): + def __init__(self, platform, width, depth, port): + self.platform = platform + self.width = width + self.depth = depth + self.port = port + + self.config = self.platform_specific_config() + self.m = Manta(self.config) + + def platform_specific_config(self): + return { + "cores": { + "mem_core": { + "type": "memory_read_only", + "width": self.width, + "depth": self.depth, + }, + "io_core": { + "type": "io", + "outputs": { + "addr": ceil(log2(self.depth)), + "data": self.width, + "we": 1, + }, + }, + }, + "uart": { + "port": self.port, + "baudrate": 3e6, + "clock_freq": self.platform.default_clk_frequency, + }, + } + + def elaborate(self, platform): + m = Module() + m.submodules["manta"] = self.m + + uart_pins = platform.request("uart") + + m.d.comb += [ + self.m.mem_core.user_addr.eq(self.m.io_core.addr), + self.m.mem_core.user_data.eq(self.m.io_core.data), + self.m.mem_core.user_we.eq(self.m.io_core.we), + self.m.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.m.interface.tx), + ] + + return m + + def build_and_program(self): + self.platform.build(self, do_program=True) + + def write_user_side(self, addr, data): + self.m.io_core.set_probe("we", 0) + self.m.io_core.set_probe("addr", addr) + self.m.io_core.set_probe("data", data) + self.m.io_core.set_probe("we", 1) + self.m.io_core.set_probe("we", 0) + + def verify_register(self, addr, expected_data): + data = self.m.mem_core.read_from_user_addr(addr) + + if data != expected_data: + raise ValueError( + f"Memory read from {hex(addr)} returned {hex(data)} instead of {hex(expected_data)}." + ) + + def verify(self): + self.build_and_program() + + # Read and write randomly from the bus side + for addr in sample(range(self.depth), k=self.depth): + data = randint(0, 2**self.width - 1) + self.write_user_side(addr, data) + self.verify_register(addr, data) + + +@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") +def test_mem_core_xilinx(): + MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, "/dev/ttyUSB2").verify() + + +@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") +def test_mem_core_ice40(): + port = "/dev/ttyUSB1" + MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 2, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 2, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 14, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 14, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 16, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 16, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 33, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 33, 1024, port).verify() diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py new file mode 100644 index 0000000..675991f --- /dev/null +++ b/test/test_mem_core_sim.py @@ -0,0 +1,45 @@ +from manta.memory_core import ReadOnlyMemoryCore +from manta.utils import * +from random import randint, sample + + +def fill_mem_from_user_port(mem_core, depth): + for i in range(depth): + yield mem_core.user_addr.eq(i) + yield mem_core.user_data.eq(i) + yield mem_core.user_we.eq(1) + yield + + yield mem_core.user_we.eq(0) + yield + + +def verify_mem_core(width, depth, base_addr): + config = {"type": "memory", "width": width, "depth": depth} + mem_core = ReadOnlyMemoryCore(config, base_addr, interface=None) + + def testbench(): + yield from fill_mem_from_user_port(mem_core, depth) + + # Read from address sequentially + for i in range(depth): + yield from verify_register(mem_core, i + base_addr, i % (2**width)) + + # Read from addresses randomly + for i in sample(range(depth), k=depth): + yield from verify_register(mem_core, i + base_addr, i % (2**width)) + + simulate(mem_core, testbench) + + +def test_sweep_core_widths(): + for i in range(1, 64): + verify_mem_core(i, 128, 0) + + +def test_random_cores(): + for _ in range(5): + width = randint(0, 512) + depth = randint(0, 1024) + base_addr = randint(0, 2**16 - 1 - depth) + verify_mem_core(width, depth, base_addr) diff --git a/test/test_toolchains.py b/test/test_toolchains.py new file mode 100644 index 0000000..c21c26a --- /dev/null +++ b/test/test_toolchains.py @@ -0,0 +1,15 @@ +from amaranth_boards.test.blinky import * +from amaranth_boards.nexys4ddr import Nexys4DDRPlatform +from amaranth_boards.icestick import ICEStickPlatform +from manta.utils import * +import pytest + + +@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") +def test_arty_a7_tools(): + Nexys4DDRPlatform().build(Blinky(), do_program=False) + + +@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") +def test_ice40_tools(): + ICEStickPlatform().build(Blinky(), do_program=False) diff --git a/test/test_uart_rx_sim.py b/test/test_uart_rx_sim.py new file mode 100644 index 0000000..3604591 --- /dev/null +++ b/test/test_uart_rx_sim.py @@ -0,0 +1,65 @@ +from amaranth.sim import Simulator +from manta.uart import UARTReceiver +from manta.utils import * +from random import sample + + +uart_rx = UARTReceiver(clocks_per_baud=10) + + +def verify_receive(data): + # 8N1 serial, LSB sent first + data_bits = "0" + f"{data:08b}"[::-1] + "1" + data_bits = [int(bit) for bit in data_bits] + + valid_asserted_before = False + + for i in range(10 * uart_rx.clocks_per_baud): + bit_index = i // uart_rx.clocks_per_baud + + # Every cycle, run checks on uart_rx: + if (yield uart_rx.valid_o): + if (yield uart_rx.data_o) != data: + a = yield uart_rx.data_o + print(data_bits) + raise ValueError( + f"Incorrect byte presented - gave {hex(a)} instead of {hex(data)}!" + ) + + if bit_index != 9: + print(bit_index) + raise ValueError("Byte presented before it is complete!") + + if not valid_asserted_before: + valid_asserted_before = True + + else: + raise ValueError("Valid asserted more than once!") + + yield uart_rx.rx.eq(data_bits[bit_index]) + yield + + if not valid_asserted_before: + raise ValueError("Failed to assert valid!") + + +def test_all_possible_bytes(): + def testbench(): + yield uart_rx.rx.eq(1) + yield + + for i in range(0xFF): + yield from verify_receive(i) + + simulate(uart_rx, testbench) + + +def test_bytes_random_sample(): + def testbench(): + yield uart_rx.rx.eq(1) + yield + + for i in sample(range(0xFF), k=0xFF): + yield from verify_receive(i) + + simulate(uart_rx, testbench) diff --git a/test/test_uart_tx_sim.py b/test/test_uart_tx_sim.py new file mode 100644 index 0000000..c78d076 --- /dev/null +++ b/test/test_uart_tx_sim.py @@ -0,0 +1,57 @@ +from amaranth.sim import Simulator +from manta.uart import UARTTransmitter +from manta.utils import * +from random import sample + + +uart_tx = UARTTransmitter(clocks_per_baud=10) + + +def verify_bit_sequence(byte): + """ + Request a byte to be transmitted, and verify that the sequence of bits is correct. + """ + + # Request byte to be transmitted + yield uart_tx.data_i.eq(byte) + yield uart_tx.start_i.eq(1) + yield + yield uart_tx.data_i.eq(0) + yield uart_tx.start_i.eq(0) + yield + + # Check that data bit is correct on every clock baud period + + # 8N1 serial, LSB sent first + data_bits = "0" + f"{byte:08b}"[::-1] + "1" + data_bits = [int(bit) for bit in data_bits] + + for i in range(10 * uart_tx.clocks_per_baud): + bit_index = i // uart_tx.clocks_per_baud + + if (yield uart_tx.tx) != data_bits[bit_index]: + raise ValueError("Wrong bit in sequence!") + + if (yield uart_tx.done_o) and (bit_index != 9): + raise ValueError("Done asserted too early!") + + yield + + if not (yield uart_tx.done_o): + raise ValueError("Done not asserted at end of transmission!") + + +def test_all_possible_bytes(): + def testbench(): + for i in range(0xFF): + yield from verify_bit_sequence(i) + + simulate(uart_tx, testbench) + + +def test_bytes_random_sample(): + def testbench(): + for i in sample(range(0xFF), k=0xFF): + yield from verify_bit_sequence(i) + + simulate(uart_tx, testbench) diff --git a/test/test_verilog_gen.py b/test/test_verilog_gen.py new file mode 100644 index 0000000..65bed93 --- /dev/null +++ b/test/test_verilog_gen.py @@ -0,0 +1,14 @@ +from manta.cli import gen +from manta import Manta +import tempfile +import os + + +def test_verilog_gen(): + with tempfile.TemporaryDirectory() as tmp_dir: + print("Created temporary directory at", tmp_dir) + + gen("test/test_verilog_gen.yaml", tmp_dir + "/manta.v") + + if not os.path.isfile(tmp_dir + "/manta.v"): + raise ValueError("No Verilog file generated!") diff --git a/test/functional_sim/io_core_tb/manta.yaml b/test/test_verilog_gen.yaml similarity index 53% rename from test/functional_sim/io_core_tb/manta.yaml rename to test/test_verilog_gen.yaml index 975a96b..09feddc 100644 --- a/test/functional_sim/io_core_tb/manta.yaml +++ b/test/test_verilog_gen.yaml @@ -2,7 +2,6 @@ cores: io_core: type: io - user_clock: True inputs: probe0: 1 @@ -14,11 +13,15 @@ cores: probe4: width: 1 initial_value: 1 - probe5: 2 + probe5: + width: 2 + initial_value: 2 probe6: 8 - probe7: 20 + probe7: + width: 20 + initial_value: 65538 uart: - port: "auto" - baudrate: 3000000 - clock_freq: 100000000 + port: "/dev/ttyUSB1" + baudrate: 115200 + clock_freq: 12000000