From b87f8cbc48b26455b3e297ddc3778ce5edb30ce0 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 14 Jul 2024 22:57:30 -0700 Subject: [PATCH] meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx --- test/test_bridge_rx_sim.py | 1 - test/test_bridge_tx_sim.py | 3 +-- test/test_io_core_hw.py | 3 +-- test/test_io_core_sim.py | 1 - test/test_logic_analyzer_fsm_sim.py | 1 - test/test_logic_analyzer_hw.py | 10 +++++++--- test/test_mem_core_hw.py | 11 +++++++---- test/test_uart_rx_sim.py | 2 -- test/test_uart_tx_sim.py | 2 -- test/test_verilog_gen.py | 1 - 10 files changed, 16 insertions(+), 19 deletions(-) diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py index d0a5edb..bf08791 100644 --- a/test/test_bridge_rx_sim.py +++ b/test/test_bridge_rx_sim.py @@ -1,4 +1,3 @@ -from amaranth.sim import Simulator from manta.uart import ReceiveBridge from manta.utils import * diff --git a/test/test_bridge_tx_sim.py b/test/test_bridge_tx_sim.py index 75987b9..029389f 100644 --- a/test/test_bridge_tx_sim.py +++ b/test/test_bridge_tx_sim.py @@ -1,7 +1,6 @@ -from amaranth.sim import Simulator from manta.uart import TransmitBridge from manta.utils import * -from random import randint, sample +from random import sample bridge_tx = TransmitBridge() diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 9e05aaa..64e071d 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -1,8 +1,7 @@ -from amaranth import * +from manta import Manta from amaranth.lib import io from amaranth_boards.nexys4ddr import Nexys4DDRPlatform from amaranth_boards.icestick import ICEStickPlatform -from manta import Manta from manta.utils import * import pytest from random import getrandbits diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py index a26b1ee..92125b6 100644 --- a/test/test_io_core_sim.py +++ b/test/test_io_core_sim.py @@ -1,5 +1,4 @@ from amaranth import * -from amaranth.sim import Simulator from manta.io_core import IOCore from manta.utils import * from random import getrandbits diff --git a/test/test_logic_analyzer_fsm_sim.py b/test/test_logic_analyzer_fsm_sim.py index a91cb98..e6e2a84 100644 --- a/test/test_logic_analyzer_fsm_sim.py +++ b/test/test_logic_analyzer_fsm_sim.py @@ -1,4 +1,3 @@ -from amaranth.sim import Simulator from manta.logic_analyzer import * from manta.utils import * diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index e199db6..739812d 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -1,4 +1,5 @@ from amaranth import * +from amaranth.lib import io from amaranth_boards.nexys4ddr import Nexys4DDRPlatform from amaranth_boards.icestick import ICEStickPlatform from manta import Manta @@ -35,7 +36,10 @@ class LogicAnalyzerCounterTest(Elaboratable): def elaborate(self, platform): m = Module() m.submodules.manta = self.manta - uart_pins = platform.request("uart") + + uart_pins = platform.request("uart", dir={"tx": "-", "rx": "-"}) + m.submodules.uart_rx = uart_rx = io.Buffer("i", uart_pins.rx) + m.submodules.uart_tx = uart_tx = io.Buffer("o", uart_pins.tx) larry = self.manta.la._probes[0] curly = self.manta.la._probes[1] @@ -46,8 +50,8 @@ class LogicAnalyzerCounterTest(Elaboratable): m.d.sync += moe.eq(moe + 1) m.d.comb += [ - self.manta.interface.rx.eq(uart_pins.rx.i), - uart_pins.tx.o.eq(self.manta.interface.tx), + self.manta.interface.rx.eq(uart_rx.i), + uart_tx.o.eq(self.manta.interface.tx), ] return m diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index fb8f853..a4cf34b 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -1,4 +1,5 @@ from amaranth import * +from amaranth.lib import io from amaranth_boards.nexys4ddr import Nexys4DDRPlatform from amaranth_boards.icestick import ICEStickPlatform from manta import Manta @@ -65,15 +66,17 @@ class MemoryCoreLoopbackTest(Elaboratable): m = Module() m.submodules.manta = self.manta - uart_pins = platform.request("uart") + uart_pins = platform.request("uart", dir={"tx": "-", "rx": "-"}) + m.submodules.uart_rx = uart_rx = io.Buffer("i", uart_pins.rx) + m.submodules.uart_tx = uart_tx = io.Buffer("o", uart_pins.tx) user_addr = self.get_probe("user_addr") user_data_in = self.get_probe("user_data_in") user_data_out = self.get_probe("user_data_out") user_write_enable = self.get_probe("user_write_enable") - m.d.comb += self.manta.interface.rx.eq(uart_pins.rx.i) - m.d.comb += uart_pins.tx.o.eq(self.manta.interface.tx) + m.d.comb += self.manta.interface.rx.eq(uart_rx.i) + m.d.comb += uart_tx.o.eq(self.manta.interface.tx) m.d.comb += self.manta.mem_core.user_addr.eq(user_addr) if self.mode in ["bidirectional", "fpga_to_host"]: @@ -136,7 +139,7 @@ class MemoryCoreLoopbackTest(Elaboratable): # Omit the bidirectional mode for now, pending completion of: # https://github.com/amaranth-lang/amaranth/issues/1011 -modes = ["fpga_to_host", "host_to_fpga"] +modes = ["fpga_to_host", "host_to_fpga", "bidirectional"] widths = [1, 8, 14, 16, 33] depths = [2, 512, 1024] nexys4ddr_cases = [(m, w, d) for m in modes for w in widths for d in depths] diff --git a/test/test_uart_rx_sim.py b/test/test_uart_rx_sim.py index 620f240..b2c7c9b 100644 --- a/test/test_uart_rx_sim.py +++ b/test/test_uart_rx_sim.py @@ -1,7 +1,5 @@ -from amaranth.sim import Simulator from manta.uart import UARTReceiver from manta.utils import * -from random import sample uart_rx = UARTReceiver(clocks_per_baud=10) diff --git a/test/test_uart_tx_sim.py b/test/test_uart_tx_sim.py index a30374a..088df2d 100644 --- a/test/test_uart_tx_sim.py +++ b/test/test_uart_tx_sim.py @@ -1,7 +1,5 @@ -from amaranth.sim import Simulator from manta.uart import UARTTransmitter from manta.utils import * -from random import sample uart_tx = UARTTransmitter(clocks_per_baud=10) diff --git a/test/test_verilog_gen.py b/test/test_verilog_gen.py index 65bed93..e4ac074 100644 --- a/test/test_verilog_gen.py +++ b/test/test_verilog_gen.py @@ -1,5 +1,4 @@ from manta.cli import gen -from manta import Manta import tempfile import os