From b11f07857acb69ce7c6f1e1afbc7eae64a197393 Mon Sep 17 00:00:00 2001 From: Fischer Moseley Date: Thu, 9 Feb 2023 15:12:07 -0500 Subject: [PATCH] blacken code --- manta.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/manta.py b/manta.py index 1363e4c..b23751c 100644 --- a/manta.py +++ b/manta.py @@ -284,10 +284,10 @@ def make_widths(config): s = sum(widths) slices = [] for width in widths: - slices.append( (s-1, s-width) ) + slices.append((s - 1, s - width)) s = s - width - - assert s == 0, 'Probe sizes are weird, cannot slice bits properly' + + assert s == 0, "Probe sizes are weird, cannot slice bits properly" return slices @@ -298,7 +298,7 @@ def export_waveform(config, data, path): from vcd import VCDWriter vcd_file = open(path, "w") - + # Use the datetime format that iVerilog uses timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y")