From a2d14116de0e082ece98adbc8654ecbdb8156de1 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Tue, 18 Apr 2023 23:14:41 -0400 Subject: [PATCH] add trigger_mode register to logic analyzer core --- src/manta/__init__.py | 42 +++++++++++++++++++----- src/manta/logic_analyzer_controller.v | 4 +-- src/manta/logic_analyzer_def_tmpl.v | 3 ++ src/manta/logic_analyzer_fsm_registers.v | 20 ++++++----- 4 files changed, 49 insertions(+), 20 deletions(-) diff --git a/src/manta/__init__.py b/src/manta/__init__.py index 34c3b33..6486345 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -487,6 +487,25 @@ class LogicAnalyzerCore: assert config["trigger_loc"] <= self.sample_depth, "Trigger location cannot exceed sample depth." self.trigger_loc = config["trigger_loc"] + # Add trigger mode + self.SINGLE_SHOT = 0 + self.INCREMENTAL = 1 + self.IMMEDIATE = 2 + + self.trigger_mode = self.SINGLE_SHOT + if "trigger_mode" in config: + assert config["trigger_mode"] in ["single_shot", "incremental", "immediate"], \ + "Unrecognized trigger mode provided." + + if config["trigger_mode"] == "single_shot": + self.trigger_mode = self.SINGLE_SHOT + + elif config["trigger_mode"] == "incremental": + self.trigger_mode = self.INCREMENTAL + + elif config["trigger_mode"] == "immediate": + self.trigger_mode = self.IMMEDIATE + # compute base addresses self.fsm_base_addr = self.base_addr self.trigger_block_base_addr = self.fsm_base_addr + 6 @@ -499,11 +518,12 @@ class LogicAnalyzerCore: # build out self register map: # these are also defined in logic_analyzer_fsm_registers.v, and should match self.state_reg_addr = self.base_addr - self.trigger_loc_reg_addr = self.base_addr + 1 - self.request_start_reg_addr = self.base_addr + 2 - self.request_stop_reg_addr = self.base_addr + 3 - self.read_pointer_reg_addr = self.base_addr + 4 - self.write_pointer_reg_addr = self.base_addr + 5 + self.trigger_mode_reg_addr = self.base_addr + 1 + self.trigger_loc_reg_addr = self.base_addr + 2 + self.request_start_reg_addr = self.base_addr + 3 + self.request_stop_reg_addr = self.base_addr + 4 + self.read_pointer_reg_addr = self.base_addr + 5 + self.write_pointer_reg_addr = self.base_addr + 6 self.IDLE = 0 self.MOVE_TO_POSITION = 1 @@ -647,7 +667,7 @@ class LogicAnalyzerCore: return ports #return VerilogManipulator().net_dec(self.probes, "input wire") - def configure_trigger_conditions(self): + def set_trigger_conditions(self): operations = { "DISABLE" : 0, @@ -710,10 +730,14 @@ class LogicAnalyzerCore: assert state == self.IDLE, "Logic analyzer did not reset to correct state when requested to." # Configure trigger conditions - print(" -> Configuring trigger conditions...") - self.configure_trigger_conditions() + print(" -> Set trigger conditions...") + self.set_trigger_conditions() - # Configure the trigger_loc, but we'll skip that for now + # Configure the trigger_mode + print(" -> Setting trigger mode") + self.interface.write_register(self.trigger_mode_reg_addr, self.trigger_mode) + + # Configure the trigger_loc print(" -> Setting trigger location...") self.interface.write_register(self.trigger_loc_reg_addr, self.trigger_loc) diff --git a/src/manta/logic_analyzer_controller.v b/src/manta/logic_analyzer_controller.v index 0c5f4b3..8b2224e 100644 --- a/src/manta/logic_analyzer_controller.v +++ b/src/manta/logic_analyzer_controller.v @@ -7,6 +7,7 @@ module logic_analyzer_controller ( // from register file output reg [3:0] state, input wire [15:0] trigger_loc, + input wire [1:0] trigger_mode, input wire request_start, input wire request_stop, output reg [ADDR_WIDTH-1:0] read_pointer, @@ -54,9 +55,6 @@ module logic_analyzer_controller ( bram_we <= 0; if(request_start && ~prev_request_start) begin - // TODO: figure out what determines whether or not we - // go into MOVE_TO_POSITION or IN_POSITION. that's for - // the morning state <= MOVE_TO_POSITION; end end diff --git a/src/manta/logic_analyzer_def_tmpl.v b/src/manta/logic_analyzer_def_tmpl.v index 9f0ff52..3d6b1c4 100644 --- a/src/manta/logic_analyzer_def_tmpl.v +++ b/src/manta/logic_analyzer_def_tmpl.v @@ -26,6 +26,7 @@ module logic_analyzer ( reg [3:0] state; reg [15:0] trigger_loc; + reg [1:0] trigger_mode; reg request_start; reg request_stop; reg [ADDR_WIDTH-1:0] read_pointer; @@ -46,6 +47,7 @@ module logic_analyzer ( // from register file .state(state), .trigger_loc(trigger_loc), + .trigger_mode(trigger_mode), .request_start(request_start), .request_stop(request_stop), .read_pointer(read_pointer), @@ -79,6 +81,7 @@ module logic_analyzer ( .state(state), .trigger_loc(trigger_loc), + .trigger_mode(trigger_mode), .request_start(request_start), .request_stop(request_stop), .read_pointer(read_pointer), diff --git a/src/manta/logic_analyzer_fsm_registers.v b/src/manta/logic_analyzer_fsm_registers.v index ccb9f1c..9efa6d4 100644 --- a/src/manta/logic_analyzer_fsm_registers.v +++ b/src/manta/logic_analyzer_fsm_registers.v @@ -21,6 +21,7 @@ module logic_analyzer_fsm_registers( // registers input wire [3:0] state, output reg [15:0] trigger_loc, + output reg [1:0] trigger_mode, output reg request_start, output reg request_stop, input wire [ADDR_WIDTH-1:0] read_pointer, @@ -28,6 +29,7 @@ module logic_analyzer_fsm_registers( ); initial trigger_loc = 0; + initial trigger_mode = 0; initial request_start = 0; initial request_stop = 0; @@ -50,20 +52,22 @@ module logic_analyzer_fsm_registers( if(!rw_i) begin case (addr_i) BASE_ADDR + 0: rdata_o <= state; - BASE_ADDR + 1: rdata_o <= trigger_loc; - BASE_ADDR + 2: rdata_o <= request_start; - BASE_ADDR + 3: rdata_o <= request_stop; - BASE_ADDR + 4: rdata_o <= read_pointer; - BASE_ADDR + 5: rdata_o <= write_pointer; + BASE_ADDR + 1: rdata_o <= trigger_mode; + BASE_ADDR + 2: rdata_o <= trigger_loc; + BASE_ADDR + 3: rdata_o <= request_start; + BASE_ADDR + 4: rdata_o <= request_stop; + BASE_ADDR + 5: rdata_o <= read_pointer; + BASE_ADDR + 6: rdata_o <= write_pointer; endcase end // writes else begin case (addr_i) - BASE_ADDR + 1: trigger_loc <= wdata_i; - BASE_ADDR + 2: request_start <= wdata_i; - BASE_ADDR + 3: request_stop <= wdata_i; + BASE_ADDR + 1: trigger_mode <= wdata_i; + BASE_ADDR + 2: trigger_loc <= wdata_i; + BASE_ADDR + 3: request_start <= wdata_i; + BASE_ADDR + 4: request_stop <= wdata_i; endcase end end