From a1c7d194e856aee8c9a803d0ca2f42db5eb822ae Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 14 Jan 2026 14:56:22 -0700 Subject: [PATCH] ethernet: use context manager to read generated LiteEth Verilog --- src/manta/ethernet/liteeth_gen.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/manta/ethernet/liteeth_gen.py b/src/manta/ethernet/liteeth_gen.py index dfddda9..cb7ad09 100755 --- a/src/manta/ethernet/liteeth_gen.py +++ b/src/manta/ethernet/liteeth_gen.py @@ -664,8 +664,5 @@ def main(core_config): builder = Builder(soc, compile_gateware=False, output_dir=path) builder.build(build_name="liteeth_core") - file = open(path + "/gateware/liteeth_core.v") - data = file.read() - file.close() - - return data + with open(path + "/gateware/liteeth_core.v") as f: + return f.read()