From 9640d7db3e30e7a928cfe5d0bbeee55d46ac28ef Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 14 Jan 2026 13:34:52 -0700 Subject: [PATCH] examples: use symlinked bash and Tcl scripts --- examples/common/build.tcl | 35 ++++++++++++++++++ examples/common/build_ice40.sh | 13 +++++++ examples/common/build_vivado.sh | 35 ++++++++++++++++++ .../verilog/icestick/uart_io_core/build.sh | 8 +---- .../icestick/uart_logic_analyzer/build.sh | 8 +---- .../ether_logic_analyzer_io_core/build.sh | 7 +--- .../ether_logic_analyzer_io_core/build.tcl | 36 ------------------- .../nexys4_ddr/uart_host_to_fpga_mem/build.sh | 7 +--- .../uart_host_to_fpga_mem/build.tcl | 36 ------------------- .../verilog/nexys4_ddr/uart_io_core/build.sh | 7 +--- .../verilog/nexys4_ddr/uart_io_core/build.tcl | 36 ------------------- .../nexys4_ddr/uart_logic_analyzer/build.sh | 7 +--- .../nexys4_ddr/uart_logic_analyzer/build.tcl | 36 ------------------- 13 files changed, 89 insertions(+), 182 deletions(-) create mode 100644 examples/common/build.tcl create mode 100755 examples/common/build_ice40.sh create mode 100755 examples/common/build_vivado.sh mode change 100755 => 120000 examples/verilog/icestick/uart_io_core/build.sh mode change 100755 => 120000 examples/verilog/icestick/uart_logic_analyzer/build.sh mode change 100755 => 120000 examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh delete mode 100644 examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl mode change 100755 => 120000 examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh delete mode 100644 examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl mode change 100755 => 120000 examples/verilog/nexys4_ddr/uart_io_core/build.sh delete mode 100644 examples/verilog/nexys4_ddr/uart_io_core/build.tcl mode change 100755 => 120000 examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh delete mode 100644 examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl diff --git a/examples/common/build.tcl b/examples/common/build.tcl new file mode 100644 index 0000000..1d7ae16 --- /dev/null +++ b/examples/common/build.tcl @@ -0,0 +1,35 @@ +#!/usr/bin/tclsh + +set partNum xc7a100tcsg324-1 + +read_verilog -sv [ glob ../*.{sv,v,svh,vh} ] +read_xdc ../top_level.xdc + +set_part $partNum + +# synth +synth_design -top top_level -part $partNum -verbose +report_utilization -file post_synth_util.rpt +report_timing_summary -file post_synth_timing_summary.rpt +report_timing -file post_synth_timing.rpt + +# place +opt_design +place_design +phys_opt_design +report_utilization -file post_place_util.rpt + +report_clock_utilization -file clock_util.rpt +report_timing_summary -file post_place_timing_summary.rpt +report_timing -file post_place_timing.rpt + +# route design and generate bitstream +route_design -directive Explore +write_bitstream -force out.bit + +report_route_status -file post_route_status.rpt +report_timing_summary -file post_route_timing_summary.rpt +report_timing -file post_route_timing.rpt +report_power -file post_route_power.rpt +report_drc -file post_imp_drc.rpt +write_verilog -force cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/common/build_ice40.sh b/examples/common/build_ice40.sh new file mode 100755 index 0000000..452089e --- /dev/null +++ b/examples/common/build_ice40.sh @@ -0,0 +1,13 @@ +#!/usr/bin/env bash +set -euo pipefail + +# Generate Verilog source for Manta +python3 -m manta gen manta.yaml manta.v + +# Clean build/ directory, and run tools from within it +rm -rf build/ +mkdir -p build/ +cd build +$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' ../top_level.sv +$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf ../top_level.pcf --asc top_level.asc +$ICEPACK top_level.asc top_level.bin diff --git a/examples/common/build_vivado.sh b/examples/common/build_vivado.sh new file mode 100755 index 0000000..689fb6a --- /dev/null +++ b/examples/common/build_vivado.sh @@ -0,0 +1,35 @@ +#!/usr/bin/env bash +set -euo pipefail + +# Generate Verilog source for Manta +python3 -m manta gen manta.yaml manta.v + +# Determine where Vivado is located - exactly one of PATH or $VIVADO must be available +vivado_on_path=false +vivado_env_set=false + +if command -v vivado &> /dev/null; then + vivado_on_path=true +fi + +if [[ -v VIVADO ]]; then + vivado_env_set=true +fi + +if $vivado_on_path && $vivado_env_set; then + echo "Error: Both \$VIVADO is set and 'vivado' is on PATH. Please use only one." >&2 + exit 1 +elif $vivado_on_path; then + VIVADO_CMD="vivado" +elif $vivado_env_set; then + VIVADO_CMD="$VIVADO" +else + echo "Error: Vivado not found. Either set \$VIVADO environment variable or add 'vivado' to PATH." >&2 + exit 1 +fi + +# Clean build/ directory, and run Vivado from within it +rm -rf build/ +mkdir -p build/ +cd build +$VIVADO_CMD -mode batch -source ../../../../common/build.tcl diff --git a/examples/verilog/icestick/uart_io_core/build.sh b/examples/verilog/icestick/uart_io_core/build.sh deleted file mode 100755 index 78b10b9..0000000 --- a/examples/verilog/icestick/uart_io_core/build.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv -$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc -$ICEPACK top_level.asc top_level.bin diff --git a/examples/verilog/icestick/uart_io_core/build.sh b/examples/verilog/icestick/uart_io_core/build.sh new file mode 120000 index 0000000..8860b0d --- /dev/null +++ b/examples/verilog/icestick/uart_io_core/build.sh @@ -0,0 +1 @@ +../../../common/build_ice40.sh \ No newline at end of file diff --git a/examples/verilog/icestick/uart_logic_analyzer/build.sh b/examples/verilog/icestick/uart_logic_analyzer/build.sh deleted file mode 100755 index 78b10b9..0000000 --- a/examples/verilog/icestick/uart_logic_analyzer/build.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv -$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc -$ICEPACK top_level.asc top_level.bin diff --git a/examples/verilog/icestick/uart_logic_analyzer/build.sh b/examples/verilog/icestick/uart_logic_analyzer/build.sh new file mode 120000 index 0000000..8860b0d --- /dev/null +++ b/examples/verilog/icestick/uart_logic_analyzer/build.sh @@ -0,0 +1 @@ +../../../common/build_ice40.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh deleted file mode 100755 index 591adda..0000000 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -mkdir -p build/ -$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh new file mode 120000 index 0000000..fdafb65 --- /dev/null +++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh @@ -0,0 +1 @@ +../../../common/build_vivado.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl deleted file mode 100644 index 0e7570e..0000000 --- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir build - -read_verilog -sv [ glob *.{sv,v,svh,vh} ] -read_xdc top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh deleted file mode 100755 index 591adda..0000000 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -mkdir -p build/ -$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh new file mode 120000 index 0000000..fdafb65 --- /dev/null +++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh @@ -0,0 +1 @@ +../../../common/build_vivado.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl deleted file mode 100644 index 0e7570e..0000000 --- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir build - -read_verilog -sv [ glob *.{sv,v,svh,vh} ] -read_xdc top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys4_ddr/uart_io_core/build.sh b/examples/verilog/nexys4_ddr/uart_io_core/build.sh deleted file mode 100755 index 591adda..0000000 --- a/examples/verilog/nexys4_ddr/uart_io_core/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -mkdir -p build/ -$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_io_core/build.sh b/examples/verilog/nexys4_ddr/uart_io_core/build.sh new file mode 120000 index 0000000..fdafb65 --- /dev/null +++ b/examples/verilog/nexys4_ddr/uart_io_core/build.sh @@ -0,0 +1 @@ +../../../common/build_vivado.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/uart_io_core/build.tcl b/examples/verilog/nexys4_ddr/uart_io_core/build.tcl deleted file mode 100644 index 0e7570e..0000000 --- a/examples/verilog/nexys4_ddr/uart_io_core/build.tcl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir build - -read_verilog -sv [ glob *.{sv,v,svh,vh} ] -read_xdc top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh deleted file mode 100755 index 591adda..0000000 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash -set -e - -python3 -m manta gen manta.yaml manta.v -mkdir -p build/ -$VIVADO -mode batch -source build.tcl diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh new file mode 120000 index 0000000..fdafb65 --- /dev/null +++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh @@ -0,0 +1 @@ +../../../common/build_vivado.sh \ No newline at end of file diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl b/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl deleted file mode 100644 index 0e7570e..0000000 --- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir build - -read_verilog -sv [ glob *.{sv,v,svh,vh} ] -read_xdc top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true