From bc616fd3bf217268aaab55de395786cdf7c6a753 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 14:22:29 -0800 Subject: [PATCH 01/89] inital source, imported from splat --- .DS_Store | Bin 0 -> 6148 bytes .github/workflows/build_docs.yml | 4 +- .github/workflows/build_examples.yml | 25 - .github/workflows/functional_simulation.yml | 29 - ...{formal_verification.yml => run_tests.yml} | 22 +- .gitignore | 35 +- Makefile | 121 +--- README.md | 4 +- examples/icestick/io_core/manta.yaml | 16 - examples/icestick/io_core/run_io_core.py | 45 -- examples/icestick/io_core/top_level.pcf | 67 -- examples/icestick/io_core/top_level.sv | 32 - .../nexys_a7/block_mem_uart/api_example.py | 18 - examples/nexys_a7/block_mem_uart/manta.yaml | 11 - .../nexys_a7/block_mem_uart/src/top_level.sv | 24 - .../nexys_a7/block_mem_uart/xdc/top_level.xdc | 254 -------- examples/nexys_a7/build.tcl | 37 -- .../nexys_a7/io_core_ether/api_example.py | 40 -- examples/nexys_a7/io_core_ether/manta.yaml | 25 - .../nexys_a7/io_core_ether/src/divider.sv | 193 ------ .../nexys_a7/io_core_ether/src/top_level.sv | 61 -- .../nexys_a7/io_core_ether/xdc/top_level.xdc | 254 -------- examples/nexys_a7/io_core_uart/api_example.py | 40 -- examples/nexys_a7/io_core_uart/manta.yaml | 26 - .../nexys_a7/io_core_uart/src/top_level.sv | 48 -- .../nexys_a7/io_core_uart/xdc/top_level.xdc | 254 -------- .../nexys_a7/large_io_core_uart/manta.yaml | 23 - .../large_io_core_uart/src/top_level.sv | 32 - examples/nexys_a7/large_io_core_uart/test.py | 26 - .../large_io_core_uart/xdc/top_level.xdc | 254 -------- .../nexys_a7/logic_analyzer_uart/manta.yaml | 20 - .../logic_analyzer_uart/sim/playback.v | 58 -- .../logic_analyzer_uart/sim/playback_tb.sv | 38 -- .../logic_analyzer_uart/src/top_level.sv | 28 - .../logic_analyzer_uart/xdc/top_level.xdc | 254 -------- .../nexys_a7/ps2_logic_analyzer/manta.yaml | 18 - .../ps2_logic_analyzer/sim/playback.v | 52 -- .../ps2_logic_analyzer/sim/playback_tb.sv | 80 --- .../ps2_logic_analyzer/src/top_level.sv | 25 - .../ps2_logic_analyzer/xdc/top_level.xdc | 254 -------- .../video_sprite_ether/img/buff_doge.png | Bin 69692 -> 0 bytes .../video_sprite_ether/img/no_testbenches.png | Bin 94971 -> 0 bytes .../video_sprite_ether/img/pop_cat.png | Bin 59936 -> 0 bytes .../nexys_a7/video_sprite_ether/manta.yaml | 10 - .../nexys_a7/video_sprite_ether/send_image.py | 37 -- .../nexys_a7/video_sprite_ether/src/clk_gen.v | 207 ------- .../video_sprite_ether/src/top_level.sv | 108 ---- .../nexys_a7/video_sprite_ether/src/vga.sv | 68 -- .../video_sprite_ether/xdc/top_level.xdc | 253 -------- .../video_sprite_uart/img/buff_doge.png | Bin 69692 -> 0 bytes .../video_sprite_uart/img/no_testbenches.png | Bin 94971 -> 0 bytes .../video_sprite_uart/img/pop_cat.png | Bin 59936 -> 0 bytes .../nexys_a7/video_sprite_uart/manta.yaml | 11 - .../nexys_a7/video_sprite_uart/send_image.py | 37 -- .../nexys_a7/video_sprite_uart/src/clk_gen.v | 207 ------- .../video_sprite_uart/src/top_level.sv | 96 --- .../nexys_a7/video_sprite_uart/src/vga.sv | 68 -- .../video_sprite_uart/xdc/top_level.xdc | 253 -------- pyproject.toml | 16 +- src/manta/__init__.py | 384 +----------- src/manta/__main__.py | 4 +- src/manta/block_mem_core/__init__.py | 77 --- src/manta/block_mem_core/block_memory.v | 114 ---- .../block_mem_core/block_memory_inst_tmpl.v | 21 - src/manta/block_mem_core/dual_port_bram.v | 60 -- src/manta/cli.py | 126 ++++ src/manta/ether_iface/__init__.py | 208 ------- src/manta/ether_iface/aggregate.v | 46 -- src/manta/ether_iface/bitorder.v | 114 ---- src/manta/ether_iface/cksum.v | 80 --- src/manta/ether_iface/crc32.v | 70 --- src/manta/ether_iface/ether.v | 77 --- src/manta/ether_iface/ethernet_rx.v | 41 -- src/manta/ether_iface/ethernet_rx_inst_tmpl.v | 13 - src/manta/ether_iface/ethernet_tx.v | 40 -- src/manta/ether_iface/ethernet_tx_inst_tmpl.v | 13 - src/manta/ether_iface/firewall.v | 80 --- src/manta/ether_iface/mac_rx.v | 106 ---- src/manta/ether_iface/mac_tx.v | 242 -------- src/manta/io_core.py | 260 ++++++++ src/manta/io_core/__init__.py | 213 ------- src/manta/io_core/io_core_def_tmpl.v | 77 --- src/manta/io_core/io_core_inst_tmpl.v | 18 - src/manta/la_core/__init__.py | 463 -------------- src/manta/la_core/logic_analyzer_controller.v | 92 --- src/manta/la_core/logic_analyzer_def_tmpl.v | 142 ----- .../la_core/logic_analyzer_fsm_registers.v | 75 --- src/manta/la_core/logic_analyzer_inst_tmpl.v | 14 - .../la_core/logic_analyzer_playback_tmpl.v | 50 -- src/manta/la_core/trigger.v | 45 -- src/manta/la_core/trigger_block_def_tmpl.v | 62 -- src/manta/la_core/trigger_block_inst_tmpl.v | 11 - src/manta/logic_analyzer_core.py | 558 +++++++++++++++++ src/manta/manta.py | 170 +++++ src/manta/manta_def_tmpl.v | 34 - src/manta/memory_core.py | 205 ++++++ src/manta/uart.py | 583 ++++++++++++++++++ src/manta/uart_iface/__init__.py | 186 ------ src/manta/uart_iface/bridge_rx.v | 150 ----- src/manta/uart_iface/bridge_tx.v | 70 --- src/manta/uart_iface/uart_rx.v | 62 -- .../uart_iface/uart_rx_bridge_rx_inst_tmpl.v | 20 - src/manta/uart_iface/uart_tx.v | 61 -- .../uart_iface/uart_tx_bridge_tx_inst_tmpl.v | 23 - src/manta/utils.py | 223 +++---- .../invalid_configs/0_mangled_yaml.yaml | 26 - .../invalid_configs/1_mangled_yaml.yaml | 26 - .../invalid_configs/2_mangled_yaml.yaml | 26 - test/auto_gen/run_tests.py | 56 -- test/auto_gen/valid_configs/0_io_core.yaml | 26 - .../valid_configs/1_logic_analyzer.yaml | 19 - test/formal_verification/bridge_rx.sby | 29 - test/functional_sim/block_memory_tb.sv | 182 ------ test/functional_sim/bridge_rx_tb.sv | 185 ------ test/functional_sim/bridge_tx_tb.sv | 116 ---- test/functional_sim/ethernet_rx_tb.sv | 98 --- test/functional_sim/ethernet_tx_tb.sv | 121 ---- test/functional_sim/io_core_tb/io_core.v | 118 ---- test/functional_sim/io_core_tb/io_core_tb.sv | 277 --------- .../logic_analyzer_tb/logic_analyzer_tb.sv | 257 -------- .../logic_analyzer_tb/manta.yaml | 19 - test/functional_sim/mac_tb.sv | 86 --- test/functional_sim/uart_rx_tb.sv | 94 --- test/functional_sim/uart_tx_tb.sv | 99 --- test/test_bridge_rx_sim.py | 120 ++++ test/test_bridge_tx_sim.py | 67 ++ test/test_io_core_hw.py | 129 ++++ test/test_io_core_sim.py | 155 +++++ test/test_logic_analyzer_hw.py | 84 +++ test/test_logic_analyzer_sim.py | 140 +++++ test/test_mem_core_hw.py | 114 ++++ test/test_mem_core_sim.py | 45 ++ test/test_toolchains.py | 15 + test/test_uart_rx_sim.py | 65 ++ test/test_uart_tx_sim.py | 57 ++ test/test_verilog_gen.py | 14 + .../manta.yaml => test_verilog_gen.yaml} | 15 +- 137 files changed, 3071 insertions(+), 9810 deletions(-) create mode 100644 .DS_Store delete mode 100644 .github/workflows/build_examples.yml delete mode 100644 .github/workflows/functional_simulation.yml rename .github/workflows/{formal_verification.yml => run_tests.yml} (53%) delete mode 100644 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test/test_bridge_tx_sim.py create mode 100644 test/test_io_core_hw.py create mode 100644 test/test_io_core_sim.py create mode 100644 test/test_logic_analyzer_hw.py create mode 100644 test/test_logic_analyzer_sim.py create mode 100644 test/test_mem_core_hw.py create mode 100644 test/test_mem_core_sim.py create mode 100644 test/test_toolchains.py create mode 100644 test/test_uart_rx_sim.py create mode 100644 test/test_uart_tx_sim.py create mode 100644 test/test_verilog_gen.py rename test/{functional_sim/io_core_tb/manta.yaml => test_verilog_gen.yaml} (53%) diff --git a/.DS_Store b/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..81229e8d26382bd3469cb3d9bb2de3f1954844ac GIT binary patch literal 6148 zcmeH~Jqp4=5QS&dB4Cr!avKle4VIuM@B*S@B?yZB9^E%TjnP_yyn&f-XEsBUS7b9H zqQmpN5$Q#wgBxXSVPuMYE)TiO>2iLYjtb*@FJ*K=2U&T%hcRwa*e@u>x3=Er<$CqZN!+^)bZi z-VT<$t|nVB+C_8t(7dzS6a&*}7cEF&S{)2jfC`Khm`C2*`M-mIoBu~GOsN1B_%j7` zvE6S6yi}g8AFpTiLso6w;GkcQ@b(jc#E#+>+ztE17GO=bASy8a2)GOkRN$uyya2`( B5q1Co literal 0 HcmV?d00001 diff --git a/.github/workflows/build_docs.yml b/.github/workflows/build_docs.yml index 3c0d632..ef4ca38 100644 --- a/.github/workflows/build_docs.yml +++ b/.github/workflows/build_docs.yml @@ -1,4 +1,4 @@ -name: build_docs +name: docs_site on: push: branches: @@ -17,5 +17,5 @@ jobs: with: key: ${{ github.ref }} path: .cache - - run: pip install mkdocs-material + - run: pip install mkdocs-material - run: mkdocs gh-deploy --force diff --git a/.github/workflows/build_examples.yml b/.github/workflows/build_examples.yml deleted file mode 100644 index a9c0598..0000000 --- a/.github/workflows/build_examples.yml +++ /dev/null @@ -1,25 +0,0 @@ -name: build_examples -on: [push] -jobs: - examples: - runs-on: self-hosted - steps: - - uses: actions/checkout@v3 - - name: Install Manta from source - run: | - pip install setuptools --upgrade - - # omitting the following commmand causes the version of setuptools - # used by python to get confused, and it doesn't detect the name - # or version of the package from pyproject.toml - so the following - # workaround is used: - # https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377 - export DEB_PYTHON_INSTALL_LAYOUT=deb_system - - python3 -m pip install . - - - name: Build Nexys A7 examples - run: make nexys_a7 - - - name: Build Icestick examples - run: make icestick diff --git a/.github/workflows/functional_simulation.yml b/.github/workflows/functional_simulation.yml deleted file mode 100644 index 1232960..0000000 --- a/.github/workflows/functional_simulation.yml +++ /dev/null @@ -1,29 +0,0 @@ -name: functional_simulation -on: [push] -jobs: - all: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v3 - - - name: Install Manta from Source - run: | - pip install setuptools --upgrade - - # omitting the following commmand causes the version of setuptools - # used by python to get confused, and it doesn't detect the name - # or version of the package from pyproject.toml - so the following - # workaround is used: - # https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377 - export DEB_PYTHON_INSTALL_LAYOUT=deb_system - - python3 -m pip install . - - - name: Install oss-cad-suite - run: | - wget --no-verbose https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2023-02-23/oss-cad-suite-linux-x64-20230223.tgz - tar -xzf oss-cad-suite-linux-x64-20230223.tgz - echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH - - - name: Run functional simulations - run: make sim \ No newline at end of file diff --git a/.github/workflows/formal_verification.yml b/.github/workflows/run_tests.yml similarity index 53% rename from .github/workflows/formal_verification.yml rename to .github/workflows/run_tests.yml index 3b548cc..331fb58 100644 --- a/.github/workflows/formal_verification.yml +++ b/.github/workflows/run_tests.yml @@ -1,4 +1,4 @@ -name: formal_verification +name: run_tests on: [push] jobs: all: @@ -8,7 +8,7 @@ jobs: - name: Install Manta from Source run: | - pip install setuptools --upgrade + python -m pip install -U pip # omitting the following commmand causes the version of setuptools # used by python to get confused, and it doesn't detect the name @@ -17,13 +17,15 @@ jobs: # https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377 export DEB_PYTHON_INSTALL_LAYOUT=deb_system - python3 -m pip install . + python -m pip install ".[dev]" - - name: Install oss-cad-suite - run: | - wget --no-verbose https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2023-02-23/oss-cad-suite-linux-x64-20230223.tgz - tar -xzf oss-cad-suite-linux-x64-20230223.tgz - echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH + # export tool paths + export VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado + export YOSYS=/tools/oss-cad-suite/bin/yosys + export NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr_ice40 + export ICEPACK=/tools/oss-cad-suite/bin/icepack + export ICEPROG=/tools/oss-cad-suite/bin/iceprog - - name: Run formal verification - run: make formal \ No newline at end of file + + - name: Run tests + run: make test \ No newline at end of file diff --git a/.gitignore b/.gitignore index 39837fb..8fb17e5 100644 --- a/.gitignore +++ b/.gitignore @@ -1,33 +1,10 @@ -# Hidden files -.DS_Store -*.vscode/ - -# Python outputs venv/ -dist/ -build/ -*.egg-info +manta.egg-info/ +.pytest_cache __pycache__/ +build/ -# Vivado output products -*.Xil/ -*.log -*.jou -*.rpt -*.bit -cpu_impl_netlist.v - -# IceStorm output products -*.bin - -# iVerilog output products +*.v +*.sv *.vcd -*.out - -# Formal outputs -test/formal_verification/*_basic -test/formal_verification/*_cover - -# Manta output products -manta.v -*.mem \ No newline at end of file +*.out \ No newline at end of file diff --git a/Makefile b/Makefile index b0ecfe5..c22f0d1 100644 --- a/Makefile +++ b/Makefile @@ -1,123 +1,12 @@ -# Tool Paths -VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado -YOSYS=/tools/oss-cad-suite/bin/yosys -NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr-ice40 -ICEPACK=/tools/oss-cad-suite/bin/icepack +.PHONY: test format clean serve_docs +test: + pytest -test: auto_gen sim formal - -examples: icestick nexys_a7 +format: + black . clean: - @echo "Deleting everything matched by .gitignore" git clean -Xdf serve_docs: mkdocs serve - -# Python Operations -python_build: - python3 -m build - -pypi_upload: build - python3 -m twine upload --repository testpypi dist/* - -python_lint: - python3 -m black src/manta/__init__.py - python3 -m black src/manta/__main__.py - -# API Generation Tests -auto_gen: - python3 test/auto_gen/run_tests.py - -# Build Examples -NEXYS_A7_EXAMPLES := io_core_ether io_core_uart ps2_logic_analyzer video_sprite_ether video_sprite_uart block_mem_uart logic_analyzer_uart large_io_core_uart - -.PHONY: nexys_a7 $(NEXYS_A7_EXAMPLES) -nexys_a7: $(NEXYS_A7_EXAMPLES) - -$(NEXYS_A7_EXAMPLES): - cd examples/nexys_a7/$@; \ - python3 -m manta gen manta.yaml src/manta.v; \ - rm -rf obj; \ - mkdir -p obj; \ - $(VIVADO) -mode batch \ - -source ../build.tcl \ - -log obj/build.log \ - -jou obj/build.jou; \ - rm -rf .Xil; - -ICESTICK_EXAMPLES := io_core - -.PHONY: icestick $(ICESTICK_EXAMPLES) -icestick: $(ICESTICK_EXAMPLES) - -$(ICESTICK_EXAMPLES): - cd examples/icestick/$@; \ - python3 -m manta gen manta.yaml manta.v; \ - $(YOSYS) -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv; \ - $(NEXTPNR_ICE40) --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc; \ - $(ICEPACK) top_level.asc top_level.bin; \ - rm -f *.json; \ - rm -f *.asc; - -# Formal Verification -formal: - sby -f test/formal_verification/bridge_rx.sby - -# Functional Simulation -sim: ethernet_tx_tb ethernet_rx_tb mac_tb block_memory_tb io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb block_memory_tb - -ethernet_tx_tb: - iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_tx_tb.sv - vvp sim.out - rm sim.out - -ethernet_rx_tb: - iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_rx_tb.sv - vvp sim.out - rm sim.out - -mac_tb: - iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/mac_tb.sv - vvp sim.out - rm sim.out - -block_memory_tb: - iverilog -g2012 -o sim.out -y src/manta/block_mem_core test/functional_sim/block_memory_tb.sv - vvp sim.out - rm sim.out - -io_core_tb: - iverilog -g2012 -o sim.out \ - test/functional_sim/io_core_tb/io_core_tb.sv \ - test/functional_sim/io_core_tb/io_core.v - vvp sim.out - rm sim.out - -logic_analyzer_tb: - cd test/functional_sim/logic_analyzer_tb; \ - python3 -m manta gen manta.yaml manta.v; \ - iverilog -g2012 -o sim.out logic_analyzer_tb.sv manta.v; \ - vvp sim.out; \ - rm sim.out - -bridge_rx_tb: - iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_rx_tb.sv - vvp sim.out - rm sim.out - -bridge_tx_tb: - iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_tx_tb.sv - vvp sim.out - rm sim.out - -uart_rx_tb: - iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/uart_rx_tb.sv - vvp sim.out - rm sim.out - -uart_tx_tb: - iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/uart_tx_tb.sv - vvp sim.out - rm sim.out diff --git a/README.md b/README.md index 3a02d2b..e49515c 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,7 @@ ![](doc/assets/logo.png) ## Manta: An In-Situ Debugging Tool for Programmable Hardware -![functional_simulation](https://github.com/fischermoseley/manta/actions/workflows/functional_simulation.yml/badge.svg) -![formal_verification](https://github.com/fischermoseley/manta/actions/workflows/formal_verification.yml/badge.svg) -![build_examples](https://github.com/fischermoseley/manta/actions/workflows/build_examples.yml/badge.svg) +![run_tests](https://github.com/fischermoseley/manta/actions/workflows/run_tests.yml/badge.svg) ![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg) [![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0) diff --git a/examples/icestick/io_core/manta.yaml b/examples/icestick/io_core/manta.yaml deleted file mode 100644 index 80757ae..0000000 --- a/examples/icestick/io_core/manta.yaml +++ /dev/null @@ -1,16 +0,0 @@ ---- -cores: - my_io_core: - type: io - - outputs: - LED0: 1 - LED1: 1 - LED2: 1 - LED3: 1 - LED4: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 12000000 \ No newline at end of file diff --git a/examples/icestick/io_core/run_io_core.py b/examples/icestick/io_core/run_io_core.py deleted file mode 100644 index 36cc4dd..0000000 --- a/examples/icestick/io_core/run_io_core.py +++ /dev/null @@ -1,45 +0,0 @@ -from manta import Manta -from time import sleep - -m = Manta('manta.yaml') - -i = 0 -while True: - i = (i+1) % 5 - - if(i==0): - m.my_io_core.LED0.set(1) - m.my_io_core.LED1.set(0) - m.my_io_core.LED2.set(0) - m.my_io_core.LED3.set(0) - m.my_io_core.LED4.set(0) - - if(i==1): - m.my_io_core.LED0.set(0) - m.my_io_core.LED1.set(1) - m.my_io_core.LED2.set(0) - m.my_io_core.LED3.set(0) - m.my_io_core.LED4.set(0) - - if(i==2): - m.my_io_core.LED0.set(0) - m.my_io_core.LED1.set(0) - m.my_io_core.LED2.set(1) - m.my_io_core.LED3.set(0) - m.my_io_core.LED4.set(0) - - if(i==3): - m.my_io_core.LED0.set(0) - m.my_io_core.LED1.set(0) - m.my_io_core.LED2.set(0) - m.my_io_core.LED3.set(1) - m.my_io_core.LED4.set(0) - - if(i==4): - m.my_io_core.LED0.set(0) - m.my_io_core.LED1.set(0) - m.my_io_core.LED2.set(0) - m.my_io_core.LED3.set(0) - m.my_io_core.LED4.set(1) - - sleep(0.1) \ No newline at end of file diff --git a/examples/icestick/io_core/top_level.pcf b/examples/icestick/io_core/top_level.pcf deleted file mode 100644 index d042aa0..0000000 --- a/examples/icestick/io_core/top_level.pcf +++ /dev/null @@ -1,67 +0,0 @@ -# Generic iCEstick placement constraints file - -# Red LEDs -set_io LED0 99 -set_io LED1 98 -set_io LED2 97 -set_io LED3 96 - -# Green LED -set_io LED4 95 - -# IrDA port -#set_io RXD 106 -#set_io TXD 105 -#set_io SD 107 - -# Pmod connector -#set_io PIO1_02 78 # Pin 1 -#set_io PIO1_03 79 # Pin 2 -#set_io PIO1_04 80 # Pin 3 -#set_io PIO1_05 81 # Pin 4 -#set_io PIO1_06 87 # Pin 7 -#set_io PIO1_07 88 # Pin 8 -#set_io PIO1_08 90 # Pin 9 -#set_io PIO1_09 91 # Pin 10 - -# Connector J1 -#set_io PIO0_02 112 # Pin 3 -#set_io PIO0_03 113 # Pin 4 -#set_io PIO0_04 114 # Pin 5 -#set_io PIO0_05 115 # Pin 6 -#set_io PIO0_06 116 # Pin 7 -#set_io PIO0_07 117 # Pin 8 -#set_io PIO0_08 118 # Pin 9 -#set_io PIO0_09 119 # Pin 10 - -# Connector J3 -#set_io PIO2_17 62 # Pin 3 -#set_io PIO2_16 61 # Pin 4 -#set_io PIO2_15 60 # Pin 5 -#set_io PIO2_14 56 # Pin 6 -#set_io PIO2_13 48 # Pin 7 -#set_io PIO2_12 47 # Pin 8 -#set_io PIO2_11 45 # Pin 9 -#set_io PIO2_10 44 # Pin 10 - -# FTDI Port B UART -#set_io DCDn 1 -#set_io DSRn 2 -#set_io DTRn 3 -#set_io CTSn 4 -#set_io RTSn 7 -set_io rs232_tx_ttl 8 -set_io rs232_rx_ttl 9 - -# SPI -#set_io SPI_SCK 70 -#set_io SPI_SI 68 -#set_io SPI_SO 67 -#set_io SPI_SS_B 71 - -# Configuration pins -#set_io CDONE 65 -#set_io CRESET_B 66 - -# 12 MHz clock -set_io clk 21 diff --git a/examples/icestick/io_core/top_level.sv b/examples/icestick/io_core/top_level.sv deleted file mode 100644 index c8a1711..0000000 --- a/examples/icestick/io_core/top_level.sv +++ /dev/null @@ -1,32 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`include "manta.v" - -module top_level ( - input wire clk, - - output logic LED0, - output logic LED1, - output logic LED2, - output logic LED3, - output logic LED4, - - input wire rs232_rx_ttl, - output logic rs232_tx_ttl - ); - - manta manta_inst ( - .clk(clk), - - .rx(rs232_rx_ttl), - .tx(rs232_tx_ttl), - - .LED0(LED0), - .LED1(LED1), - .LED2(LED2), - .LED3(LED3), - .LED4(LED4)); -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/block_mem_uart/api_example.py b/examples/nexys_a7/block_mem_uart/api_example.py deleted file mode 100644 index 6323e75..0000000 --- a/examples/nexys_a7/block_mem_uart/api_example.py +++ /dev/null @@ -1,18 +0,0 @@ -from manta import Manta -from time import sleep -from random import randint - -m = Manta('manta.yaml') - -for addr in range(1024): - number = randint(0,65535) - m.my_block_memory.write(addr, number) - - readback = m.my_block_memory.read(addr) - - if readback == number: - print(f"Success! Wrote and read back {hex(number)} from {hex(addr)}") - - else: - print(f"Failure! Wrote {hex(number)} to {hex(addr)}, but received {hex(readback)}") - exit() diff --git a/examples/nexys_a7/block_mem_uart/manta.yaml b/examples/nexys_a7/block_mem_uart/manta.yaml deleted file mode 100644 index 756dab7..0000000 --- a/examples/nexys_a7/block_mem_uart/manta.yaml +++ /dev/null @@ -1,11 +0,0 @@ ---- -cores: - my_block_memory: - type: block_memory - width: 16 - depth: 1024 - -uart: - port: "/dev/ttyUSB1" - baudrate: 2000000 - clock_freq: 100000000 \ No newline at end of file diff --git a/examples/nexys_a7/block_mem_uart/src/top_level.sv b/examples/nexys_a7/block_mem_uart/src/top_level.sv deleted file mode 100644 index bb5cd1a..0000000 --- a/examples/nexys_a7/block_mem_uart/src/top_level.sv +++ /dev/null @@ -1,24 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire uart_txd_in, - output logic uart_rxd_out); - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .my_block_memory_clk(clk), - .my_block_memory_addr(0), - .my_block_memory_din(0), - .my_block_memory_dout(), - .my_block_memory_we(0)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/block_mem_uart/xdc/top_level.xdc b/examples/nexys_a7/block_mem_uart/xdc/top_level.xdc deleted file mode 100644 index df10467..0000000 --- a/examples/nexys_a7/block_mem_uart/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/build.tcl b/examples/nexys_a7/build.tcl deleted file mode 100644 index 810232a..0000000 --- a/examples/nexys_a7/build.tcl +++ /dev/null @@ -1,37 +0,0 @@ -#!/usr/bin/tclsh - -set partNum xc7a100tcsg324-1 -set outputDir obj - -read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ] -read_xdc ./xdc/top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -report_timing_summary -file $outputDir/post_synth_timing_summary.rpt -report_timing -file $outputDir/post_synth_timing.rpt - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -report_clock_utilization -file $outputDir/clock_util.rpt -report_timing_summary -file $outputDir/post_place_timing_summary.rpt -report_timing -file $outputDir/post_place_timing.rpt - -# route design and generate bitstream - -route_design -directive Explore -write_bitstream -force $outputDir/out.bit - -report_route_status -file $outputDir/post_route_status.rpt -report_timing_summary -file $outputDir/post_route_timing_summary.rpt -report_timing -file $outputDir/post_route_timing.rpt -report_power -file $outputDir/post_route_power.rpt -report_drc -file $outputDir/post_imp_drc.rpt -write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/nexys_a7/io_core_ether/api_example.py b/examples/nexys_a7/io_core_ether/api_example.py deleted file mode 100644 index d9d03b4..0000000 --- a/examples/nexys_a7/io_core_ether/api_example.py +++ /dev/null @@ -1,40 +0,0 @@ -from manta import Manta -from time import sleep - -m = Manta('manta.yaml') - -i = 0 -direction = "left" - -while True: - if direction == "left": - if i == 15: - direction = "right" - i = i - 1 - m.my_io_core.led16_r.set(1) - m.my_io_core.led16_g.set(0) - m.my_io_core.led16_b.set(1) - else: - i = i + 1 - - if direction == "right": - if i == 0: - direction = "left" - i = i + 1 - m.my_io_core.led16_r.set(0) - m.my_io_core.led16_g.set(1) - m.my_io_core.led16_b.set(0) - - else: - i = i - 1 - - m.my_io_core.led.set(2**i) - print(f"Input Ports:") - print(f" btnu: {m.my_io_core.btnu.get()}") - print(f" btnd: {m.my_io_core.btnd.get()}") - print(f" btnr: {m.my_io_core.btnr.get()}") - print(f" btnl: {m.my_io_core.btnl.get()}") - print(f" btnc: {m.my_io_core.btnc.get()}") - print(f" sw: {m.my_io_core.sw.get()}\n") - sleep(0.5) - diff --git a/examples/nexys_a7/io_core_ether/manta.yaml b/examples/nexys_a7/io_core_ether/manta.yaml deleted file mode 100644 index 4ca285e..0000000 --- a/examples/nexys_a7/io_core_ether/manta.yaml +++ /dev/null @@ -1,25 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: 1 - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -ethernet: - interface: "en8" - host_mac: "12:34:56:78:90:ab" \ No newline at end of file diff --git a/examples/nexys_a7/io_core_ether/src/divider.sv b/examples/nexys_a7/io_core_ether/src/divider.sv deleted file mode 100644 index 55aada8..0000000 --- a/examples/nexys_a7/io_core_ether/src/divider.sv +++ /dev/null @@ -1,193 +0,0 @@ -`default_nettype wire - -// file: divider.sv -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// popopopopopopopopopopop -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// __ethclk__50.00000______0.000______50.0______151.636_____98.575 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_________100.000____________0.010 - -`timescale 1ps/1ps - -module divider - - (// Clock in ports - // Clock out ports - output ethclk, - input clk - ); - // Input buffering - //------------------------------------ -wire clk_divider; -wire clk_in2_divider; - IBUF clkin1_ibufg - (.O (clk_divider), - .I (clk)); - - - - - // Clocking PRIMITIVE - //------------------------------------ - - // Instantiation of the MMCM PRIMITIVE - // * Unused inputs are tied off - // * Unused outputs are labeled unused - - wire ethclk_divider; - wire clk_out2_divider; - wire clk_out3_divider; - wire clk_out4_divider; - wire clk_out5_divider; - wire clk_out6_divider; - wire clk_out7_divider; - - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_int; - wire clkfbout_divider; - wire clkfbout_buf_divider; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (10.000), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (20.000), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (10.000)) - mmcm_adv_inst - // Output clocks - ( - .CLKFBOUT (clkfbout_divider), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (ethclk_divider), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clkout1_unused), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout_buf_divider), - .CLKIN1 (clk_divider), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (1'b0)); - -// Clock Monitor clock assigning -//-------------------------------------- - // Output buffering - //----------------------------------- - - BUFG clkf_buf - (.O (clkfbout_buf_divider), - .I (clkfbout_divider)); - - BUFG clkout1_buf - (.O (ethclk), - .I (ethclk_divider)); - -endmodule - -`default_nettype none diff --git a/examples/nexys_a7/io_core_ether/src/top_level.sv b/examples/nexys_a7/io_core_ether/src/top_level.sv deleted file mode 100644 index 913faca..0000000 --- a/examples/nexys_a7/io_core_ether/src/top_level.sv +++ /dev/null @@ -1,61 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire eth_crsdv, - input wire [1:0] eth_rxd, - output logic [1:0] eth_txd, - output logic eth_txen, - output logic eth_refclk, - output logic eth_rstn, - - input wire btnu, - input wire btnd, - input wire btnl, - input wire btnr, - input wire btnc, - input wire [15:0] sw, - output logic [15:0] led, - output logic led16_b, - output logic led16_g, - output logic led16_r, - output logic led17_b, - output logic led17_g, - output logic led17_r); - - // 50MHz clock generation for the RMII - logic ethclk; - divider div ( - .clk(clk), - .ethclk(ethclk)); - - assign eth_rstn = 1; - assign eth_refclk = ethclk; - - manta manta_inst ( - .clk(ethclk), - - .crsdv(eth_crsdv), - .rxd(eth_rxd), - .txen(eth_txen), - .txd(eth_txd), - - .btnu(btnu), - .btnd(btnd), - .btnl(btnl), - .btnr(btnr), - .btnc(btnc), - .sw(sw), - .led(led), - .led16_b(led16_b), - .led16_g(led16_g), - .led16_r(led16_r), - .led17_b(led17_b), - .led17_g(led17_g), - .led17_r(led17_r)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/io_core_ether/xdc/top_level.xdc b/examples/nexys_a7/io_core_ether/xdc/top_level.xdc deleted file mode 100644 index 119c5d3..0000000 --- a/examples/nexys_a7/io_core_ether/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/io_core_uart/api_example.py b/examples/nexys_a7/io_core_uart/api_example.py deleted file mode 100644 index d9d03b4..0000000 --- a/examples/nexys_a7/io_core_uart/api_example.py +++ /dev/null @@ -1,40 +0,0 @@ -from manta import Manta -from time import sleep - -m = Manta('manta.yaml') - -i = 0 -direction = "left" - -while True: - if direction == "left": - if i == 15: - direction = "right" - i = i - 1 - m.my_io_core.led16_r.set(1) - m.my_io_core.led16_g.set(0) - m.my_io_core.led16_b.set(1) - else: - i = i + 1 - - if direction == "right": - if i == 0: - direction = "left" - i = i + 1 - m.my_io_core.led16_r.set(0) - m.my_io_core.led16_g.set(1) - m.my_io_core.led16_b.set(0) - - else: - i = i - 1 - - m.my_io_core.led.set(2**i) - print(f"Input Ports:") - print(f" btnu: {m.my_io_core.btnu.get()}") - print(f" btnd: {m.my_io_core.btnd.get()}") - print(f" btnr: {m.my_io_core.btnr.get()}") - print(f" btnl: {m.my_io_core.btnl.get()}") - print(f" btnc: {m.my_io_core.btnc.get()}") - print(f" sw: {m.my_io_core.sw.get()}\n") - sleep(0.5) - diff --git a/examples/nexys_a7/io_core_uart/manta.yaml b/examples/nexys_a7/io_core_uart/manta.yaml deleted file mode 100644 index 867efbe..0000000 --- a/examples/nexys_a7/io_core_uart/manta.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: 1 - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/examples/nexys_a7/io_core_uart/src/top_level.sv b/examples/nexys_a7/io_core_uart/src/top_level.sv deleted file mode 100644 index d6e0f8c..0000000 --- a/examples/nexys_a7/io_core_uart/src/top_level.sv +++ /dev/null @@ -1,48 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire uart_txd_in, - output logic uart_rxd_out, - - input wire btnu, - input wire btnd, - input wire btnl, - input wire btnr, - input wire btnc, - - input wire [15:0] sw, - - output logic [15:0] led, - output logic led16_b, - output logic led16_g, - output logic led16_r, - output logic led17_b, - output logic led17_g, - output logic led17_r); - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .btnu(btnu), - .btnd(btnd), - .btnl(btnl), - .btnr(btnr), - .btnc(btnc), - .sw(sw), - .led(led), - .led16_b(led16_b), - .led16_g(led16_g), - .led16_r(led16_r), - .led17_b(led17_b), - .led17_g(led17_g), - .led17_r(led17_r)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/io_core_uart/xdc/top_level.xdc b/examples/nexys_a7/io_core_uart/xdc/top_level.xdc deleted file mode 100644 index 82c04c3..0000000 --- a/examples/nexys_a7/io_core_uart/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/large_io_core_uart/manta.yaml b/examples/nexys_a7/large_io_core_uart/manta.yaml deleted file mode 100644 index 25047eb..0000000 --- a/examples/nexys_a7/large_io_core_uart/manta.yaml +++ /dev/null @@ -1,23 +0,0 @@ ---- -cores: - io_core: - type: io - - inputs: - probe0: 1 - probe1: 2 - probe2: 8 - probe3: 20 - - outputs: - probe4: - width: 1 - initial_value: 1 - probe5: 2 - probe6: 8 - probe7: 20 - -uart: - port: "auto" - baudrate: 3000000 - clock_freq: 100000000 diff --git a/examples/nexys_a7/large_io_core_uart/src/top_level.sv b/examples/nexys_a7/large_io_core_uart/src/top_level.sv deleted file mode 100644 index 1664a41..0000000 --- a/examples/nexys_a7/large_io_core_uart/src/top_level.sv +++ /dev/null @@ -1,32 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire uart_txd_in, - output logic uart_rxd_out); - - logic probe0; - logic [1:0] probe1; - logic [7:0] probe2; - logic [19:0] probe3; - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .probe0(probe0), - .probe1(probe1), - .probe2(probe2), - .probe3(probe3), - .probe4(probe0), - .probe5(probe1), - .probe6(probe2), - .probe7(probe3)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/large_io_core_uart/test.py b/examples/nexys_a7/large_io_core_uart/test.py deleted file mode 100644 index f9bee51..0000000 --- a/examples/nexys_a7/large_io_core_uart/test.py +++ /dev/null @@ -1,26 +0,0 @@ -from manta import Manta -from random import randint -m = Manta('manta.yaml') - -n_tests = 100 -for i in range(n_tests): - print(f"-> Beginning test {i} of {n_tests}") - probe4 = randint(0, 1) - m.io_core.probe4.set(probe4) - assert m.io_core.probe4.get() == probe4 - assert m.io_core.probe0.get() == probe4 - - probe5 = randint(0, 3) - m.io_core.probe5.set(probe5) - assert m.io_core.probe5.get() == probe5 - assert m.io_core.probe1.get() == probe5 - - probe6 = randint(0, 255) - m.io_core.probe6.set(probe6) - assert m.io_core.probe6.get() == probe6 - assert m.io_core.probe2.get() == probe6 - - probe7 = randint(0, (2**20)-1) - m.io_core.probe7.set(probe7) - assert m.io_core.probe7.get() == probe7 - assert m.io_core.probe3.get() == probe7 diff --git a/examples/nexys_a7/large_io_core_uart/xdc/top_level.xdc b/examples/nexys_a7/large_io_core_uart/xdc/top_level.xdc deleted file mode 100644 index c23f104..0000000 --- a/examples/nexys_a7/large_io_core_uart/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] -# -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/logic_analyzer_uart/manta.yaml b/examples/nexys_a7/logic_analyzer_uart/manta.yaml deleted file mode 100644 index ccb1bea..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/manta.yaml +++ /dev/null @@ -1,20 +0,0 @@ ---- -cores: - my_logic_analyzer: - type: logic_analyzer - sample_depth: 1024 - - probes: - spike: 1 - jet: 2 - valentine: 3 - ed: 4 - ein: 5 - - triggers: - - ein EQ 3 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/examples/nexys_a7/logic_analyzer_uart/sim/playback.v b/examples/nexys_a7/logic_analyzer_uart/sim/playback.v deleted file mode 100644 index 9aa7a47..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/sim/playback.v +++ /dev/null @@ -1,58 +0,0 @@ -/* -This playback module was generated with Manta v0.0.5 on 23 Aug 2023 at 11:25:46 by fischerm - -If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! - -my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst ( - .clk(clk), - .enable(1'b1), - - .spike(spike), - .jet(jet), - .valentine(valentine), - .ed(ed), - .ein(ein)); - -*/ - - -module my_logic_analyzer_playback ( - input wire clk, - - input wire enable, - output reg done, - - output reg spike, - output reg [1:0] jet, - output reg [2:0] valentine, - output reg [3:0] ed, - output reg [4:0] ein); - - parameter MEM_FILE = ""; - localparam SAMPLE_DEPTH = 1024; - localparam TOTAL_PROBE_WIDTH = 15; - - reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0]; - reg [$clog2(SAMPLE_DEPTH)-1:0] addr; - reg [TOTAL_PROBE_WIDTH-1:0] sample; - - assign done = (addr >= SAMPLE_DEPTH); - - initial begin - $readmemb(MEM_FILE, capture, 0, SAMPLE_DEPTH-1); - addr = 0; - end - - always @(posedge clk) begin - if (enable && !done) begin - addr = addr + 1; - sample = capture[addr]; - {ein, ed, valentine, jet, spike} = sample; - end - end -endmodule \ No newline at end of file diff --git a/examples/nexys_a7/logic_analyzer_uart/sim/playback_tb.sv b/examples/nexys_a7/logic_analyzer_uart/sim/playback_tb.sv deleted file mode 100644 index d89ace9..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/sim/playback_tb.sv +++ /dev/null @@ -1,38 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module playback_tb(); - logic clk; - - always begin - #5; - clk = !clk; - end - - logic spike; - logic [1:0] jet; - logic [2:0] valentine; - logic [3:0] ed; - logic [4:0] ein; - - my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst ( - .clk(clk), - .enable(1'b1), - - .spike(spike), - .jet(jet), - .valentine(valentine), - .ed(ed), - .ein(ein)); - - initial begin - clk = 0; - $dumpfile("playback_tb.vcd"); - $dumpvars(0, playback_tb); - - #(450000*5); - $finish(); - end - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/logic_analyzer_uart/src/top_level.sv b/examples/nexys_a7/logic_analyzer_uart/src/top_level.sv deleted file mode 100644 index 2127b3d..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/src/top_level.sv +++ /dev/null @@ -1,28 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire uart_txd_in, - output logic uart_rxd_out - ); - - logic [4:0] counter = 0; - always @(posedge clk) counter <= counter + 1; - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .spike(counter[0]), - .jet(counter[1:0]), - .valentine(counter[2:0]), - .ed(counter[3:0]), - .ein(counter)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/logic_analyzer_uart/xdc/top_level.xdc b/examples/nexys_a7/logic_analyzer_uart/xdc/top_level.xdc deleted file mode 100644 index 81c1998..0000000 --- a/examples/nexys_a7/logic_analyzer_uart/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/ps2_logic_analyzer/manta.yaml b/examples/nexys_a7/ps2_logic_analyzer/manta.yaml deleted file mode 100644 index c2d1e5f..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/manta.yaml +++ /dev/null @@ -1,18 +0,0 @@ ---- -cores: - my_logic_analyzer: - type: logic_analyzer - sample_depth: 64000 - trigger_location: 15000 - - probes: - ps2_clk: 1 - ps2_data: 1 - - triggers: - - ps2_data FALLING - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 50000000 \ No newline at end of file diff --git a/examples/nexys_a7/ps2_logic_analyzer/sim/playback.v b/examples/nexys_a7/ps2_logic_analyzer/sim/playback.v deleted file mode 100644 index acf7d73..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/sim/playback.v +++ /dev/null @@ -1,52 +0,0 @@ -/* -This playback module was generated with Manta v0.0.5 on 19 Jul 2023 at 18:52:11 by fischerm - -If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! - -my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst ( - .clk(clk), - .enable(1'b1), - - .ps2_clk(ps2_clk), - .ps2_data(ps2_data)); - -*/ - - -module my_logic_analyzer_playback ( - input wire clk, - - input wire enable, - output reg done, - - output reg ps2_clk, - output reg ps2_data); - - parameter MEM_FILE = ""; - localparam SAMPLE_DEPTH = 64000; - localparam TOTAL_PROBE_WIDTH = 2; - - reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0]; - reg [$clog2(SAMPLE_DEPTH)-1:0] addr; - reg [TOTAL_PROBE_WIDTH-1:0] sample; - - assign done = (addr >= SAMPLE_DEPTH); - - initial begin - $readmemb(MEM_FILE, capture, 0, SAMPLE_DEPTH-1); - addr = 0; - end - - always @(posedge clk) begin - if (enable && !done) begin - addr = addr + 1; - sample = capture[addr]; - {ps2_data, ps2_clk} = sample; - end - end -endmodule \ No newline at end of file diff --git a/examples/nexys_a7/ps2_logic_analyzer/sim/playback_tb.sv b/examples/nexys_a7/ps2_logic_analyzer/sim/playback_tb.sv deleted file mode 100644 index 7116fb8..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/sim/playback_tb.sv +++ /dev/null @@ -1,80 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module ps2_decoder( - input wire clk, - - input wire ps2_clk, - input wire ps2_data, - - output logic [7:0] data - ); - - reg prev_clk; - reg [10:0] buffer = 0; - reg [3:0] counter = 0; - - always @(posedge clk) begin - prev_clk <= ps2_clk; - - if (!prev_clk && ps2_clk) begin - buffer <= {buffer[9:0], ps2_data}; - counter <= counter + 1; - end - - if (counter == 11) begin - if (!buffer[10] && buffer[0]) begin - counter <= 0; - data <= {buffer[2], buffer[3], buffer[4], buffer[5], buffer[6], buffer[7], buffer[8], buffer[9]}; - end - end - - end - -endmodule - -module playback_tb(); - logic clk; - - always begin - #5; - clk = !clk; - end - - logic ps2_clk; - logic ps2_data; - - my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst ( - .clk(clk), - .enable(1'b1), - - .ps2_clk(ps2_clk), - .ps2_data(ps2_data)); - - logic [7:0] data; - - ps2_decoder decoder( - .clk(clk), - - .ps2_clk(ps2_clk), - .ps2_data(ps2_data), - - .data(data) - ); - - initial begin - clk = 0; - $dumpfile("playback_tb.vcd"); - $dumpvars(0, playback_tb); - - #(450000*5); - $finish(); - end - -endmodule - - - - - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/ps2_logic_analyzer/src/top_level.sv b/examples/nexys_a7/ps2_logic_analyzer/src/top_level.sv deleted file mode 100644 index b54ef17..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/src/top_level.sv +++ /dev/null @@ -1,25 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -module top_level ( - input wire clk, - - input wire ps2_clk, - input wire ps2_data, - - input wire uart_txd_in, - output logic uart_rxd_out - ); - - manta manta_inst ( - .clk(clk), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .ps2_clk(ps2_clk), - .ps2_data(ps2_data)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/ps2_logic_analyzer/xdc/top_level.xdc b/examples/nexys_a7/ps2_logic_analyzer/xdc/top_level.xdc deleted file mode 100644 index 81c1998..0000000 --- a/examples/nexys_a7/ps2_logic_analyzer/xdc/top_level.xdc +++ /dev/null @@ -1,254 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal - uncomment _both_ of these lines to create clk_100mhz -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - - diff --git a/examples/nexys_a7/video_sprite_ether/img/buff_doge.png b/examples/nexys_a7/video_sprite_ether/img/buff_doge.png deleted file mode 100644 index d504d022b1fbe9896a43e008ec41ffbad202d00d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 69692 zcmeFZWl&t*wl>;0!5at=v}r5^clX9!gS$2E?(PH$Zb5@XaMuJva1HJf++8m3yZ6~= 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sys.argv[1] - image_in = Image.open(input_fname) - image_in = image_in.convert('RGB') - - # Resize the image - image_in = image_in.resize((128, 128)) - image_out = image_in.copy() - w, h = image_in.size - - # Take input image and divide each color channel's value by 16 - for y in range(h): - for x in range(w): - r, g, b = image_in.getpixel((x, y)) - image_out.putpixel((x,y), (r//16, g//16, b//16)) - - - # Save the image itself - pixels = [] - for y in range(h): - for x in range(w): - (r, g, b) = image_out.getpixel((x,y)) - color = (r*16*16) + (g*16) + (b) - pixels.append(color) - - from manta import Manta - m = Manta('manta.yaml') - - addrs = list(range(len(pixels))) - m.image_mem.write(addrs, pixels) \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_uart/src/clk_gen.v b/examples/nexys_a7/video_sprite_uart/src/clk_gen.v deleted file mode 100644 index 91d4265..0000000 --- a/examples/nexys_a7/video_sprite_uart/src/clk_gen.v +++ /dev/null @@ -1,207 +0,0 @@ - -// file: clk_gen.v -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_50mhz__50.00000______0.000______50.0______150.541_____99.281 -// clk_65mhz__65.00000______0.000______50.0______142.278_____99.281 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_________100.000____________0.010 - -`timescale 1ps/1ps - -module clk_gen - - (// Clock in ports - // Clock out ports - output clk_50mhz, - output clk_65mhz, - input clk_100mhz - ); - // Input buffering - //------------------------------------ -wire clk_100mhz_clk_gen; -wire clk_in2_clk_gen; - IBUF clkin1_ibufg - (.O (clk_100mhz_clk_gen), - .I (clk_100mhz)); - - - - - // Clocking PRIMITIVE - //------------------------------------ - - // Instantiation of the MMCM PRIMITIVE - // * Unused inputs are tied off - // * Unused outputs are labeled unused - - wire clk_50mhz_clk_gen; - wire clk_65mhz_clk_gen; - wire clk_out3_clk_gen; - wire clk_out4_clk_gen; - wire clk_out5_clk_gen; - wire clk_out6_clk_gen; - wire clk_out7_clk_gen; - - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_int; - wire clkfbout_clk_gen; - wire clkfbout_buf_clk_gen; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (9.750), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (19.500), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (15), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (10.000)) - mmcm_adv_inst - // Output clocks - ( - .CLKFBOUT (clkfbout_clk_gen), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (clk_50mhz_clk_gen), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clk_65mhz_clk_gen), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout_buf_clk_gen), - .CLKIN1 (clk_100mhz_clk_gen), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (1'b0)); - -// Clock Monitor clock assigning -//-------------------------------------- - // Output buffering - //----------------------------------- - - BUFG clkf_buf - (.O (clkfbout_buf_clk_gen), - .I (clkfbout_clk_gen)); - - - - - - - BUFG clkout1_buf - (.O (clk_50mhz), - .I (clk_50mhz_clk_gen)); - - - BUFG clkout2_buf - (.O (clk_65mhz), - .I (clk_65mhz_clk_gen)); - - - -endmodule diff --git a/examples/nexys_a7/video_sprite_uart/src/top_level.sv b/examples/nexys_a7/video_sprite_uart/src/top_level.sv deleted file mode 100644 index 01645fd..0000000 --- a/examples/nexys_a7/video_sprite_uart/src/top_level.sv +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module top_level ( - input wire clk_100mhz, - - input wire uart_txd_in, - output logic uart_rxd_out, - - output logic [3:0] vga_r, vga_g, vga_b, - output logic vga_hs, vga_vs); - - // Clock generation - logic clk_65mhz; - - clk_gen gen( - .clk_100mhz(clk_100mhz), - .clk_50mhz(), - .clk_65mhz(clk_65mhz)); - - // VGA signals - logic [10:0] hcount; - logic [9:0] vcount; - logic hsync, vsync, blank; - - vga vga_gen( - .pixel_clk_in(clk_65mhz), - .hcount_out(hcount), - .vcount_out(vcount), - .hsync_out(hsync), - .vsync_out(vsync), - .blank_out(blank)); - - // VGA Pipelining - reg[1:0][10:0] hcount_pipe; - reg[1:0][10:0] vcount_pipe; - reg[1:0] hsync_pipe; - reg[1:0] vsync_pipe; - reg[1:0] blank_pipe; - - always_ff @(posedge clk_65mhz)begin - hcount_pipe[0] <= hcount; - vcount_pipe[0] <= vcount; - hsync_pipe[0] <= hsync; - vsync_pipe[0] <= vsync; - blank_pipe[0] <= blank; - for (int i=1; i<2; i = i+1)begin - hcount_pipe[i] <= hcount_pipe[i-1]; - vcount_pipe[i] <= vcount_pipe[i-1]; - hsync_pipe[i] <= hsync_pipe[i-1]; - vsync_pipe[i] <= vsync_pipe[i-1]; - blank_pipe[i] <= blank_pipe[i-1]; - end - end - - localparam WIDTH = 128; - localparam HEIGHT = 128; - - localparam X = 0; - localparam Y = 0; - - // calculate rom address - logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr; - assign image_addr = (hcount - X) + ((vcount - Y) * WIDTH); - - logic in_sprite; - assign in_sprite = ((hcount_pipe[1] >= X && hcount_pipe[1] < (X + WIDTH)) && - (vcount_pipe[1] >= Y && vcount_pipe[1] < (Y + HEIGHT))); - - manta manta_inst ( - .clk(clk_65mhz), - - .rx(uart_txd_in), - .tx(uart_rxd_out), - - .image_mem_clk(clk_65mhz), - .image_mem_addr(image_addr), - .image_mem_din(), - .image_mem_dout(sprite_color), - .image_mem_we(1'b0)); - - logic [11:0] sprite_color; - logic [11:0] color; - assign color = in_sprite ? sprite_color : 12'h0; - - // the following lines are required for the Nexys4 VGA circuit - do not change - assign vga_r = ~blank_pipe[1] ? color[11:8]: 0; - assign vga_g = ~blank_pipe[1] ? color[7:4] : 0; - assign vga_b = ~blank_pipe[1] ? color[3:0] : 0; - - assign vga_hs = ~hsync_pipe[1]; - assign vga_vs = ~vsync_pipe[1]; - - -endmodule -`default_nettype wire diff --git a/examples/nexys_a7/video_sprite_uart/src/vga.sv b/examples/nexys_a7/video_sprite_uart/src/vga.sv deleted file mode 100644 index 3fa787f..0000000 --- a/examples/nexys_a7/video_sprite_uart/src/vga.sv +++ /dev/null @@ -1,68 +0,0 @@ - -/* vga: Generate VGA display signals (1024 x 768 @ 60Hz) - * - * ---- HORIZONTAL ----- ------VERTICAL ----- - * Active Active - * Freq Video FP Sync BP Video FP Sync BP - * 640x480, 60Hz 25.175 640 16 96 48 480 11 2 31 - * 800x600, 60Hz 40.000 800 40 128 88 600 1 4 23 - * 1024x768, 60Hz 65.000 1024 24 136 160 768 3 6 29 - * 1280x1024, 60Hz 108.00 1280 48 112 248 768 1 3 38 - * 1280x720p 60Hz 75.25 1280 72 80 216 720 3 5 30 - * 1920x1080 60Hz 148.5 1920 88 44 148 1080 4 5 36 - * - * change the clock frequency, front porches, sync's, and back porches to create - * other screen resolutions - */ - -module vga( - input wire pixel_clk_in, - output logic [10:0] hcount_out, // pixel number on current line - output logic [9:0] vcount_out, // line number - output logic vsync_out, hsync_out, - output logic blank_out); - - parameter DISPLAY_WIDTH = 1024; // display width - parameter DISPLAY_HEIGHT = 768; // number of lines - - parameter H_FP = 24; // horizontal front porch - parameter H_SYNC_PULSE = 136; // horizontal sync - parameter H_BP = 160; // horizontal back porch - - parameter V_FP = 3; // vertical front porch - parameter V_SYNC_PULSE = 6; // vertical sync - parameter V_BP = 29; // vertical back porch - - // horizontal: 1344 pixels total - // display 1024 pixels per line - logic hblank,vblank; - logic hsyncon,hsyncoff,hreset,hblankon; - assign hblankon = (hcount_out == (DISPLAY_WIDTH -1)); - assign hsyncon = (hcount_out == (DISPLAY_WIDTH + H_FP - 1)); //1047 - assign hsyncoff = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE - 1)); // 1183 - assign hreset = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE + H_BP - 1)); //1343 - - // vertical: 806 lines total - // display 768 lines - logic vsyncon,vsyncoff,vreset,vblankon; - assign vblankon = hreset & (vcount_out == (DISPLAY_HEIGHT - 1)); // 767 - assign vsyncon = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP - 1)); // 771 - assign vsyncoff = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE - 1)); // 777 - assign vreset = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE + V_BP - 1)); // 805 - - // sync and blanking - logic next_hblank,next_vblank; - assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank; - assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank; - always_ff @(posedge pixel_clk_in) begin - hcount_out <= hreset ? 0 : hcount_out + 1; - hblank <= next_hblank; - hsync_out <= hsyncon ? 0 : hsyncoff ? 1 : hsync_out; // active low - - vcount_out <= hreset ? (vreset ? 0 : vcount_out + 1) : vcount_out; - vblank <= next_vblank; - vsync_out <= vsyncon ? 0 : vsyncoff ? 1 : vsync_out; // active low - - blank_out <= next_vblank | (next_hblank & ~hreset); - end -endmodule \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc b/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc deleted file mode 100644 index 817beb0..0000000 --- a/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc +++ /dev/null @@ -1,253 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; - - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] - -set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] - -set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file diff --git a/pyproject.toml b/pyproject.toml index 949089d..8e9b9e9 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,12 +1,13 @@ [project] -name = "mantaray" -version = "0.0.5" +name = "manta" +version = "0.1.0" authors = [ { name="Fischer Moseley", email="fischerm@mit.edu" }, ] description = "An In-Situ Debugging Tool for Programmable Hardware" readme = "README.md" dependencies = [ + "amaranth[builtin-yosys]@git+https://github.com/amaranth-lang/amaranth", "PyYAML", "pyserial", "pyvcd", @@ -15,6 +16,14 @@ dependencies = [ requires-python = ">=3.7" +[project.optional-dependencies] +dev = [ + "pytest", + "black", + "mkdocs-material", + "amaranth_boards@git+https://github.com/amaranth-lang/amaranth-boards" +] + [project.urls] "Homepage" = "https://github.com/fischermoseley/manta" @@ -24,9 +33,6 @@ manta = "manta:main" [tool.setuptools.packages.find] where = ["src"] -[tool.setuptools.package-data] -manta = ["**/*.v"] - [build-system] requires = ["setuptools"] build-backend = "setuptools.build_meta" \ No newline at end of file diff --git a/src/manta/__init__.py b/src/manta/__init__.py index 587e4d8..60b9f60 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -1,385 +1,5 @@ -# Internal Dependencies -from .utils import * -from .la_core import * -from .io_core import * -from .block_mem_core import * - -# External Dependencies -from sys import argv -import os -from datetime import datetime -from pkg_resources import get_distribution - -class Manta: - def __init__(self, config_filepath): - config = self.read_config_file(config_filepath) - - # set interface - if "uart" in config: - from .uart_iface import UARTInterface - self.interface = UARTInterface(config["uart"]) - - elif "ethernet" in config: - from .ether_iface import EthernetInterface - self.interface = EthernetInterface(config["ethernet"]) - - else: - raise ValueError("Unrecognized interface specified.") - - # check that cores were provided - assert "cores" in config, "No cores found." - assert len(config["cores"]) > 0, "Must specify at least one core." - - # add cores to self - base_addr = 0 - self.cores = [] - for i, core_name in enumerate(config["cores"]): - core = config["cores"][core_name] - - # make sure a type was specified for this core - assert "type" in core, f"No type specified for core {core_name}." - - # add the core to ourself - if core["type"] == "logic_analyzer": - new_core = LogicAnalyzerCore(core, core_name, base_addr, self.interface) - - elif core["type"] == "io": - new_core = IOCore(core, core_name, base_addr, self.interface) - - elif core["type"] == "block_memory": - new_core = BlockMemoryCore(core, core_name, base_addr, self.interface) - - else: - raise ValueError(f"Unrecognized core type specified for {core_name}.") - - # make sure we're not out of address space - assert new_core.max_addr < (2**16)-1, f"Ran out of address space to allocate to core {core_name}." - - # make the next core's base address start one address after the previous one's - base_addr = new_core.max_addr + 1 - - # add friendly name, so users can do Manta.my_logic_analyzer.read() for example - setattr(self, core_name, new_core) - self.cores.append(new_core) - - def read_config_file(self, path): - """Take path to configuration file, and retun the configuration as a python list/dict object.""" - extension = path.split(".")[-1] - - if "json" in extension: - with open(path, "r") as f: - import json - - config = json.load(f) - - elif "yaml" in extension or "yml" in extension: - with open(path, "r") as f: - import yaml - - config = yaml.safe_load(f) - - else: - raise ValueError("Unable to recognize configuration file extension.") - - return config - - def gen_connections(self): - # generates hdl for registers that connect two modules together - - # make pairwise cores - core_pairs = [(self.cores[i - 1], self.cores[i]) for i in range(1, len(self.cores))] - - conns = [] - for core_pair in core_pairs: - src = core_pair[0].name - dst = core_pair[1].name - - hdl = f"reg [15:0] {src}_{dst}_addr;\n" - hdl += f"reg [15:0] {src}_{dst}_data;\n" - hdl += f"reg {src}_{dst}_rw;\n" - hdl += f"reg {src}_{dst}_valid;\n" - conns.append(hdl) - - return conns - - def gen_instances(self): - # generates hdl for modules that need to be connected together - - insts = [] - for i, core in enumerate(self.cores): - # should probably check if core is LogicAnalyzerCore or IOCore - - hdl = core.hdl_inst() - - # connect input - if (i == 0): - src_name = "brx" - - else: - src_name = self.cores[i-1].name - - hdl = hdl.replace(".addr_i()", f".addr_i({src_name}_{core.name}_addr)") - hdl = hdl.replace(".data_i()", f".data_i({src_name}_{core.name}_data)") - hdl = hdl.replace(".rw_i()", f".rw_i({src_name}_{core.name}_rw)") - hdl = hdl.replace(".valid_i()", f".valid_i({src_name}_{core.name}_valid)") - - - - # connect output - if (i < len(self.cores)-1): - dst_name = self.cores[i+1].name - hdl = hdl.replace(".addr_o()", f".addr_o({core.name}_{dst_name}_addr)") - - else: - dst_name = "btx" - - hdl = hdl.replace(".data_o()", f".data_o({core.name}_{dst_name}_data)") - hdl = hdl.replace(".rw_o()", f".rw_o({core.name}_{dst_name}_rw)") - hdl = hdl.replace(".valid_o()", f".valid_o({core.name}_{dst_name}_valid)") - - insts.append(hdl) - - return insts - - def gen_core_chain(self): - insts = self.gen_instances() - conns = self.gen_connections() - core_chain = [] - for i, inst in enumerate(insts): - core_chain.append(inst) - - if (i != len(insts)-1): - core_chain.append(conns[i]) - - return '\n'.join(core_chain) - - def gen_example_inst_ports(self): - # this is a C-style block comment that contains an instantiation - # of the configured manta instance - the idea is that a user - # can copy-paste that into their design instead of trying to spot - # the difference between their code and the autogenerated code. - - # hopefully this saves time! - - - # this turns a list like ['input wire foo', 'output reg bar'] into - # a nice string like ".foo(foo),\n .bar(bar)" - interface_ports = self.interface.hdl_top_level_ports() - interface_ports = [port.split(',')[0] for port in interface_ports] - interface_ports = [port.split(' ')[-1] for port in interface_ports] - interface_ports = [f".{port}({port}),\n" for port in interface_ports] - interface_ports = "".join(interface_ports) - - core_chain_ports = [] - for core in self.cores: - ports = [port.split(',')[0] for port in core.hdl_top_level_ports()] - ports = [port.split(' ')[-1] for port in ports] - ports = [f".{port}({port}), \n" for port in ports] - ports = "".join(ports) - ports = "\n" + ports - core_chain_ports.append(ports) - - core_chain_ports = "\n".join(core_chain_ports) - - ports = interface_ports + core_chain_ports - - # remove trailing comma - ports = ports.rstrip() - if ports[-1] == ",": - ports = ports[:-1] - - return ports - - def gen_top_level_ports(self): - # get all the top level connections for each module. - - interface_ports = self.interface.hdl_top_level_ports() - interface_ports = [f"{port},\n" for port in interface_ports] - interface_ports = "".join(interface_ports) + "\n" - - core_chain_ports = [] - for core in self.cores: - ports = [f"{port},\n" for port in core.hdl_top_level_ports()] - ports = "".join(ports) - core_chain_ports.append(ports) - - core_chain_ports = "\n".join(core_chain_ports) - - ports = interface_ports + core_chain_ports - - # remove trailing comma - ports = ports.rstrip() - if ports[-1] == ",": - ports = ports[:-1] - - return ports - - def gen_interface_rx(self): - # instantiate interface_rx, substitute in register names - interface_rx_inst = self.interface.rx_hdl_inst() - - interface_rx_inst = interface_rx_inst.replace("addr_o()", f"addr_o(brx_{self.cores[0].name}_addr)") - interface_rx_inst = interface_rx_inst.replace("data_o()", f"data_o(brx_{self.cores[0].name}_data)") - interface_rx_inst = interface_rx_inst.replace("rw_o()", f"rw_o(brx_{self.cores[0].name}_rw)") - interface_rx_inst = interface_rx_inst.replace("valid_o()", f"valid_o(brx_{self.cores[0].name}_valid)") - - # connect interface_rx to core_chain - interface_rx_conn= f""" -reg [15:0] brx_{self.cores[0].name}_addr; -reg [15:0] brx_{self.cores[0].name}_data; -reg brx_{self.cores[0].name}_rw; -reg brx_{self.cores[0].name}_valid;\n""" - - return interface_rx_inst + interface_rx_conn - - def gen_interface_tx(self): - - # connect core_chain to interface_tx - interface_tx_conn = f""" -reg [15:0] {self.cores[-1].name}_btx_data; -reg {self.cores[-1].name}_btx_rw; -reg {self.cores[-1].name}_btx_valid;\n""" - - # instantiate interface_tx, substitute in register names - interface_tx_inst = self.interface.tx_hdl_inst() - - interface_tx_inst = interface_tx_inst.replace("addr_i()", f"addr_i({self.cores[-1].name}_btx_addr)") - interface_tx_inst = interface_tx_inst.replace("data_i()", f"data_i({self.cores[-1].name}_btx_data)") - interface_tx_inst = interface_tx_inst.replace("rw_i()", f"rw_i({self.cores[-1].name}_btx_rw)") - interface_tx_inst = interface_tx_inst.replace("valid_i()", f"valid_i({self.cores[-1].name}_btx_valid)") - - return interface_tx_conn + interface_tx_inst - - def gen_module_defs(self): - # aggregate module definitions and remove duplicates - module_defs_with_dups = [self.interface.rx_hdl_def()] + [core.hdl_def() for core in self.cores] + [self.interface.tx_hdl_def()] - module_defs = [] - module_defs = [m_def for m_def in module_defs_with_dups if m_def not in module_defs] - module_defs = [m_def.strip() for m_def in module_defs] - return '\n\n'.join(module_defs) - - def generate_hdl(self, output_filepath): - manta = VerilogManipulator("manta_def_tmpl.v") - - version = "v" + get_distribution('mantaray').version - manta.sub(version, "/* VERSION */") - - timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S") - manta.sub(timestamp, "/* TIMESTAMP */") - - user = os.environ.get("USER", os.environ.get("USERNAME")) - manta.sub(user, "/* USER */") - - ex_inst_ports = self.gen_example_inst_ports() - manta.sub(ex_inst_ports, "/* EX_INST_PORTS */") - - top_level_ports = self.gen_top_level_ports() - manta.sub(top_level_ports, "/* TOP_LEVEL_PORTS */") - - interface_rx = self.gen_interface_rx() - manta.sub(interface_rx, "/* INTERFACE_RX */") - - core_chain = self.gen_core_chain() - manta.sub(core_chain, "/* CORE_CHAIN */") - - interface_tx = self.gen_interface_tx() - manta.sub(interface_tx, "/* INTERFACE_TX */") - - module_defs = self.gen_module_defs() - manta.sub(module_defs, "/* MODULE_DEFS */") - - manta.hdl = "`timescale 1ns/1ps\n" + manta.hdl - manta.hdl = "`default_nettype none\n"+ manta.hdl - manta.hdl = manta.hdl + "\n`default_nettype wire" - - return manta.get_hdl() - -def main(): - # print help menu if no args passed or help menu requested - - if len(argv) == 1 or argv[1] == "help" or argv[1] == "ray" or argv[1] == "bae": - version = "v" + get_distribution('mantaray').version - print( - f""" -\033[96m (\.-./) -\033[96m / \\ -\033[96m .' : '. -\033[96m _.-'` ' `'-._ \033[34;49;1m | \033[34;49;1m Manta {version} \033[00m -\033[96m .-' : '-. \033[34;49;1m | \033[34;49;3m An In-Situ Debugging Tool for Programmable Hardware \033[00m -\033[96m ,'_.._ . _.._', \033[34;49;1m | \033[34;49m https://github.com/fischermoseley/manta \033[00m -\033[96m '` `'-. ' .-'` -\033[96m '. : .' \033[34;49;1m | \033[34;49;3m fischerm [at] mit.edu \033[00m -\033[96m \_. ._/ -\033[96m \ |^| -\033[96m | | ; -\033[96m \\'.___.' / -\033[96m '-....-' \033[00m - -Supported commands: - gen [config_file] [verilog_file] generate a verilog file specifying the Manta module from a given configuration file, and save to the provided path - capture [config_file] [LA_core_name] [vcd_file] [mem_file] start a capture on the specified core, and save the results to a .mem or .vcd file at the provided path(s) - playback [config file] [LA_core_name] [verilog_file] generate a verilog module that plays back a capture from a given logic analyzer core, and save to the provided path - ports list all available serial ports - help, ray display this splash screen (hehe...splash screen) -""" - ) - - # list available serial ports - elif argv[1] == "ports": - import serial.tools.list_ports - for port in serial.tools.list_ports.comports(): - print(port) - - # sometimes macOS will enumerate non-serial devices as serial ports, - # in which case the PID/VID/serial/location/etc are all None - pid = f"0x{port.vid:04X}" if port.pid is not None else "None" - vid = f"0x{port.vid:04X}" if port.vid is not None else "None" - - print(f" -> pid: {pid}") - print(f" -> vid: {vid}") - print(f" -> ser: {port.serial_number}") - print(f" -> loc: {port.location}") - print(f" -> mftr: {port.manufacturer}") - print(f" -> prod: {port.product}") - print(f" -> desc: {port.description}\n") - - # generate the specified configuration - elif argv[1] == "gen": - assert len(argv) == 4, "Wrong number of arguments, run 'manta help' for proper usage." - - m = Manta(argv[2]) - hdl = m.generate_hdl(argv[3]) - with open(argv[3], "w") as f: - f.write(hdl) - - # run the specified core - elif argv[1] == "capture": - assert len(argv) >= 5, "Wrong number of arguments, run 'manta help' for proper usage." - - m = Manta(argv[2]) - la = getattr(m, argv[3]) - data = la.capture() - - for path in argv[4:]: - if ".vcd" in path: - la.export_vcd(data, path) - - elif ".mem" in path: - la.export_mem(data, path) - - else: - print(f"Warning: Unknown output file format for {path}, skipping...") - - elif argv[1] == "playback": - assert len(argv) == 5, "Wrong number of arguments, run 'manta help' for proper usage." - - m = Manta(argv[2]) - la = getattr(m, argv[3]) - la.export_playback_module(argv[4]) - - else: - print("Option not recognized, run 'manta help' for proper usage.") - +from .manta import Manta +from .cli import main if __name__ == "__main__": main() diff --git a/src/manta/__main__.py b/src/manta/__main__.py index b23d9a5..4e28416 100644 --- a/src/manta/__main__.py +++ b/src/manta/__main__.py @@ -1,3 +1,3 @@ -import manta +from .cli import main -manta.main() +main() diff --git a/src/manta/block_mem_core/__init__.py b/src/manta/block_mem_core/__init__.py deleted file mode 100644 index dbe841c..0000000 --- a/src/manta/block_mem_core/__init__.py +++ /dev/null @@ -1,77 +0,0 @@ -from ..utils import * - -from math import ceil, log2 - -class BlockMemoryCore: - def __init__(self, config, name, base_addr, interface): - self.name = name - self.base_addr = base_addr - self.interface = interface - - # Warn if unrecognized options have been given - for option in config: - if option not in ["type", "depth", "width", "expose_port"]: - print(f"Warning: Ignoring unrecognized option '{option}' in Block Memory core '{self.name}'") - - # Determine if we expose the BRAM's second port to the top of the module - if "expose_port" in config: - assert isinstance(config["expose_port"], bool), "Configuring BRAM exposure must be done with a boolean." - self.expose_port = config["expose_port"] - - else: - self.expose_port = True - - # Get depth - assert "depth" in config, "Depth not specified for Block Memory core." - assert config["depth"] > 0, "Block Memory core must have positive depth." - assert isinstance(config["depth"], int), "Block Memory core must have integer depth." - self.depth = config["depth"] - - # Get width - assert "width" in config, "Width not specified for Block Memory core." - assert config["width"] > 0, "Block Memory core must have positive width." - assert isinstance(config["width"], int), "Block Memory core must have integer width." - self.width = config["width"] - - self.addr_width = ceil(log2(self.depth)) - self.n_brams = ceil(self.width / 16) - self.max_addr = self.base_addr + (self.depth * self.n_brams) - - def hdl_inst(self): - inst = VerilogManipulator("block_mem_core/block_memory_inst_tmpl.v") - inst.sub(self.name, "/* INST_NAME */") - inst.sub(self.depth, "/* DEPTH */") - inst.sub(self.width, "/* WIDTH */") - return inst.get_hdl() - - def hdl_def(self): - block_memory = VerilogManipulator("block_mem_core/block_memory.v").get_hdl() - dual_port_bram = VerilogManipulator("block_mem_core/dual_port_bram.v").get_hdl() - return block_memory + "\n" + dual_port_bram - - def hdl_top_level_ports(self): - if not self.expose_port: - return "" - - tlp = [] - tlp.append(f"input wire {self.name}_clk") - tlp.append(f"input wire [{self.addr_width-1}:0] {self.name}_addr") - tlp.append(f"input wire [{self.width-1}:0] {self.name}_din") - tlp.append(f"output reg [{self.width-1}:0] {self.name}_dout") - tlp.append(f"input wire {self.name}_we") - return tlp - - def get_physical_addr(self, addr): - if isinstance(addr, int): - return addr + self.base_addr - - elif isinstance(addr, list): - return [a + self.base_addr for a in addr] - - raise ValueError("Read address must be integer or list of integers.") - - def read(self, addr): - return self.interface.read(self.get_physical_addr(addr)) - - def write(self, addr, data): - return self.interface.write(self.get_physical_addr(addr), data) \ No newline at end of file diff --git a/src/manta/block_mem_core/block_memory.v b/src/manta/block_mem_core/block_memory.v deleted file mode 100644 index ae00f17..0000000 --- a/src/manta/block_mem_core/block_memory.v +++ /dev/null @@ -1,114 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module block_memory ( - input wire clk, - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o, - - // BRAM itself - input wire user_clk, - input wire [ADDR_WIDTH-1:0] user_addr, - input wire [WIDTH-1:0] user_din, - output reg [WIDTH-1:0] user_dout, - input wire user_we); - - parameter BASE_ADDR = 0; - parameter WIDTH = 0; - parameter DEPTH = 0; - localparam ADDR_WIDTH = $clog2(DEPTH); - - // ugly typecasting, but just computes ceil(WIDTH / 16) - localparam N_BRAMS = int'($ceil(real'(WIDTH) / 16.0)); - localparam MAX_ADDR = BASE_ADDR + (DEPTH * N_BRAMS); - - // Port A of BRAMs - reg [N_BRAMS-1:0][ADDR_WIDTH-1:0] addra = 0; - reg [N_BRAMS-1:0][15:0] dina = 0; - reg [N_BRAMS-1:0][15:0] douta; - reg [N_BRAMS-1:0] wea = 0; - - // Port B of BRAMs - reg [N_BRAMS-1:0][15:0] dinb; - reg [N_BRAMS-1:0][15:0] doutb; - assign dinb = user_din; - - // kind of a hack to part select from a 2d array that's been flattened to 1d - reg [(N_BRAMS*16)-1:0] doutb_flattened; - assign doutb_flattened = doutb; - assign user_dout = doutb_flattened[WIDTH-1:0]; - - // Pipelining - reg [2:0][15:0] addr_pipe = 0; - reg [2:0][15:0] data_pipe = 0; - reg [2:0] valid_pipe = 0; - reg [2:0] rw_pipe = 0; - - always @(posedge clk) begin - addr_pipe[0] <= addr_i; - data_pipe[0] <= data_i; - valid_pipe[0] <= valid_i; - rw_pipe[0] <= rw_i; - - addr_o <= addr_pipe[2]; - data_o <= data_pipe[2]; - valid_o <= valid_pipe[2]; - rw_o <= rw_pipe[2]; - - for(int i=1; i<3; i=i+1) begin - addr_pipe[i] <= addr_pipe[i-1]; - data_pipe[i] <= data_pipe[i-1]; - valid_pipe[i] <= valid_pipe[i-1]; - rw_pipe[i] <= rw_pipe[i-1]; - end - - // throw BRAM operations into the front of the pipeline - wea <= 0; - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= MAX_ADDR)) begin - wea[(addr_i - BASE_ADDR) % N_BRAMS] <= rw_i; - addra[(addr_i - BASE_ADDR) % N_BRAMS] <= (addr_i - BASE_ADDR) / N_BRAMS; - dina[(addr_i - BASE_ADDR) % N_BRAMS] <= data_i; - end - - // pull BRAM reads from the back of the pipeline - if( (valid_pipe[2]) && (addr_pipe[2] >= BASE_ADDR) && (addr_pipe[2] <= MAX_ADDR)) begin - data_o <= douta[(addr_pipe[2] - BASE_ADDR) % N_BRAMS]; - end - end - - // generate the BRAMs - genvar i; - generate - for(i=0; i pid: {pid}") + print(f" -> vid: {vid}") + print(f" -> ser: {port.serial_number}") + print(f" -> loc: {port.location}") + print(f" -> mftr: {port.manufacturer}") + print(f" -> prod: {port.product}") + print(f" -> desc: {port.description}\n") + + +def main(): + if len(argv) == 1: + help() + + elif argv[1] in ["help", "-h", "-help", "--help", "ray"]: + help() + + elif argv[1] == "gen": + if len(argv) != 4: + wrong_args() + gen(argv[2], argv[3]) + + elif argv[1] == "capture": + if len(argv) < 5: + wrong_args() + capture(argv[2], argv[3], argv[4]) + + elif argv[1] == "playback": + if len(argv) != 5: + wrong_args() + playback(argv[2], argv[3], argv[4]) + + elif argv[1] == "mmap": + if len(argv) != 3: + wrong_args() + mmap(argv[2]) + + elif argv[1] == "ports": + ports() + + else: + wrong_args() + + +if __name__ == "__main__": + main() diff --git a/src/manta/ether_iface/__init__.py b/src/manta/ether_iface/__init__.py deleted file mode 100644 index 042bffe..0000000 --- a/src/manta/ether_iface/__init__.py +++ /dev/null @@ -1,208 +0,0 @@ -from ..utils import * - -# Lazy and selective imports for quick builds! -from scapy.interfaces import get_if_list -from scapy.arch import get_if_hwaddr -from scapy.layers.l2 import Ether -from scapy.sendrecv import AsyncSniffer, sendp, sendpfast -from time import sleep - -from scapy.all import * - -class EthernetInterface: - def __init__(self, config): - # Warn if unrecognized options have been given - for option in config: - if option not in ["interface", "host_mac", "fpga_mac", "ethertype", "tcpreplay", "verbose"]: - print(f"Warning: Ignoring unrecognized option '{option}' in Ethernet interface.") - - # Obtain interface. - assert "interface" in config, "No interface provided for Ethernet core." - if config["interface"] not in get_if_list(): - print(f"Warning: Interface specified is not detected by the host.") - self.iface = config["interface"] - - # Obtain Host MAC address - if self.iface in get_if_list(): - self.host_mac = get_if_hwaddr(self.iface) - else: - assert "host_mac" in config, \ - "Can't automatically detect host mac address from interface, host_mac must be manually provided" - self.host_mac = config["host_mac"] - - # Obtain FPGA MAC address - # - the default address is a locally administered unicast address, - # which is an important distinction. please refer to: - # https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses - self.fpga_mac = "12:34:56:78:9A:BC" - if "fpga_mac" in config: - self.fpga_mac = config["fpga_mac"] - - # Obtain Ethertype - # - the default ethertype being used is reserved for local - # experimentation by the IEEE - and might not make it beyond - # your NIC as a result. - self.ethertype = 0x88B5 - if "ethertype" in config: - self.ethertype = int(config["ethertype"], 16) - - # Set whether we use tcpreplay for faster packet blasting - if "tcpreplay" in config: - assert isinstance(config["tcpreplay"], bool), \ - "tcpreplay configuration option must be boolean!" - - if config["tcpreplay"]: - self.send_packets = lambda p: sendpfast(p, iface=self.iface) - - else: - self.send_packets = lambda p: sendp(p, iface=self.iface, verbose=0) - - else: - self.send_packets = lambda p: sendp(p, iface=self.iface, verbose=0) - - - self.verbose = False - if "verbose" in config: - assert isinstance(config["verbose"], bool), \ - "verbose configuration option must be boolean!" - self.verbose = config["verbose"] - - def read(self, addr): - # Perform type checks, output list of addresses - if isinstance(addr, int): - addrs = [addr] - - elif isinstance(addr, list): - assert all(isinstance(a, int) for a in addr), \ - "Read addresses must be integer or list of integers." - addrs = addr - - else: - raise ValueError("Read addresses must be integer or list of integers.") - - # Prepare packets with read requests - request_pkts = [] - for a in addrs: - pkt = Ether() - pkt.src = self.host_mac - pkt.dst = self.fpga_mac - pkt.type = self.ethertype - - # one byte of rw, two bytes of address, and 44 of padding - # makes the 46 byte minimum length - msg = b'\x00' + a.to_bytes(2, 'big') + 43*b'\x00' - - pkt = pkt / msg - pkt.load = msg - request_pkts.append(pkt) - - # Start sniffer in another thread, send packets, grab responses - sniffer = AsyncSniffer(iface = self.iface, count = len(addrs), filter=f"ether src {self.fpga_mac}") - sniffer.start() - sleep(0.5) - self.send_packets(request_pkts) - sniffer.join() - response_pkts = sniffer.results - assert len(response_pkts) == len(request_pkts), "Received wrong number of packets!" - - # Get read data by pulling bytes 3 and 4 from the returned packets - # payload, and interpreting it as big endian - get_read_data = lambda x: int.from_bytes(bytes(x.payload)[3:5], 'big') - read_data = [get_read_data(pkt) for pkt in response_pkts] - - if len(read_data) == 1: - return read_data[0] - - else: - return read_data - - def write(self, addr, data): - # Perform type checks, output list of addresses - if isinstance(addr, int): - assert isinstance(data, int), \ - "Data must also be integer if address is integer." - addrs = [addr] - datas = [data] - - elif isinstance(addr, list): - assert all(isinstance(a, int) for a in addr), \ - "Write addresses must be integer or list of integers." - - assert all(isinstance(d, int) for d in data), \ - "Write data must be integer or list of integers." - - assert len(addr) == len(data), \ - "There must be equal number of write addresses and data." - - addrs = addr - datas = data - - else: - raise ValueError("Write addresses and data must be integer or list of integers.") - - # Prepare packets with write requests - request_pkts = [] - for a, d in zip(addrs, datas): - pkt = Ether() - pkt.src = self.host_mac - pkt.dst = self.fpga_mac - pkt.type = self.ethertype - - # one byte of rw, two bytes of address, two bytes of data, and 42 of padding - # makes the 46 byte minimum length - msg = b'\x01' + a.to_bytes(2, 'big') + d.to_bytes(2, 'big') + 41*b'\x00' - - pkt = pkt / msg - pkt.load = msg - request_pkts.append(pkt) - - self.send_packets(request_pkts) - - def hdl_top_level_ports(self): - return ["input wire crsdv", \ - "input wire [1:0] rxd", \ - "output reg txen", \ - "output reg [1:0] txd"] - - def rx_hdl_def(self): - tx = VerilogManipulator("ether_iface/ethernet_rx.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/mac_rx.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/ether.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/bitorder.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/firewall.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/aggregate.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/crc32.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/cksum.v").get_hdl() + "\n" - return tx - - def tx_hdl_def(self): - tx = VerilogManipulator("ether_iface/ethernet_tx.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/mac_tx.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/bitorder.v").get_hdl() + "\n" - tx += VerilogManipulator("ether_iface/crc32.v").get_hdl() + "\n" - return tx - - def rx_hdl_inst(self): - rx = VerilogManipulator("ether_iface/ethernet_rx_inst_tmpl.v") - - fpga_mac_verilog_literal = "48'h" + self.fpga_mac.replace(":", "_").upper() - rx.sub(fpga_mac_verilog_literal, "/* FPGA_MAC */") - - ethertype_verilog_literal = f"16'h{self.ethertype:02X}" - rx.sub(ethertype_verilog_literal, "/* ETHERTYPE */") - - return rx.get_hdl() - - def tx_hdl_inst(self): - tx = VerilogManipulator("ether_iface/ethernet_tx_inst_tmpl.v") - - fpga_mac_verilog_literal = "48'h" + self.fpga_mac.replace(":", "_").upper() - tx.sub(fpga_mac_verilog_literal, "/* FPGA_MAC */") - - host_mac_verilog_literal = "48'h" + self.host_mac.replace(":", "_").upper() - tx.sub(host_mac_verilog_literal, "/* HOST_MAC */") - - ethertype_verilog_literal = f"16'h{self.ethertype:02X}" - tx.sub(ethertype_verilog_literal, "/* ETHERTYPE */") - - return tx.get_hdl() \ No newline at end of file diff --git a/src/manta/ether_iface/aggregate.v b/src/manta/ether_iface/aggregate.v deleted file mode 100644 index aad4e53..0000000 --- a/src/manta/ether_iface/aggregate.v +++ /dev/null @@ -1,46 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -/* Aggregates the first 64 bits of an incoming - * Ethernet transmission (thus shedding the FCS - * and anything else extraneous) and outputs the - * first 32 bits on an AXI bus for a single cycle. - * If the packet is not at least 64 bits long, - * nothing happens - */ - -`define AGR_MAX 56 -`define AGR_SHOW 64 - -module aggregate ( - input wire clk, - input wire [1:0] axiid, - input wire axiiv, - - output reg [55:0] axiod, - output reg axiov); - - /* A quick and dirty counter. As long as this is below - * 32, we'll dump packets into the AXI output data buffer. - * Once the counter gets to AGR_MAX, we'll assert AXI valid. - * Then we'll hang until axiiv drops - */ - - reg [31:0] counter; - - assign axiov = counter == `AGR_SHOW; - - always @(posedge clk) begin: COUNTER - if (!axiiv) counter <= 32'b0; - else counter <= counter + 2; - end - - always @(posedge clk) begin: AXIOD - if (!axiiv) axiod <= 32'b0; - else if (counter < `AGR_MAX && axiiv) - axiod[`AGR_MAX - counter - 2 +: 2] <= axiid; - end - -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/bitorder.v b/src/manta/ether_iface/bitorder.v deleted file mode 100644 index e7ca283..0000000 --- a/src/manta/ether_iface/bitorder.v +++ /dev/null @@ -1,114 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`define BO_SENDA 2'b00 -`define BO_SENDB 2'b01 -`define BO_EMPTYA 2'b10 -`define BO_EMPTYB 2'b11 - -module bitorder ( - input wire clk, - - input wire axiiv, - input wire [1:0] axiid, - - output reg [1:0] axiod, - output reg axiov); - - /* Two registers to hold data coming in off the wire, - * byte by byte. This is where we'll buffer until - * we've received a byte of data, at which point - * we'll start sending out the byte in the correct - * order using one register. Meanwhile, we'll start - * receiving into the other register - dual buffers. - */ - reg [7:0] bufa = 8'b0; - reg [7:0] bufb = 8'b0; - - /* A counter. This indicates what 'stage' we're in, - * and always refers to the index we're reading into - * in the receiving buffer or sending out of in the - * sending buffer - */ - reg [2:0] countera = 3'b0; - reg [2:0] counterb = 3'b0; - - /* Which state we're in - should we be using buffer - * A to send, buffer B to send, or neither because - * we've just come out of reset? - */ - reg [1:0] state = `BO_EMPTYB; - initial axiov = 0; - initial axiod = 0; - - always @(*) begin: AXIOV - if (state == `BO_SENDA || state == `BO_SENDB) axiov = 1'b1; - else axiov = 1'b0; - end - - always @(*) begin: AXIOD - if (state == `BO_SENDA) axiod = bufa[countera +: 2]; - else if (state == `BO_SENDB) axiod = bufb[counterb +: 2]; - else axiod = 1'b0; - end - - always @(posedge clk) begin: BUFFERIN - if (axiiv) begin - case (state) - `BO_EMPTYB, `BO_SENDB: - bufa[countera +: 2] <= axiid; - `BO_EMPTYA, `BO_SENDA: - bufb[counterb +: 2] <= axiid; - endcase - end - - else if (state == `BO_EMPTYB || state == `BO_EMPTYA) begin - bufa <= 8'b0; - bufb <= 8'b0; - end - end - - always @(posedge clk) begin: STATES - case (state) - `BO_EMPTYB: begin - if (axiiv) begin - if (countera == 3'h6) - state <= `BO_SENDA; - else countera <= countera + 2; - end else countera <= 3'b0; - end - - `BO_EMPTYA: begin - if (axiiv) begin - if (counterb == 3'h6) - state <= `BO_SENDB; - else counterb <= counterb + 2; - end else counterb <= 3'b0; - end - - `BO_SENDB: begin - if (counterb == 3'h0) state <= `BO_EMPTYB; - else counterb <= counterb - 2; - - if (axiiv) begin - if (countera == 3'h6) - state <= `BO_SENDA; - else countera <= countera + 2; - end - end - - `BO_SENDA: begin - if (countera == 3'h0) state <= `BO_EMPTYA; - else countera <= countera - 2; - - if (axiiv) begin - if (counterb == 3'h6) - state <= `BO_SENDB; - else counterb <= counterb + 2; - end - end - endcase - end -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/cksum.v b/src/manta/ether_iface/cksum.v deleted file mode 100644 index a1b823b..0000000 --- a/src/manta/ether_iface/cksum.v +++ /dev/null @@ -1,80 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -/* Computes the ethernet checksum - * The following combinations of `done` and `kill` - * represent the state of the module: - * - * - done = 0, kill = 0: processing data or freshly reset - * - done = 1, kill = 0: correct ethernet checksum verified - * - done = 1, kill = 1: data valid set to zero before correct - * checksum value computed, therefore bad checksum - * - done = 0, kill = 1: never asserted - * - * the done and/or kill signals are asserted high beginning - * the cycle after input data ceases, and until new data - * is received via the AXI input - */ - -`define CK_FRESH 2'b00 -`define CK_COMPUTING 2'b01 -`define CK_DONE 2'b10 - -`define MAGIC_CHECK 32'h38_fb_22_84 - -module cksum ( - input wire clk, - input wire [1:0] axiid, - input wire axiiv, - - output reg done, - output reg kill); - - reg [31:0] crcd; - reg crcv; - - /* Decoupled logic to reset the CRC module independently - * Used to compute multiple CRCs back to back - */ - reg crcrst; - - reg [1:0] state = `CK_FRESH; - initial done = 0; - initial kill = 0; - initial crcrst = 0; - - crc32 cksum( - .clk(clk), - .rst(crcrst), - .axiiv(axiiv), - .axiid(axiid), - .axiov(crcv), - .axiod(crcd)); - - always @(posedge clk) begin: OUTPUTS - if (axiiv) begin - done <= 1'b0; - kill <= 1'b0; - crcrst <= 1'b0; - end else begin - if (state == `CK_COMPUTING && !axiiv) begin - done <= 1'b1; - crcrst <= 1'b1; - kill <= (crcd != `MAGIC_CHECK); - end - - else crcrst <= 1'b0; - end - end - - always @(posedge clk) begin: FSM - case (state) - `CK_FRESH: if (axiiv) state <= `CK_COMPUTING; - `CK_COMPUTING: if (!axiiv) state <= `CK_DONE; - `CK_DONE: if (axiiv) state <= `CK_COMPUTING; - endcase - end - -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/crc32.v b/src/manta/ether_iface/crc32.v deleted file mode 100644 index 51e4397..0000000 --- a/src/manta/ether_iface/crc32.v +++ /dev/null @@ -1,70 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`define LAGGING_SHIFT_IN (caxiod[30] ^ axiid[1]) -`define LEADING_SHIFT_IN (caxiod[31] ^ axiid[0]) -`define DOUBLED_SHIFT_IN (`LEADING_SHIFT_IN ^ `LAGGING_SHIFT_IN) - -`define LAGGING_TAPS 4, 7, 10, 16, 22, 26 -`define DOUBLED_TAPS 2, 5, 8, 11, 12, 23 -`define LEADING_TAPS 3, 6, 9, 13, 17, 24, 27 - -/* this module implements CRC32-BZIP2, with a two bit input: - * - poly 0x04C11DB7 - * - init 0xFFFFFFFF - * - NEW: XOR outputs - * - * == check: 0xfc891918 == - * - * this is the ethernet checksum!! - */ - -module crc32( - input wire clk, - input wire rst, - input wire axiiv, - input wire [1:0] axiid, - - output reg axiov, - output reg [31:0] axiod); - - reg [31:0] caxiod, saxiod; - initial caxiod = 32'hFFFF_FFFF; - integer i; - - assign axiov = 1; - assign axiod = ~caxiod; - - always @(*) begin - for (i = 0; i < 32; i = i + 1) begin - case (i) - 0: saxiod[i] = `LAGGING_SHIFT_IN; - 1: saxiod[i] = `DOUBLED_SHIFT_IN; - - `LAGGING_TAPS: - saxiod[i] = caxiod[i - 2] ^ `LAGGING_SHIFT_IN; - `DOUBLED_TAPS: - saxiod[i] = caxiod[i - 2] ^ `DOUBLED_SHIFT_IN; - `LEADING_TAPS: - saxiod[i] = caxiod[i - 2] ^ `LEADING_SHIFT_IN; - - default: saxiod[i] = caxiod[i - 2]; - endcase - end - end - - always @(posedge clk) begin - if (rst) caxiod <= 32'hFFFF_FFFF; - - /* our output validity hinges on whether - * we are calculating anything or not - * on this clock cycle. if there is no - * valid input for us, don't do a shift - * this cycle - */ - else caxiod <= (axiiv) ? saxiod : caxiod; - end - -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/ether.v b/src/manta/ether_iface/ether.v deleted file mode 100644 index 56ad986..0000000 --- a/src/manta/ether_iface/ether.v +++ /dev/null @@ -1,77 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`define EF_IDLE 3'b000 -`define EF_PREAM 3'b001 -`define EF_DATA 3'b011 -`define EF_BAD 3'b101 - -`define PREAM_BITS 64 -`define PREAM_SIZE (`PREAM_BITS / 2) - -`define PREAM_FIRST 2'b00 -`define PREAM_EXPECT 2'b01 -`define PREAM_LAST 2'b11 -`define PREAM_BAD 2'b10 - -module ether ( - input wire clk, - input wire [1:0] rxd, - input wire crsdv, - - output reg axiov, - output reg [1:0] axiod); - - reg [4:0] count; - reg [2:0] state; - - reg [1:0] preamex; - reg preamok, start; - - always @(*) begin: PREAM - if (count == `PREAM_SIZE - 1) preamex = `PREAM_LAST; - else preamex = `PREAM_EXPECT; - - preamok = crsdv && rxd == preamex; - end - - always @(*) start = crsdv && rxd != `PREAM_FIRST; - - always @(posedge clk) begin: COUNT - if (state == `EF_PREAM) count <= count + 1; - else if (state == `EF_IDLE && start) count <= count + 1; - else count <= 0; - end - - initial begin - axiod = 2'b0; - axiov = 1'b0; - state = 3'b0; - end - - always @(posedge clk) begin: FSM - case (state) - `EF_BAD: if (!crsdv) state <= `EF_IDLE; - `EF_IDLE: if (start) state <= `EF_PREAM; - - `EF_PREAM: begin - if (!preamok || !crsdv) state <= `EF_BAD; - else if (count == `PREAM_SIZE - 1) - state <= `EF_DATA; - end - - `EF_DATA: begin - if (crsdv) begin - axiov <= 1'b1; - axiod <= rxd; - end else begin - axiov <= 1'b0; - axiod <= 2'b0; - state <= `EF_IDLE; - end - end - endcase - end -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/ethernet_rx.v b/src/manta/ether_iface/ethernet_rx.v deleted file mode 100644 index ba36ec7..0000000 --- a/src/manta/ether_iface/ethernet_rx.v +++ /dev/null @@ -1,41 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module ethernet_rx ( - input wire clk, - - input wire crsdv, - input wire [1:0] rxd, - - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o - ); - - parameter FPGA_MAC = 0; - parameter ETHERTYPE = 0; - - reg [55:0] payload; - reg valid; - - mac_rx #( - .FPGA_MAC(FPGA_MAC), - .ETHERTYPE(ETHERTYPE) - ) mrx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .payload(payload), - .valid(valid)); - - assign rw_o = (payload[39:32] == 8'd1); - assign addr_o = payload[31:16]; - assign data_o = payload[15:0]; - assign valid_o = valid && ( payload[39:32] == 8'd0 || payload[39:32] == 8'd1) && (payload[55:40] == 16'h88B5); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/ether_iface/ethernet_rx_inst_tmpl.v b/src/manta/ether_iface/ethernet_rx_inst_tmpl.v deleted file mode 100644 index 7eae02b..0000000 --- a/src/manta/ether_iface/ethernet_rx_inst_tmpl.v +++ /dev/null @@ -1,13 +0,0 @@ -ethernet_rx #( - .FPGA_MAC(/* FPGA_MAC */), - .ETHERTYPE(/* ETHERTYPE */) -) erx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .addr_o(), - .data_o(), - .rw_o(), - .valid_o()); \ No newline at end of file diff --git a/src/manta/ether_iface/ethernet_tx.v b/src/manta/ether_iface/ethernet_tx.v deleted file mode 100644 index 318b3ba..0000000 --- a/src/manta/ether_iface/ethernet_tx.v +++ /dev/null @@ -1,40 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module ethernet_tx ( - input wire clk, - - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - output reg txen, - output reg [1:0] txd - ); - - parameter FPGA_MAC = 0; - parameter HOST_MAC = 0; - parameter ETHERTYPE = 0; - - reg [15:0] data_buf = 0; - - always @(posedge clk) - if(~rw_i && valid_i) data_buf <= data_i; - - mac_tx #( - .SRC_MAC(FPGA_MAC), - .DST_MAC(HOST_MAC), - .ETHERTYPE(ETHERTYPE), - .PAYLOAD_LENGTH_BYTES(5) - ) mtx ( - .clk(clk), - - .payload({24'd0, data_buf}), - .start(~rw_i && valid_i), - - .txen(txen), - .txd(txd)); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/ether_iface/ethernet_tx_inst_tmpl.v b/src/manta/ether_iface/ethernet_tx_inst_tmpl.v deleted file mode 100644 index 6082910..0000000 --- a/src/manta/ether_iface/ethernet_tx_inst_tmpl.v +++ /dev/null @@ -1,13 +0,0 @@ -ethernet_tx #( - .FPGA_MAC(/* FPGA_MAC */), - .HOST_MAC(/* HOST_MAC */), - .ETHERTYPE(/* ETHERTYPE */) -) etx ( - .clk(clk), - - .data_i(), - .rw_i(), - .valid_i(), - - .txen(txen), - .txd(txd)); \ No newline at end of file diff --git a/src/manta/ether_iface/firewall.v b/src/manta/ether_iface/firewall.v deleted file mode 100644 index 611e310..0000000 --- a/src/manta/ether_iface/firewall.v +++ /dev/null @@ -1,80 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`define FW_DESTSTART 0 -`define FW_DESTEND (`FW_DESTSTART + 48) - -`define FW_DATASTART (48 + 48) - -module firewall ( - input wire clk, - input wire axiiv, - input wire [1:0] axiid, - - output reg axiov, - output reg [1:0] axiod); - - parameter ETHERTYPE = 0; - parameter FPGA_MAC = 0; - - /* Buffers to hold our MAC address in the reverse order, - * to make comparison easier than it otherwise would be - */ - reg [0:47] me; - - /* A counter, to determine whether we should be comparing - * with a MAC address or stripping off data - */ - reg [31:0] counter; - - /* An internal set of flags to mark whether the currently - * traversing packet is valid, i.e we should forward data, - * or not. One of these flags tracks whether the destination - * MAC address matches _our_ (FW_ME) mac address, the other - * tracks whether the destination matches the broadcast - * (FW_BCAST) MAC. If either one of these is high once the - * destination MAC finishes rolling through, the packet - * is forwarded. - */ - reg matchme, matchbcast; - - assign me = FPGA_MAC; - - always @(posedge clk) begin: MATCH - if (counter == 32'b0) begin - matchme <= 1'b1; - matchbcast <= 1'b1; - end - - /* could overwrite the above, which is ideal if - * FW_DESTSTART == 0 (it is) and we have a mismatch - * out the gate - */ - if (counter >= `FW_DESTSTART && counter < `FW_DESTEND) begin - if (axiiv) begin - if (axiid != {me[counter], me[counter + 1]}) - matchme <= 1'b0; - if (axiid != 2'b11) - matchbcast <= 1'b0; - end - end - end - - always @(*) begin: AXIOUT - if (counter >= `FW_DATASTART && (matchme | matchbcast)) begin - axiod = axiid; - axiov = axiiv; - end else begin - axiod = 2'b00; - axiov = 1'b0; - end - end - - always @(posedge clk) begin: COUNTER - if (axiiv) counter <= counter + 2; - else counter <= 32'b0; - end - -endmodule - -`default_nettype wire diff --git a/src/manta/ether_iface/mac_rx.v b/src/manta/ether_iface/mac_rx.v deleted file mode 100644 index 46ff330..0000000 --- a/src/manta/ether_iface/mac_rx.v +++ /dev/null @@ -1,106 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module mac_rx ( - input wire clk, - - input wire crsdv, - input wire [1:0] rxd, - - output reg [55:0] payload, - output reg valid); - - parameter FPGA_MAC = 0; - parameter ETHERTYPE = 0; - - reg [1:0] ether_axiod; - reg ether_axiov; - - ether e ( - .clk(clk), - .rxd(rxd), - .crsdv(crsdv), - .axiov(ether_axiov), - .axiod(ether_axiod)); - - reg [1:0] bitorder_axiod; - reg bitorder_axiov; - - bitorder b ( - .clk(clk), - .axiiv(ether_axiov), - .axiid(ether_axiod), - .axiov(bitorder_axiov), - .axiod(bitorder_axiod)); - - reg [1:0] firewall_axiod; - reg firewall_axiov; - - firewall #( - .FPGA_MAC(FPGA_MAC), - .ETHERTYPE(ETHERTYPE) - ) f ( - .clk(clk), - .axiiv(bitorder_axiov), - .axiid(bitorder_axiod), - .axiov(firewall_axiov), - .axiod(firewall_axiod)); - - reg [55:0] aggregate_axiod; - reg aggregate_axiov; - - aggregate a ( - .clk(clk), - .axiiv(firewall_axiov), - .axiid(firewall_axiod), - .axiov(aggregate_axiov), - .axiod(aggregate_axiod)); - - reg cksum_done; - reg cksum_kill; - - cksum c ( - .clk(clk), - .axiiv(ether_axiov), - .axiid(ether_axiod), - .done(cksum_done), - .kill(cksum_kill)); - - // state machine - localparam IDLE = 0; - localparam WAIT_FOR_DATA = 1; - localparam WAIT_FOR_FCS = 2; - - reg [1:0] state = IDLE; - - initial valid = 0; - initial payload = 0; - - always @(posedge clk) begin - valid <= 0; - - if(state == IDLE) begin - if(crsdv) state <= WAIT_FOR_DATA; - end - - else if(state == WAIT_FOR_DATA) begin - if(aggregate_axiov) begin - state <= WAIT_FOR_FCS; - payload <= aggregate_axiod; - end - - // if aggregate never gives us data, - // go back to idle when the packet ends - else if(cksum_done) state <= IDLE; - end - - else if(state == WAIT_FOR_FCS) begin - if(cksum_done) begin - state <= IDLE; - valid <= ~cksum_kill; - end - end - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/ether_iface/mac_tx.v b/src/manta/ether_iface/mac_tx.v deleted file mode 100644 index 812c078..0000000 --- a/src/manta/ether_iface/mac_tx.v +++ /dev/null @@ -1,242 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module mac_tx ( - input wire clk, - - input wire [(8 * PAYLOAD_LENGTH_BYTES)-1:0] payload, - input wire start, - - output reg txen, - output reg [1:0] txd); - - // packet magic numbers - localparam PREAMBLE = {7{8'b01010101}}; - localparam SFD = 8'b11010101; - parameter [47:0] SRC_MAC = 0; - parameter [47:0] DST_MAC = 0; - parameter [15:0] ETHERTYPE = 0; - parameter PAYLOAD_LENGTH_BYTES = 0; - - // all lengths are in units of dibits, hence all the mulitplies by four - localparam PREAMBLE_LEN = 7 * 4; - localparam SFD_LEN = 1 * 4; - localparam SRC_MAC_LEN = 6 * 4; - localparam DST_MAC_LEN = 6 * 4; - localparam ETHERTYPE_LEN = 2 * 4; - localparam PAYLOAD_LEN = PAYLOAD_LENGTH_BYTES * 4; - localparam ZERO_PAD_LEN = (46 * 4) - PAYLOAD_LEN + 4; // minimum payload size is 46 bytes - localparam FCS_LEN = 4 * 4; - localparam IPG_LEN = 96 / 2; - - reg [1:0] bitorder_axiid; - reg [1:0] bitorder_axiod; - reg bitorder_axiiv; - reg bitorder_axiov; - - bitorder bitorder ( - .clk(clk), - - .axiiv(bitorder_axiiv), - .axiid(bitorder_axiid), - - .axiov(bitorder_axiov), - .axiod(bitorder_axiod)); - - reg crc_rst = 1; - reg crc_axiiv = 0; - reg [31:0] crc_axiod; - - crc32 crc ( - .clk(clk), - .rst(crc_rst), - - .axiiv(crc_axiiv), - .axiid(bitorder_axiod), - - // TODO: remove axiov from crc32 module, it's always valid - .axiov(), - .axiod(crc_axiod)); - - - // state machine - reg [8:0] counter = 0; - reg [3:0] state = 0; - - localparam IDLE_STATE = 0; - localparam PREAMBLE_STATE = 1; - localparam SFD_STATE = 2; - localparam DST_MAC_STATE = 3; - localparam SRC_MAC_STATE = 4; - localparam ETHERTYPE_STATE = 5; - localparam PAYLOAD_STATE = 6; - localparam ZERO_PAD_STATE = 7; - localparam FCS_STATE = 8; - localparam IPG_STATE = 9; - - - // sequential logic manages the state machine - always @(posedge clk) begin - counter <= counter + 1; - crc_rst <= 0; - - if(state == IDLE_STATE) begin - counter <= 0; - crc_axiiv <= 0; - if(start) state <= PREAMBLE_STATE; - end - - else if(state == PREAMBLE_STATE) begin - if(counter == PREAMBLE_LEN - 1) begin - counter <= 0; - state <= SFD_STATE; - end - end - - else if(state == SFD_STATE) begin - if(counter == SFD_LEN - 1) begin - counter <= 0; - state <= DST_MAC_STATE; - end - end - - else if(state == DST_MAC_STATE) begin - // this is because the crc module lags behind the FSM, - // as it has to go through bitorder first - if(counter == 3) crc_axiiv <= 1; - - if(counter == DST_MAC_LEN - 1) begin - counter <= 0; - state <= SRC_MAC_STATE; - end - end - - else if(state == SRC_MAC_STATE) begin - if(counter == SRC_MAC_LEN - 1) begin - counter <= 0; - state <= ETHERTYPE_STATE; - end - end - - else if(state == ETHERTYPE_STATE) begin - if(counter == ETHERTYPE_LEN - 1) begin - counter <= 0; - state <= PAYLOAD_STATE; - end - end - - else if(state == PAYLOAD_STATE) begin - if(counter == PAYLOAD_LEN - 1) begin - counter <= 0; - state <= ZERO_PAD_STATE; - end - end - - else if(state == ZERO_PAD_STATE) begin - if(counter == ZERO_PAD_LEN - 1) begin - crc_axiiv <= 0; - counter <= 0; - state <= FCS_STATE; - end - end - - else if(state == FCS_STATE) begin - if(counter == FCS_LEN - 1) begin - counter <= 0; - state <= IPG_STATE; - end - end - - else if(state == IPG_STATE) begin - if(counter == IPG_LEN - 1) begin - crc_rst <= 1; - counter <= 0; - state <= IDLE_STATE; - end - end - end - - // combinational logic handles the pipeline - always @(*) begin - case (state) - IDLE_STATE: begin - bitorder_axiiv = 0; - bitorder_axiid = 0; - txen = 0; - txd = 0; - end - - PREAMBLE_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = PREAMBLE[2*(PREAMBLE_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - SFD_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = SFD[2*(SFD_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - DST_MAC_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = DST_MAC[2*(DST_MAC_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - SRC_MAC_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = SRC_MAC[2*(SRC_MAC_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - ETHERTYPE_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = ETHERTYPE[2*(ETHERTYPE_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - PAYLOAD_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = payload[2*(PAYLOAD_LEN-counter)-1-:2]; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - ZERO_PAD_STATE: begin - bitorder_axiiv = 1; - bitorder_axiid = 0; - txen = bitorder_axiov; - txd = bitorder_axiod; - end - - FCS_STATE: begin - bitorder_axiiv = 0; - bitorder_axiid = 0; - txen = 1; - txd = {crc_axiod[2*(FCS_LEN-counter)-2], crc_axiod[2*(FCS_LEN-counter)-1]}; - end - - IPG_STATE: begin - bitorder_axiiv = 0; - bitorder_axiid = 0; - txen = 0; - txd = 0; - end - - default: begin - bitorder_axiiv = 0; - bitorder_axiid = 0; - txen = 0; - txd = 0; - end - endcase - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/io_core.py b/src/manta/io_core.py new file mode 100644 index 0000000..97d869f --- /dev/null +++ b/src/manta/io_core.py @@ -0,0 +1,260 @@ +from amaranth import * +from warnings import warn +from .utils import * +from math import ceil + + +class IOCore(Elaboratable): + """ + Contains the HDL to instantiate an IO core on a FPGA, and the functions to interact with it. For + more information on the core itself, check out the IO core documentation. + """ + + def __init__(self, config, base_addr, interface): + self.config = config + self.base_addr = base_addr + self.interface = interface + + self.check_config(self.config) + self.define_signals() + self.mmap, self.max_addr = self.assign_memory() + + def check_config(self, config): + # make sure ports are defined + if "inputs" not in config and "outputs" not in config: + raise ValueError("No input or output ports specified.") + + # check for unrecognized options + valid_options = ["type", "inputs", "outputs", "user_clock"] + for option in config: + if option not in valid_options: + warn(f"Ignoring unrecognized option '{option}' in IO core.'") + + # check that user_clock is a bool + if "user_clock" in config: + if not isinstance(config["user_clock"], bool): + raise ValueError("Option user_clock must be a boolean.") + + # check that inputs is only dicts of format name:width + if "inputs" in config: + for name, attrs in config["inputs"].items(): + if not isinstance(name, str): + raise ValueError( + f'Input probe "{name}" has invalid name, names must be strings.' + ) + + if not isinstance(attrs, int): + raise ValueError(f'Input probe "{name}" must have integer width.') + + if not attrs > 0: + raise ValueError(f'Input probe "{name}" must have positive width.') + + if "outputs" in config: + for name, attrs in config["outputs"].items(): + if not isinstance(name, str): + raise ValueError( + f'Output probe "{name}" has invalid name, names must be strings.' + ) + + if not isinstance(attrs, int) and not isinstance(attrs, dict): + raise ValueError(f'Unrecognized format for output probe "{name}".') + + if isinstance(attrs, int): + if not attrs > 0: + raise ValueError( + f'Output probe "{name}" must have positive width.' + ) + + if isinstance(attrs, dict): + # check that each output probe has only recognized options + valid_options = ["width", "initial_value"] + for option in attrs: + if option not in valid_options: + warn(f'Ignoring unrecognized option "{option}" in IO core.') + + # check that widths are appropriate + if "width" not in attrs: + raise ValueError(f"No width specified for output probe {name}.") + + if not isinstance(attrs["width"], int): + raise ValueError( + f'Output probe "{name}" must have integer width.' + ) + + if not attrs["width"] > 0: + raise ValueError( + f'Input probe "{name}" must have positive width.' + ) + + def define_signals(self): + # Bus Ports + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal() + self.valid_o = Signal() + + # Input Probes (and buffers) + if "inputs" in self.config: + for name, width in self.config["inputs"].items(): + setattr(self, name, Signal(width, name=name)) + setattr(self, name + "_buf", Signal(width, name=name + "_buf")) + + # Output Probes (and buffers) + if "outputs" in self.config: + for name, attrs in self.config["outputs"].items(): + if isinstance(attrs, dict): + width = attrs["width"] + initial_value = attrs["initial_value"] + else: + width = attrs + initial_value = 0 + + setattr(self, name, Signal(width, name=name, reset=initial_value)) + setattr( + self, + name + "_buf", + Signal(width, name=name + "_buf", reset=initial_value), + ) + + # Strobe Register + self.strobe = Signal(reset=0) + + def assign_memory(self): + """ + the memory map is a dict that maps registers (in memory) to their locations (in memory) + as well as their Signals (from Amaranth). This looks like the following: + + { + strobe: + addrs: [0x0000] + signals: [self.strobe] + probe0_buf: + addrs: [0x0001] + signals: [self.probe0_buf] + probe1_buf: + addrs: [0x0002] + signals: [self.probe1_buf] + probe2_buf: + addrs: [0x0003] + signals: [self.probe2_buf] + probe3_buf: + addrs: [0x0004, 0x0005] + signals: [self.probe3_buf[0:15], self.probe3_buf[16:19]] + ... and so on + } + + """ + mmap = {} + + # Add strobe register first + mmap["strobe"] = dict(addrs=[self.base_addr], signals=[self.strobe]) + + # Add all input and output probes + all_probes = {} + if "inputs" in self.config: + all_probes = {**all_probes, **self.config["inputs"]} + + if "outputs" in self.config: + all_probes = {**all_probes, **self.config["outputs"]} + + for name, attrs in all_probes.items(): + # Handle output probes that might have initial value specified in addition to width + if isinstance(attrs, dict): + width = attrs["width"] + else: + width = attrs + + # Assign addresses + last_used_addr = list(mmap.values())[-1]["addrs"][-1] + addrs = [last_used_addr + 1 + i for i in range(ceil(width / 16))] + + # Slice signal into 16-bit chunks + signal = getattr(self, name + "_buf") + signals = [signal[16 * i : 16 * (i + 1)] for i in range(ceil(width / 16))] + + mmap[name + "_buf"] = {"addrs": addrs, "signals": signals} + + # Compute maximum address used by the core + max_addr = list(mmap.values())[-1]["addrs"][-1] + return mmap, max_addr + + def elaborate(self, platform): + m = Module() + + # Shuffle bus transactions along + m.d.sync += self.addr_o.eq(self.addr_i) + m.d.sync += self.data_o.eq(self.data_i) + m.d.sync += self.rw_o.eq(self.rw_i) + m.d.sync += self.valid_o.eq(self.valid_i) + + # Update buffers from probes + with m.If(self.strobe): + # Input buffers + if "inputs" in self.config: + for name in self.config["inputs"]: + input_probe = getattr(self, name) + input_probe_buf = getattr(self, name + "_buf") + m.d.sync += input_probe_buf.eq(input_probe) + + # Output buffers + if "outputs" in self.config: + for name in self.config["outputs"]: + output_probe = getattr(self, name) + output_probe_buf = getattr(self, name + "_buf") + m.d.sync += output_probe.eq(output_probe_buf) + + # Handle register reads and writes + with m.If((self.addr_i >= self.base_addr)): + with m.If((self.addr_o <= self.max_addr)): + for entry in self.mmap.values(): + for addr, signal in zip(entry["addrs"], entry["signals"]): + with m.If(self.rw_i): + with m.If(self.addr_i == addr): + m.d.sync += signal.eq(self.data_i) + + with m.Else(): + with m.If(self.addr_i == addr): + m.d.sync += self.data_o.eq(signal) + + return m + + def get_top_level_ports(self): + ports = [] + for name in self.config["inputs"].keys(): + ports.append(getattr(self, name)) + + for name in self.config["outputs"].keys(): + ports.append(getattr(self, name)) + + return ports + + def get_max_addr(self): + return self.max_addr + + def set_probe(self, probe_name, value): + # set value in buffer + addrs = self.mmap[probe_name + "_buf"]["addrs"] + datas = value_to_words(value, len(addrs)) + self.interface.write(addrs, datas) + + # pulse strobe register + strobe_addr = self.mmap["strobe"]["addrs"][0] + self.interface.write(strobe_addr, 0) + self.interface.write(strobe_addr, 1) + self.interface.write(strobe_addr, 0) + + def get_probe(self, probe_name): + # pulse strobe register + strobe_addr = self.mmap["strobe"]["addrs"][0] + self.interface.write(strobe_addr, 0) + self.interface.write(strobe_addr, 1) + self.interface.write(strobe_addr, 0) + + # get value from buffer + addrs = self.mmap[probe_name + "_buf"]["addrs"] + return words_to_value(self.interface.read(addrs)) diff --git a/src/manta/io_core/__init__.py b/src/manta/io_core/__init__.py deleted file mode 100644 index 8e33562..0000000 --- a/src/manta/io_core/__init__.py +++ /dev/null @@ -1,213 +0,0 @@ -from ..utils import * -from math import ceil - -class InputProbe: - def __init__(self, name, width, base_addr, strobe_addr, interface): - assert isinstance(width, int), f"Probe {name} must have integer width." - assert width > 0, f"Probe {name} must have positive width." - - self.name = name - self.width = width - self.strobe_addr = strobe_addr - self.interface = interface - - n_addrs = ceil(self.width / 16) - self.addrs = list(range(base_addr, base_addr + n_addrs)) - self.brackets = "" if self.width == 1 else f"[{self.width-1}:0] " - - def pulse_strobe_register(self): - # pulse the strobe register - self.interface.write(self.strobe_addr, 1) - self.interface.write(self.strobe_addr, 0) - strobe = self.interface.read(self.strobe_addr) - if strobe != 0: - raise ValueError("Unable to set strobe register to zero!") - - def get(self): - self.pulse_strobe_register() - return pack_16bit_words(self.interface.read(self.addrs)) - -class OutputProbe(InputProbe): - def __init__(self, name, width, base_addr, strobe_addr, interface, initial_value): - super().__init__(name, width, base_addr, strobe_addr, interface) - self.initial_value = initial_value - - def set(self, value): - # check that value is an integer - assert isinstance(value, int), "Value must be an integer." - - # check that value is within range for the width of the probe - if value > 0: - assert value <= (2**self.width) - 1, f"Unsigned value too large for probe of width {self.width}" - - elif value < 0: - assert abs(value) <= (2**(self.width-1))-1, f"Signed value too large for probe of width {self.width}" - - self.interface.write(self.addrs, unpack_16bit_words(value, len(self.addrs))) - self.pulse_strobe_register() - -class IOCore: - def __init__(self, config, name, base_addr, interface): - self.name = name - self.base_addr = base_addr - self.interface = interface - - # make sure we have ports defined - assert ('inputs' in config) or ('outputs' in config), "No input or output ports specified." - - # check for unrecognized options - for option in config: - if option not in ["type", "inputs", "outputs", "user_clock"]: - print(f"Warning: Ignoring unrecognized option '{option}' in IO core '{name}'") - - # add user clock - self.user_clock = False - if "user_clock" in config: - assert isinstance(config["user_clock"], bool), "Option user_clock must be a boolean." - self.user_clock = config["user_clock"] - - # add input probes to core - self.input_probes = [] - last_used_addr = self.base_addr # start at one since strobe register is at BASE_ADDR - if 'inputs' in config: - for name, width in config["inputs"].items(): - probe = InputProbe(name, width, last_used_addr + 1, self.base_addr, interface) - last_used_addr = probe.addrs[-1] - self.input_probes.append(probe) - - # add output probes to core - self.output_probes = [] - if 'outputs' in config: - for name, params in config["outputs"].items(): - # get width and initial value from config - if isinstance(params, int): - width = params - initial_value = 0 - - elif "width" in params and "initial_value" in params: - width = params["width"] - initial_value = params["initial_value"] - - else: - raise ValueError(f"Unable to determine probe width and initial value for {name}") - - # add probe to core - probe = OutputProbe(name, width, last_used_addr + 1, self.base_addr, interface, initial_value) - last_used_addr = probe.addrs[-1] - self.output_probes.append(probe) - - self.max_addr = last_used_addr - - # add friendly names to each probe - # (so users can do io_core.probe.set() and get() for instance) - for probe in self.input_probes + self.output_probes: - setattr(self, probe.name, probe) - - def hdl_top_level_ports(self): - ports = [] - - if self.user_clock: - ports.append(f"input wire {self.name}_user_clock") - - for probe in self.input_probes: - ports.append(f"input wire {probe.brackets}{probe.name}") - - for probe in self.output_probes: - ports.append(f"output reg {probe.brackets}{probe.name}") - - return ports - - def hdl_inst(self): - inst = VerilogManipulator("io_core/io_core_inst_tmpl.v") - inst.sub(self.name, "/* MODULE_NAME */") - inst.sub(self.name + "_inst", "/* INST_NAME */") - - # tie user_clock to bus_clk if external clock is not being used - if not self.user_clock: - inst.sub("clk", "/* USER_CLK */") - - else: - inst.sub(f"{self.name}_user_clk", "/* USER_CLK */") - - probes = {p.name:p.width for p in self.input_probes + self.output_probes} - inst_ports = inst.net_conn(probes, trailing_comma=True) - inst.sub(inst_ports, "/* INST_PORTS */") - - return inst.get_hdl() - - def hdl_def(self): - io_core = VerilogManipulator("io_core/io_core_def_tmpl.v") - io_core.sub(self.name, "/* MODULE_NAME */") - io_core.sub(self.max_addr, "/* MAX_ADDR */") - - # generate declaration - top_level_ports = ',\n'.join(self.hdl_top_level_ports()) - top_level_ports += ',' - io_core.sub(top_level_ports, "/* TOP_LEVEL_PORTS */") - - # generate memory handling - io_core.sub(self.gen_read_case_statement_body(), "/* READ_CASE_STATEMENT_BODY */") - io_core.sub(self.gen_write_case_statement_body(), "/* WRITE_CASE_STATEMENT_BODY */") - - # generate input and output probe buffers with initial values - io_core.sub(self.gen_input_probe_bufs(), "/* INPUT_PROBE_BUFFERS */") - io_core.sub(self.gen_output_probe_bufs(), "/* OUTPUT_PROBE_BUFFERS */") - io_core.sub(self.gen_output_probe_initial_values(), "/* OUTPUT_PROBE_INITIAL_VALUES */") - io_core.sub(self.gen_update_input_buffers(), "/* UPDATE_INPUT_BUFFERS */") - io_core.sub(self.gen_update_output_buffers(), "/* UPDATE_OUTPUT_BUFFERS */") - - return io_core.get_hdl() - - def gen_read_case_statement_body(self): - lines = [] - for probe in self.input_probes + self.output_probes: - if probe.width <= 16: - lines.append(f"BASE_ADDR + {probe.addrs[0]}: data_o <= {probe.name}_buf;") - - # assign 16-bit slices of each probe's buffer to each address taken by the probe - else: - for i in range(ceil(probe.width/16)): - top = ((i + 1) * 16) - 1 - btm = i * 16 - if top > probe.width - 1: - top = probe.width - 1 - lines.append(f"BASE_ADDR + {probe.addrs[i]}: data_o <= {probe.name}_buf[{top}:{btm}];") - - return '\n'.join(lines) - - def gen_write_case_statement_body(self): - lines = [] - for probe in self.output_probes: - if probe.width <= 16: - lines.append(f"BASE_ADDR + {probe.addrs[0]}: {probe.name}_buf <= data_i;") - - else: - for i in range(ceil(probe.width/16)): - top = ((i + 1) * 16) - 1 - btm = i * 16 - if top > probe.width - 1: - top = probe.width - 1 - - lines.append(f"BASE_ADDR + {probe.addrs[i]}: {probe.name}_buf[{top}:{btm}] <= data_i;") - - return '\n'.join(lines) - - def gen_input_probe_bufs(self): - lines = [f"reg {p.brackets}{p.name}_buf = 0;" for p in self.input_probes] - return '\n'.join(lines) - - def gen_output_probe_bufs(self): - lines = [f"reg {p.brackets}{p.name}_buf = {p.initial_value};" for p in self.output_probes] - return '\n'.join(lines) - - def gen_output_probe_initial_values(self): - lines = [f"{p.name} = {p.initial_value};" for p in self.output_probes] - return '\n'.join(lines) - - def gen_update_input_buffers(self): - lines = [f"{p.name}_buf <= {p.name};" for p in self.input_probes] - return '\n'.join(lines) - - def gen_update_output_buffers(self): - lines = [f"{p.name} <= {p.name}_buf;" for p in self.output_probes] - return '\n'.join(lines) diff --git a/src/manta/io_core/io_core_def_tmpl.v b/src/manta/io_core/io_core_def_tmpl.v deleted file mode 100644 index 5803486..0000000 --- a/src/manta/io_core/io_core_def_tmpl.v +++ /dev/null @@ -1,77 +0,0 @@ -module /* MODULE_NAME */ ( - input wire bus_clk, - input wire user_clk, - - // ports - /* TOP_LEVEL_PORTS */ - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o - ); - - parameter BASE_ADDR = 0; - - reg strobe = 0; - - // input probe buffers - /* INPUT_PROBE_BUFFERS */ - - // output probe buffers - /* OUTPUT_PROBE_BUFFERS */ - - // output probe initial values - initial begin - /* OUTPUT_PROBE_INITIAL_VALUES */ - end - - // synchronize buffers and probes on strobe - always @(posedge user_clk) begin - if(strobe) begin - // update input buffers from input probes - /* UPDATE_INPUT_BUFFERS */ - - // update output buffers from output probes - /* UPDATE_OUTPUT_BUFFERS */ - end - end - - // handle bus operations - always @(posedge bus_clk) begin - addr_o <= addr_i; - data_o <= data_i; - rw_o <= rw_i; - valid_o <= valid_i; - - // check if address is valid - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + /* MAX_ADDR */)) begin - - // reads - if(!rw_i) begin - case (addr_i) - BASE_ADDR + 0: data_o <= strobe; - - /* READ_CASE_STATEMENT_BODY */ - endcase - end - - // writes - else begin - case (addr_i) - BASE_ADDR + 0: strobe <= data_i; - - /* WRITE_CASE_STATEMENT_BODY */ - endcase - end - end - end - -endmodule \ No newline at end of file diff --git a/src/manta/io_core/io_core_inst_tmpl.v b/src/manta/io_core/io_core_inst_tmpl.v deleted file mode 100644 index 4568ef0..0000000 --- a/src/manta/io_core/io_core_inst_tmpl.v +++ /dev/null @@ -1,18 +0,0 @@ -/* MODULE_NAME */ /* INST_NAME */ ( - .bus_clk(clk), - .user_clk(/* USER_CLK */), - - // ports - /* INST_PORTS */ - - // input port - .addr_i(), - .data_i(), - .rw_i(), - .valid_i(), - - // output port - .addr_o(), - .data_o(), - .rw_o(), - .valid_o()); \ No newline at end of file diff --git a/src/manta/la_core/__init__.py b/src/manta/la_core/__init__.py deleted file mode 100644 index a33c307..0000000 --- a/src/manta/la_core/__init__.py +++ /dev/null @@ -1,463 +0,0 @@ -from ..utils import * - -from datetime import datetime -from pkg_resources import get_distribution -import math -import os - -class LogicAnalyzerCore: - def __init__(self, config, name, base_addr, interface): - self.name = name - self.base_addr = base_addr - self.interface = interface - - # Warn if unrecognized options have been given - valid_options = ["type", "sample_depth", "probes", "triggers", "trigger_loc", "trigger_mode"] - for option in config: - if option not in valid_options: - print(f"Warning: Ignoring unrecognized option '{option}' in Logic Analyzer core '{self.name}'") - - # Load sample depth - assert "sample_depth" in config, \ - "Sample depth not found for Logic Analyzer core {self.name}." - - assert isinstance(config["sample_depth"], int), \ - "Sample depth must be an integer." - - self.sample_depth = config["sample_depth"] - - # Add probes - assert "probes" in config, "No probe definitions found." - assert len(config["probes"]) > 0, "Must specify at least one probe." - - for probe_name, probe_width in config["probes"].items(): - assert probe_width > 0, f"Probe {probe_name} is of invalid width - it must be of at least width one." - - self.probes = config["probes"] - - # Add triggers - assert "triggers" in config, "No triggers found." - assert len(config["triggers"]) > 0, "Must specify at least one trigger." - self.triggers = config["triggers"] - - # Add trigger location - self.trigger_loc = self.sample_depth // 2 - if "trigger_loc" in config: - assert isinstance(config["trigger_loc"], int), \ - "Trigger location must be an integer." - - assert config["trigger_loc"] >= 0, \ - "Trigger location cannot be negative." - - assert config["trigger_loc"] <= self.sample_depth, \ - "Trigger location cannot exceed sample depth." - - self.trigger_loc = config["trigger_loc"] - - # Add trigger mode - self.SINGLE_SHOT = 0 - self.INCREMENTAL = 1 - self.IMMEDIATE = 2 - - self.trigger_mode = self.SINGLE_SHOT - if "trigger_mode" in config: - assert config["trigger_mode"] in ["single_shot", "incremental", "immediate"], \ - "Unrecognized trigger mode provided." - - if config["trigger_mode"] == "single_shot": - self.trigger_mode = self.SINGLE_SHOT - - elif config["trigger_mode"] == "incremental": - self.trigger_mode = self.INCREMENTAL - - elif config["trigger_mode"] == "immediate": - self.trigger_mode = self.IMMEDIATE - - # compute base addresses - self.fsm_base_addr = self.base_addr - self.trigger_block_base_addr = self.fsm_base_addr + 7 - - self.total_probe_width = sum(self.probes.values()) - self.n_brams = math.ceil(self.total_probe_width / 16) - self.block_memory_base_addr = self.trigger_block_base_addr + (2*len(self.probes)) - self.max_addr = self.block_memory_base_addr + (self.n_brams * self.sample_depth) - - # build out self register map: - # these are also defined in logic_analyzer_fsm_registers.v, and should match - self.state_reg_addr = self.base_addr - self.trigger_mode_reg_addr = self.base_addr + 1 - self.trigger_loc_reg_addr = self.base_addr + 2 - self.request_start_reg_addr = self.base_addr + 3 - self.request_stop_reg_addr = self.base_addr + 4 - self.read_pointer_reg_addr = self.base_addr + 5 - self.write_pointer_reg_addr = self.base_addr + 6 - - self.IDLE = 0 - self.MOVE_TO_POSITION = 1 - self.IN_POSITION = 2 - self.CAPTURING = 3 - self.CAPTURED = 4 - - def hdl_inst(self): - la_inst = VerilogManipulator("la_core/logic_analyzer_inst_tmpl.v") - - # add module name to instantiation - la_inst.sub(self.name, "/* INST_NAME */") - - # add net connections to instantiation - conns = la_inst.net_conn(self.probes, trailing_comma=True) - la_inst.sub(conns, "/* NET_CONNS */") - return la_inst.get_hdl() - - def gen_trigger_block_def(self): - trigger_block = VerilogManipulator("la_core/trigger_block_def_tmpl.v") - - # add probe ports to module declaration - # these ports belong to the logic analyzer, but - # need to be included in the trigger_block module declaration - probe_ports = trigger_block.net_dec(self.probes, "input wire", trailing_comma=True) - trigger_block.sub(probe_ports, "/* PROBE_PORTS */") - - - # add trigger cores to module definition - # these are instances of the trigger module, of which one gets wired - # into each probe - trigger_module_insts = [] - for name, width in self.probes.items(): - trig_inst = VerilogManipulator("la_core/trigger_block_inst_tmpl.v") - trig_inst.sub(width, "/* INPUT_WIDTH */") - trig_inst.sub(f"{name}_trigger", "/* NAME */") - - trig_inst.sub(f"reg [3:0] {name}_op = 0;", "/* OP_DEC */") - trig_inst.sub(f"reg {name}_trig;", "/* TRIG_DEC */") - - if width == 1: - trig_inst.sub(f"reg {name}_arg = 0;", "/* ARG_DEC */") - - else: - trig_inst.sub(f"reg [{width-1}:0] {name}_arg = 0;", "/* ARG_DEC */") - - trig_inst.sub(name, "/* PROBE */") - trig_inst.sub(f"{name}_op", "/* OP */") - trig_inst.sub(f"{name}_arg", "/* ARG */") - trig_inst.sub(f"{name}_trig", "/* TRIG */") - - trigger_module_insts.append(trig_inst.get_hdl()) - - trigger_module_insts = "\n".join(trigger_module_insts) - trigger_block.sub(trigger_module_insts, "/* TRIGGER_MODULE_INSTS */") - - # add combined individual triggers - cit = [f"{name}_trig" for name in self.probes] - cit = " || ".join(cit) - cit = f"assign trig = {cit};" - trigger_block.sub(cit, " /* COMBINE_INDIV_TRIGGERS */") - - # add read and write block case statement bodies - rcsb = "" # read case statement body - wcsb = "" # write case statement body - addr = 0 - for i, name in enumerate(self.probes): - addr = 2 * i - rcsb += f"BASE_ADDR + {addr}: data_o <= {name}_op;\n" - wcsb += f"BASE_ADDR + {addr}: {name}_op <= data_i;\n" - - addr = (2 * i) + 1 - rcsb += f"BASE_ADDR + {addr}: data_o <= {name}_arg;\n" - wcsb += f"BASE_ADDR + {addr}: {name}_arg <= data_i;\n" - - rcsb = rcsb.strip() - wcsb = wcsb.strip() - - trigger_block.sub(rcsb, "/* READ_CASE_STATEMENT_BODY */") - trigger_block.sub(wcsb, "/* WRITE_CASE_STATEMENT_BODY */") - trigger_block.sub(self.trigger_block_base_addr + addr + 1, "/* MAX_ADDR */") - - return trigger_block.get_hdl() - - def gen_logic_analyzer_def(self): - la = VerilogManipulator("la_core/logic_analyzer_def_tmpl.v") - - # add top level probe ports to module declaration - ports = la.net_dec(self.probes, "input wire", trailing_comma=True) - la.sub(ports, "/* TOP_LEVEL_PROBE_PORTS */") - - # assign base addresses to the FSM, trigger block, and sample mem - la.sub(self.fsm_base_addr, "/* FSM_BASE_ADDR */") - la.sub(self.trigger_block_base_addr, "/* TRIGGER_BLOCK_BASE_ADDR */") - la.sub(self.block_memory_base_addr, "/* BLOCK_MEMORY_BASE_ADDR */") - - # set sample depth - la.sub(self.sample_depth, "/* SAMPLE_DEPTH */") - - # set probe ports for the trigger block and sample mem - probe_ports = la.net_conn(self.probes, trailing_comma=True) - la.sub(probe_ports, "/* TRIGGER_BLOCK_PROBE_PORTS */") - - la.sub(self.total_probe_width, "/* TOTAL_PROBE_WIDTH */") - - # concatenate the probes together to make one big register, - # but do so such that the first probe in the config file - # is at the least-significant position in that big register. - # - # this makes part-selecting out from the memory easier to - # implement in python, and because verilog and python conventions - # are different, we would have had to reverse it somwehere anyway - probes_concat = list(self.probes.keys())[::-1] - probes_concat = '{' + ', '.join(probes_concat) + '}' - la.sub(probes_concat, "/* PROBES_CONCAT */") - - return la.get_hdl() - - def hdl_def(self): - # Return an autogenerated verilog module definition for the core. - # load source files - hdl = self.gen_logic_analyzer_def() + "\n" - hdl += VerilogManipulator("la_core/logic_analyzer_controller.v").get_hdl() + "\n" - hdl += VerilogManipulator("la_core/logic_analyzer_fsm_registers.v").get_hdl() + "\n" - hdl += VerilogManipulator("block_mem_core/block_memory.v").get_hdl() + "\n" - hdl += VerilogManipulator("block_mem_core/dual_port_bram.v").get_hdl() + "\n" - hdl += self.gen_trigger_block_def() + "\n" - hdl += VerilogManipulator("la_core/trigger.v").get_hdl() + "\n" - - return hdl - - def hdl_top_level_ports(self): - # the probes that we want as ports on the top-level manta module - ports = [] - for name, width in self.probes.items(): - if width == 1: - ports.append(f"input wire {name}") - - else: - ports.append(f"input wire [{width-1}:0] {name}") - return ports - #return VerilogManipulator().net_dec(self.probes, "input wire") - - def set_trigger_conditions(self): - - operations = { - "DISABLE" : 0, - "RISING" : 1, - "FALLING" : 2, - "CHANGING" : 3, - "GT" : 4, - "LT" : 5, - "GEQ" : 6, - "LEQ" : 7, - "EQ" : 8, - "NEQ" : 9 - } - - ops_with_no_args = ["DISABLE", "RISING" , "FALLING", "CHANGING"] - - # reset all the other triggers - for addr in range(self.trigger_block_base_addr, self.block_memory_base_addr): - self.interface.write(addr, 0) - - for trigger in self.triggers: - # determine if the trigger is good - - # most triggers will have 3 parts - the trigger, the operation, and the argument - # this is true unless the argument is RISING, FALLING, or CHANGING - - statement = trigger.split(' ') - if len(statement) == 2: - assert statement[1] in ops_with_no_args, "Invalid operation in trigger statement." - probe_name, op = statement - - op_register = 2*(list(self.probes.keys()).index(probe_name)) + self.trigger_block_base_addr - - self.interface.write(op_register, operations[op]) - - else: - assert len(statement) == 3, "Missing information in trigger statement." - probe_name, op, arg = statement - - op_register = 2*(list(self.probes.keys()).index(probe_name)) + self.trigger_block_base_addr - arg_register = op_register + 1 - - self.interface.write(op_register, operations[op]) - self.interface.write(arg_register, int(arg)) - - - - # functions for actually using the core: - def capture(self): - # Check state - if it's in anything other than IDLE, - # request to stop the existing capture - - print(" -> Resetting core...") - state = self.interface.read(self.state_reg_addr) - if state != self.IDLE: - self.interface.write(self.request_stop_reg_addr, 0) - self.interface.write(self.request_stop_reg_addr, 1) - self.interface.write(self.request_stop_reg_addr, 0) - - state = self.interface.read(self.state_reg_addr) - assert state == self.IDLE, "Logic analyzer did not reset to correct state when requested to." - - # Configure trigger conditions - print(" -> Set trigger conditions...") - self.set_trigger_conditions() - - # Configure the trigger_mode - print(" -> Setting trigger mode") - self.interface.write(self.trigger_mode_reg_addr, self.trigger_mode) - - # Configure the trigger_loc - print(" -> Setting trigger location...") - self.interface.write(self.trigger_loc_reg_addr, self.trigger_loc) - - # Start the capture by pulsing request_start - print(" -> Starting capture...") - self.interface.write(self.request_start_reg_addr, 1) - self.interface.write(self.request_start_reg_addr, 0) - - # Wait for core to finish capturing data - print(" -> Waiting for capture to complete...") - state = self.interface.read(self.state_reg_addr) - while(state != self.CAPTURED): - state = self.interface.read(self.state_reg_addr) - - # Read out contents from memory - print(" -> Reading sample memory contents...") - addrs = list(range(self.block_memory_base_addr, self.max_addr)) - block_mem_contents = self.interface.read(addrs) - - # Revolve BRAM contents around so the data pointed to by the read_pointer - # is at the beginning - print(" -> Reading read_pointer and revolving memory...") - read_pointer = self.interface.read(self.read_pointer_reg_addr) - - # when the total probe width is >16 bits and multiple BRAMs are used, - # then a single sample is stored across multiple locations in memory, - # so we must combine the data from n_brams addresses to get the value - # of the sample at that time - - # convert the sample number at read_pointer to memory address - read_address = self.n_brams * read_pointer - sample_mem = block_mem_contents[read_address:] + block_mem_contents[:read_address] - - # split sample memory into chunks of size n_brams - chunks = [sample_mem[i: i + self.n_brams] for i in range(0, len(sample_mem), self.n_brams)] - - # concat them in little-endian order (ie, chunk[0] is LSB) - concat = lambda x: int( ''.join([f'{i:016b}' for i in x[::-1]]), 2) - return [concat(c) for c in chunks] - - - def export_vcd(self, capture_data, path): - from vcd import VCDWriter - vcd_file = open(path, "w") - - # Use the same datetime format that iVerilog uses - timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y") - - with VCDWriter(vcd_file, '10 ns', timestamp, "manta") as writer: - - # each probe has a name, width, and writer associated with it - signals = [] - for name, width in self.probes.items(): - signal = { - "name" : name, - "width" : width, - "data" : self.part_select_capture_data(capture_data, name), - "var": writer.register_var("manta", name, "wire", size=width) - } - signals.append(signal) - - clock = writer.register_var("manta", "clk", "wire", size=1) - trigger = writer.register_var("manta", "trigger", "wire", size=1) - - # add the data to each probe in the vcd file - for timestamp in range(0, 2*len(capture_data)): - - # run the clock - writer.change(clock, timestamp, timestamp % 2 == 0) - - # set the trigger - triggered = (timestamp // 2) >= self.trigger_loc - writer.change(trigger, timestamp, triggered) - - # add other signals - for signal in signals: - var = signal["var"] - sample = signal["data"][timestamp // 2] - - writer.change(var, timestamp, sample) - - vcd_file.close() - - def export_mem(self, capture_data, path): - with open(path, "w") as f: - # a wee bit of cursed string formatting, but just - # outputs each sample as binary, padded to a fixed length - w = self.total_probe_width - f.writelines([f'{s:0{w}b}\n' for s in capture_data]) - - def export_playback_module(self, path): - playback = VerilogManipulator("la_core/logic_analyzer_playback_tmpl.v") - - module_name = f"{self.name}_playback" - playback.sub(module_name, "/* MODULE_NAME */") - - version = "v" + get_distribution('mantaray').version - playback.sub(version, "/* VERSION */") - - timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S") - playback.sub(timestamp, "/* TIMESTAMP */") - - user = os.environ.get("USER", os.environ.get("USERNAME")) - playback.sub(user, "/* USER */") - - ports = [f".{name}({name})" for name in self.probes.keys()] - ports = ",\n".join(ports) - playback.sub(ports, "/* PORTS */") - - playback.sub(self.sample_depth, "/* SAMPLE_DEPTH */") - playback.sub(self.total_probe_width, "/* TOTAL_PROBE_WIDTH */") - - # see the note in generate_logic_analyzer_def about why we do this - probes_concat = list(self.probes.keys())[::-1] - probes_concat = '{' + ', '.join(probes_concat) + '}' - playback.sub(probes_concat, "/* PROBES_CONCAT */") - - - probe_dec = playback.net_dec(self.probes, "output reg") - playback.sub(probe_dec, "/* PROBE_DEC */") - - with open(path, "w") as f: - f.write(playback.get_hdl()) - - - def part_select_capture_data(self, capture_data, probe_name): - """Given the name of the probe, part-select the appropriate bits of capture data, - and return as an integer. Accepts capture_data as an integer or a list of integers.""" - - # sum up the widths of the probes below this one - lower = 0 - for name, width in self.probes.items(): - if name == probe_name: - break - - lower += width - - upper = lower + (self.probes[probe_name] - 1) - - # define the part select - mask = 2 ** (upper - lower + 1) - 1 - part_select = lambda x: (x >> lower) & mask - - # apply the part_select function depending on type - if isinstance(capture_data, int): - return part_select(capture_data) - - elif isinstance(capture_data, list): - for i in capture_data: - assert isinstance(i, int), "Can only part select on integers and list of integers." - - return [part_select(sample) for sample in capture_data] - - else: - raise ValueError("Can only part select on integers and lists of integers.") diff --git a/src/manta/la_core/logic_analyzer_controller.v b/src/manta/la_core/logic_analyzer_controller.v deleted file mode 100644 index 50c90bf..0000000 --- a/src/manta/la_core/logic_analyzer_controller.v +++ /dev/null @@ -1,92 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module logic_analyzer_controller ( - input wire clk, - - // from register file - output reg [3:0] state, - input wire [15:0] trigger_loc, - input wire [1:0] trigger_mode, - input wire request_start, - input wire request_stop, - output reg [ADDR_WIDTH-1:0] read_pointer, - output reg [ADDR_WIDTH-1:0] write_pointer, - - // from trigger block - input wire trig, - - // block memory user port - output reg [ADDR_WIDTH-1:0] bram_addr, - output reg bram_we - ); - - assign bram_addr = write_pointer; - - parameter SAMPLE_DEPTH= 0; - localparam ADDR_WIDTH = $clog2(SAMPLE_DEPTH); - - /* ----- FIFO ----- */ - initial read_pointer = 0; - initial write_pointer = 0; - - /* ----- FSM ----- */ - localparam IDLE = 0; - localparam MOVE_TO_POSITION = 1; - localparam IN_POSITION = 2; - localparam CAPTURING = 3; - localparam CAPTURED = 4; - - initial state = IDLE; - - // rising edge detection for start/stop requests - reg prev_request_start; - always @(posedge clk) prev_request_start <= request_start; - - reg prev_request_stop; - always @(posedge clk) prev_request_stop <= request_stop; - - always @(posedge clk) begin - // don't do anything to the FIFO unless told to - - if(state == IDLE) begin - write_pointer <= 0; - read_pointer <= 0; - bram_we <= 0; - - if(request_start && ~prev_request_start) begin - state <= MOVE_TO_POSITION; - end - end - - else if(state == MOVE_TO_POSITION) begin - write_pointer <= write_pointer + 1; - bram_we <= 1; - - if(write_pointer == trigger_loc) begin - if(trig) state <= CAPTURING; - else state <= IN_POSITION; - end - end - - else if(state == IN_POSITION) begin - write_pointer <= (write_pointer + 1) % SAMPLE_DEPTH; - read_pointer <= (read_pointer + 1) % SAMPLE_DEPTH; - bram_we <= 1; - if(trig) state <= CAPTURING; - end - - else if(state == CAPTURING) begin - if(write_pointer == read_pointer) begin - bram_we <= 0; - state <= CAPTURED; - end - - else write_pointer <= (write_pointer + 1) % SAMPLE_DEPTH; - end - - if(request_stop && ~prev_request_stop) state <= IDLE; - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/logic_analyzer_def_tmpl.v b/src/manta/la_core/logic_analyzer_def_tmpl.v deleted file mode 100644 index cbb0ef9..0000000 --- a/src/manta/la_core/logic_analyzer_def_tmpl.v +++ /dev/null @@ -1,142 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module logic_analyzer ( - input wire clk, - - // probes - /* TOP_LEVEL_PROBE_PORTS */ - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o - ); - localparam SAMPLE_DEPTH = /* SAMPLE_DEPTH */; - localparam ADDR_WIDTH = $clog2(SAMPLE_DEPTH); - - reg [3:0] state; - reg [15:0] trigger_loc; - reg [1:0] trigger_mode; - reg request_start; - reg request_stop; - reg [ADDR_WIDTH-1:0] read_pointer; - reg [ADDR_WIDTH-1:0] write_pointer; - - reg trig; - - reg [ADDR_WIDTH-1:0] bram_addr; - reg bram_we; - - localparam TOTAL_PROBE_WIDTH = /* TOTAL_PROBE_WIDTH */; - reg [TOTAL_PROBE_WIDTH-1:0] probes_concat; - assign probes_concat = /* PROBES_CONCAT */; - - logic_analyzer_controller #(.SAMPLE_DEPTH(SAMPLE_DEPTH)) la_controller ( - .clk(clk), - - // from register file - .state(state), - .trigger_loc(trigger_loc), - .trigger_mode(trigger_mode), - .request_start(request_start), - .request_stop(request_stop), - .read_pointer(read_pointer), - .write_pointer(write_pointer), - - // from trigger block - .trig(trig), - - // from block memory user port - .bram_addr(bram_addr), - .bram_we(bram_we) - ); - - logic_analyzer_fsm_registers #( - .BASE_ADDR(/* FSM_BASE_ADDR */), - .SAMPLE_DEPTH(SAMPLE_DEPTH) - ) fsm_registers ( - .clk(clk), - - .addr_i(addr_i), - .data_i(data_i), - .rw_i(rw_i), - .valid_i(valid_i), - - .addr_o(fsm_reg_trig_blk_addr), - .data_o(fsm_reg_trig_blk_data), - .rw_o(fsm_reg_trig_blk_rw), - .valid_o(fsm_reg_trig_blk_valid), - - .state(state), - .trigger_loc(trigger_loc), - .trigger_mode(trigger_mode), - .request_start(request_start), - .request_stop(request_stop), - .read_pointer(read_pointer), - .write_pointer(write_pointer)); - - reg [15:0] fsm_reg_trig_blk_addr; - reg [15:0] fsm_reg_trig_blk_data; - reg fsm_reg_trig_blk_rw; - reg fsm_reg_trig_blk_valid; - - // trigger block - trigger_block #(.BASE_ADDR(/* TRIGGER_BLOCK_BASE_ADDR */)) trig_blk ( - .clk(clk), - - /* TRIGGER_BLOCK_PROBE_PORTS */ - - .trig(trig), - - .addr_i(fsm_reg_trig_blk_addr), - .data_i(fsm_reg_trig_blk_data), - .rw_i(fsm_reg_trig_blk_rw), - .valid_i(fsm_reg_trig_blk_valid), - - .addr_o(trig_blk_block_mem_addr), - .data_o(trig_blk_block_mem_data), - .rw_o(trig_blk_block_mem_rw), - .valid_o(trig_blk_block_mem_valid)); - - reg [15:0] trig_blk_block_mem_addr; - reg [15:0] trig_blk_block_mem_data; - reg trig_blk_block_mem_rw; - reg trig_blk_block_mem_valid; - - // sample memory - block_memory #( - .BASE_ADDR(/* BLOCK_MEMORY_BASE_ADDR */), - .WIDTH(TOTAL_PROBE_WIDTH), - .DEPTH(SAMPLE_DEPTH) - ) block_mem ( - .clk(clk), - - // input port - .addr_i(trig_blk_block_mem_addr), - .data_i(trig_blk_block_mem_data), - .rw_i(trig_blk_block_mem_rw), - .valid_i(trig_blk_block_mem_valid), - - // output port - .addr_o(addr_o), - .data_o(data_o), - .rw_o(rw_o), - .valid_o(valid_o), - - // BRAM itself - .user_clk(clk), - .user_addr(bram_addr), - .user_din(probes_concat), - .user_dout(), - .user_we(bram_we)); -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/logic_analyzer_fsm_registers.v b/src/manta/la_core/logic_analyzer_fsm_registers.v deleted file mode 100644 index d35bcfb..0000000 --- a/src/manta/la_core/logic_analyzer_fsm_registers.v +++ /dev/null @@ -1,75 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module logic_analyzer_fsm_registers( - input wire clk, - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o, - - // registers - input wire [3:0] state, - output reg [15:0] trigger_loc, - output reg [1:0] trigger_mode, - output reg request_start, - output reg request_stop, - input wire [ADDR_WIDTH-1:0] read_pointer, - input wire [ADDR_WIDTH-1:0] write_pointer - ); - - initial trigger_loc = 0; - initial trigger_mode = 0; - initial request_start = 0; - initial request_stop = 0; - - parameter BASE_ADDR = 0; - localparam MAX_ADDR = BASE_ADDR + 5; - parameter SAMPLE_DEPTH = 0; - parameter ADDR_WIDTH = $clog2(SAMPLE_DEPTH); - - always @(posedge clk) begin - addr_o <= addr_i; - data_o <= data_i; - rw_o <= rw_i; - valid_o <= valid_i; - - // check if address is valid - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= MAX_ADDR)) begin - - // reads - if(!rw_i) begin - case (addr_i) - BASE_ADDR + 0: data_o <= state; - BASE_ADDR + 1: data_o <= trigger_mode; - BASE_ADDR + 2: data_o <= trigger_loc; - BASE_ADDR + 3: data_o <= request_start; - BASE_ADDR + 4: data_o <= request_stop; - BASE_ADDR + 5: data_o <= read_pointer; - BASE_ADDR + 6: data_o <= write_pointer; - endcase - end - - // writes - else begin - case (addr_i) - BASE_ADDR + 1: trigger_mode <= data_i; - BASE_ADDR + 2: trigger_loc <= data_i; - BASE_ADDR + 3: request_start <= data_i; - BASE_ADDR + 4: request_stop <= data_i; - endcase - end - end - end - - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/logic_analyzer_inst_tmpl.v b/src/manta/la_core/logic_analyzer_inst_tmpl.v deleted file mode 100644 index eebb872..0000000 --- a/src/manta/la_core/logic_analyzer_inst_tmpl.v +++ /dev/null @@ -1,14 +0,0 @@ -logic_analyzer /* INST_NAME */ ( - .clk(clk), - - .addr_i(), - .data_i(), - .rw_i(), - .valid_i(), - - /* NET_CONNS */ - - .addr_o(), - .data_o(), - .rw_o(), - .valid_o()); \ No newline at end of file diff --git a/src/manta/la_core/logic_analyzer_playback_tmpl.v b/src/manta/la_core/logic_analyzer_playback_tmpl.v deleted file mode 100644 index e87228f..0000000 --- a/src/manta/la_core/logic_analyzer_playback_tmpl.v +++ /dev/null @@ -1,50 +0,0 @@ -/* -This playback module was generated with Manta /* VERSION */ on /* TIMESTAMP */ by /* USER */ - -If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! - -/* MODULE_NAME */ #(.MEM_FILE("capture.mem")) /* MODULE_NAME */_inst ( - .clk(clk), - .enable(1'b1), - - /* PORTS */); - -*/ - - -module /* MODULE_NAME */ ( - input wire clk, - - input wire enable, - output reg done, - - /* PROBE_DEC */); - - parameter MEM_FILE = ""; - localparam SAMPLE_DEPTH = /* SAMPLE_DEPTH */; - localparam TOTAL_PROBE_WIDTH = /* TOTAL_PROBE_WIDTH */; - - reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0]; - reg [$clog2(SAMPLE_DEPTH)-1:0] addr; - reg [TOTAL_PROBE_WIDTH-1:0] sample; - - assign done = (addr >= SAMPLE_DEPTH); - - initial begin - $readmemb(MEM_FILE, capture, 0, SAMPLE_DEPTH-1); - addr = 0; - end - - always @(posedge clk) begin - if (enable && !done) begin - addr = addr + 1; - sample = capture[addr]; - /* PROBES_CONCAT */ = sample; - end - end -endmodule \ No newline at end of file diff --git a/src/manta/la_core/trigger.v b/src/manta/la_core/trigger.v deleted file mode 100644 index 05939e1..0000000 --- a/src/manta/la_core/trigger.v +++ /dev/null @@ -1,45 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module trigger ( - input wire clk, - - input wire [INPUT_WIDTH-1:0] probe, - input wire [3:0] op, - input wire [INPUT_WIDTH-1:0] arg, - - output reg trig); - - parameter INPUT_WIDTH = 0; - - localparam DISABLE = 0; - localparam RISING = 1; - localparam FALLING = 2; - localparam CHANGING = 3; - localparam GT = 4; - localparam LT = 5; - localparam GEQ = 6; - localparam LEQ = 7; - localparam EQ = 8; - localparam NEQ = 9; - - reg [INPUT_WIDTH-1:0] probe_prev = 0; - always @(posedge clk) probe_prev <= probe; - - always @(*) begin - case (op) - RISING : trig = (probe > probe_prev); - FALLING : trig = (probe < probe_prev); - CHANGING : trig = (probe != probe_prev); - GT: trig = (probe > arg); - LT: trig = (probe < arg); - GEQ: trig = (probe >= arg); - LEQ: trig = (probe <= arg); - EQ: trig = (probe == arg); - NEQ: trig = (probe != arg); - default: trig = 0; - endcase - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/trigger_block_def_tmpl.v b/src/manta/la_core/trigger_block_def_tmpl.v deleted file mode 100644 index 39af04f..0000000 --- a/src/manta/la_core/trigger_block_def_tmpl.v +++ /dev/null @@ -1,62 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module trigger_block ( - input wire clk, - - // probes - /* PROBE_PORTS */ - - // trigger - output reg trig, - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o); - - parameter BASE_ADDR = 0; - localparam MAX_ADDR = /* MAX_ADDR */; - - // trigger configuration registers - // - each probe gets an operation and a compare register - // - at the end we OR them all together. along with any custom probes the user specs - - /* TRIGGER_MODULE_INSTS */ - - /* COMBINE_INDIV_TRIGGERS */ - - // perform register operations - always @(posedge clk) begin - addr_o <= addr_i; - data_o <= data_i; - rw_o <= rw_i; - valid_o <= valid_i; - - if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + MAX_ADDR) ) begin - - // reads - if(valid_i && !rw_i) begin - case (addr_i) - /* READ_CASE_STATEMENT_BODY */ - endcase - end - - // writes - else if(valid_i && rw_i) begin - case (addr_i) - /* WRITE_CASE_STATEMENT_BODY */ - endcase - end - end - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/la_core/trigger_block_inst_tmpl.v b/src/manta/la_core/trigger_block_inst_tmpl.v deleted file mode 100644 index f796fa2..0000000 --- a/src/manta/la_core/trigger_block_inst_tmpl.v +++ /dev/null @@ -1,11 +0,0 @@ -/* OP_DEC */ -/* ARG_DEC */ -/* TRIG_DEC */ - -trigger #(.INPUT_WIDTH(/* INPUT_WIDTH */)) /* NAME */ ( - .clk(clk), - - .probe(/* PROBE */), - .op(/* OP */), - .arg(/* ARG */), - .trig(/* TRIG */)); diff --git a/src/manta/logic_analyzer_core.py b/src/manta/logic_analyzer_core.py new file mode 100644 index 0000000..4acedd5 --- /dev/null +++ b/src/manta/logic_analyzer_core.py @@ -0,0 +1,558 @@ +from amaranth import * +from warnings import warn +from .utils import * +from .io_core import IOCore +from .memory_core import ReadOnlyMemoryCore +from math import ceil, log2 + + +class LogicAnalyzerCore(Elaboratable): + """ """ + + def __init__(self, config, base_addr, interface): + self.config = config + self.base_addr = base_addr + self.interface = interface + + self.check_config(config) + + # State Machine Values + self.states = { + "IDLE": 0, + "MOVE_TO_POSITION": 1, + "IN_POSITION": 2, + "CAPTURING": 3, + "CAPTURED": 4, + } + + # Trigger Modes + self.trigger_modes = {"SINGLE_SHOT": 0, "INCREMENTAL": 1, "IMMEDIATE": 2} + + # Trigger operations + self.operations = { + "DISABLE": 0, + "RISING": 1, + "FALLING": 2, + "CHANGING": 3, + "GT": 4, + "LT": 5, + "GEQ": 6, + "LEQ": 7, + "EQ": 8, + "NEQ": 9, + } + + self.registers = self.make_registers(self.base_addr) + self.sample_mem = self.make_sample_mem(self.registers.max_addr) + self.define_signals() + + def check_config(self, config): + # Check for unrecognized options + valid_options = [ + "type", + "sample_depth", + "probes", + "triggers", + "trigger_loc", + "trigger_mode", + ] + for option in config: + if option not in valid_options: + warn(f"Ignoring unrecognized option '{option}' in Logic Analyzer.") + + # Check sample depth is provided and positive + if "sample_depth" not in config: + raise ValueError("Logic Analyzer must have sample_depth specified.") + + if not isinstance(config["sample_depth"], int): + raise ValueError("Logic Analyzer sample_depth must be an integer.") + + if config["sample_depth"] <= 0: + raise ValueError("Logic Analyzer sample_depth must be positive.") + + # Check probes + if "probes" not in config: + raise ValueError("Logic Analyzer must have at least one probe specified.") + + if len(config["probes"]) == 0: + raise ValueError("Logic Analyzer must have at least one probe specified.") + + for name, width in config["probes"].items(): + if width < 0: + raise ValueError(f"Width of probe {name} must be positive.") + + # Check triggers + if "triggers" not in config: + raise ValueError("Logic Analyzer must have at least one trigger specified.") + + if len(config["triggers"]) == 0: + raise ValueError("Logic Analyzer must have at least one trigger specified.") + + # Check trigger location + if "trigger_loc" in config: + if not isinstance(config["trigger_loc"], int): + raise ValueError("Trigger location must be an integer.") + + if config["trigger_loc"] < 0: + raise ValueError("Trigger location must be positive.") + + if config["trigger_loc"] > config["sample_depth"]: + raise ValueError("Trigger location cannot exceed sample depth.") + + # Check trigger mode + if "trigger_mode" in config: + valid_modes = ["single_shot", "incremental", "immediate"] + if config["trigger_mode"] not in valid_modes: + raise ValueError( + f"Unrecognized trigger mode {config['trigger_mode']} provided." + ) + + # Check triggers themselves + for trigger in config["triggers"]: + if not isinstance(trigger, str): + raise ValueError("Trigger must be specified with a string.") + + # Trigger conditions may be composed of either two or three components, + # depending on the operation specified. In the case of operations that + # don't need an argument (like DISABLE, RISING, FALLING, CHANGING) or + # three statements in + + # Check the trigger operations + components = trigger.strip().split(" ") + if len(components) == 2: + name, op = components + if op not in ["DISABLE", "RISING", "FALLING", "CHANGING"]: + raise ValueError( + f"Unable to interpret trigger condition '{trigger}'." + ) + + elif len(components) == 3: + name, op, arg = components + if op not in ["GT", "LT", "GEQ", "LEQ", "EQ", "NEQ"]: + raise ValueError( + f"Unable to interpret trigger condition '{trigger}'." + ) + + else: + raise ValueError(f"Unable to interpret trigger condition '{trigger}'.") + + # Check probe names + if components[0] not in config["probes"]: + raise ValueError(f"Unknown probe name '{components[0]}' specified.") + + def define_signals(self): + # Bus Input + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal(1) + self.valid_i = Signal(1) + + # Bus Output + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal(1) + self.valid_o = Signal(1) + + # Probes + self.probe_signals = {} + for name, width in self.config["probes"].items(): + self.probe_signals[name] = { + "top_level": Signal(width), + "prev": Signal(width), + "trigger_arg": getattr(self.registers, f"{name}_arg"), + "trigger_op": getattr(self.registers, f"{name}_op"), + "triggered": Signal(1), + } + + # Global trigger. High if any probe is triggered. + self.trig = Signal(1) + + def make_registers(self, base_addr): + # The logic analyzer uses an IO core to handle inputs to the FSM and trigger comparators + register_config = { + "inputs": { + "state": 4, + "read_pointer": ceil(log2(self.config["sample_depth"])), + "write_pointer": ceil(log2(self.config["sample_depth"])), + }, + "outputs": { + "trigger_loc": ceil(log2(self.config["sample_depth"])), + "trigger_mode": 2, + "request_start": 1, + "request_stop": 1, + }, + } + + for name, width in self.config["probes"].items(): + register_config["outputs"][name + "_arg"] = width + register_config["outputs"][name + "_op"] = 4 + + return IOCore(register_config, base_addr, self.interface) + + def make_sample_mem(self, base_addr): + sample_mem_config = { + "width": sum(self.config["probes"].values()), + "depth": self.config["sample_depth"], + } + + return ReadOnlyMemoryCore(sample_mem_config, base_addr, self.interface) + + def run_triggers(self, m): + # Run the trigger for each individual probe + for name, attrs in self.probe_signals.items(): + top_level = attrs["top_level"] + prev = attrs["prev"] + trigger_arg = attrs["trigger_arg"] + trigger_op = attrs["trigger_op"] + triggered = attrs["triggered"] + + # Save the previous value to a register so we can do rising/falling edge detection later! + m.d.sync += prev.eq(top_level) + + with m.If(trigger_op == self.operations["DISABLE"]): + m.d.comb += triggered.eq(0) + + with m.Elif(trigger_op == self.operations["RISING"]): + m.d.comb += triggered.eq((top_level) & (~prev)) + + with m.Elif(trigger_op == self.operations["FALLING"]): + m.d.comb += triggered.eq((~top_level) & (prev)) + + with m.Elif(trigger_op == self.operations["CHANGING"]): + m.d.comb += triggered.eq(top_level != prev) + + with m.Elif(trigger_op == self.operations["GT"]): + m.d.comb += triggered.eq(top_level > trigger_arg) + + with m.Elif(trigger_op == self.operations["LT"]): + m.d.comb += triggered.eq(top_level < trigger_arg) + + with m.Elif(trigger_op == self.operations["GEQ"]): + m.d.comb += triggered.eq(top_level >= trigger_arg) + + with m.Elif(trigger_op == self.operations["LEQ"]): + m.d.comb += triggered.eq(top_level <= trigger_arg) + + with m.Elif(trigger_op == self.operations["EQ"]): + m.d.comb += triggered.eq(top_level == trigger_arg) + + with m.Elif(trigger_op == self.operations["NEQ"]): + m.d.comb += triggered.eq(top_level != trigger_arg) + + with m.Else(): + m.d.comb += triggered.eq(0) + + # Combine all the triggers + m.d.comb += self.trig.eq( + Cat(attrs["triggered"] for attrs in self.probe_signals.values()).any() + ) + + def run_state_machine(self, m): + self.prev_request_start = Signal(1) + self.prev_request_stop = Signal(1) + + # Rising edge detection for start/stop requests + m.d.sync += self.prev_request_start.eq(self.registers.request_start) + m.d.sync += self.prev_request_stop.eq(self.registers.request_stop) + + m.d.comb += self.sample_mem.user_addr.eq(self.registers.write_pointer) + + with m.If(self.registers.state == self.states["IDLE"]): + m.d.sync += self.registers.write_pointer.eq(0) + m.d.sync += self.registers.read_pointer.eq(0) + m.d.sync += self.sample_mem.user_we.eq(0) # or something like this + + with m.If((self.registers.request_start) & (~self.prev_request_start)): + m.d.sync += self.registers.state.eq(self.states["MOVE_TO_POSITION"]) + + with m.Elif(self.registers.state == self.states["MOVE_TO_POSITION"]): + m.d.sync += self.registers.write_pointer.eq( + self.registers.write_pointer + 1 + ) + m.d.sync += self.sample_mem.user_we.eq(1) + + with m.If(self.registers.write_pointer == self.registers.trigger_loc): + with m.If(self.trig): + m.d.sync += self.registers.state.eq(self.states["CAPTURING"]) + + with m.Else(): + m.d.sync += self.registers.state.eq(self.states["IN_POSITION"]) + + with m.Elif(self.registers.state == self.states["IN_POSITION"]): + m.d.sync += self.registers.write_pointer.eq( + (self.registers.write_pointer + 1) % self.config["sample_depth"] + ) + m.d.sync += self.registers.read_pointer.eq( + (self.registers.read_pointer + 1) % self.config["sample_depth"] + ) + m.d.sync += self.sample_mem.user_we.eq(1) + + with m.If(self.trig): + m.d.sync += self.registers.state.eq(self.states["CAPTURING"]) + + with m.Elif(self.registers.state == self.states["CAPTURING"]): + with m.If(self.registers.write_pointer == self.registers.read_pointer): + m.d.sync += self.sample_mem.user_we.eq(0) + m.d.sync += self.registers.state.eq(self.states["CAPTURED"]) + + with m.Else(): + m.d.sync += self.registers.write_pointer.eq( + (self.registers.write_pointer + 1) % self.config["sample_depth"] + ) + + with m.If((self.registers.request_stop) & (~self.prev_request_stop)): + m.d.sync += self.registers.state.eq(self.states["IDLE"]) + + def elaborate(self, platform): + m = Module() + + # Add registers and sample memory as submodules + m.submodules["registers"] = self.registers + m.submodules["sample_mem"] = self.sample_mem + + # Concat all the probes together, and feed to input of sample memory + # (it is necessary to reverse the order such that first probe occupies + # the lowest location in memory) + m.d.comb += self.sample_mem.user_data.eq( + Cat([p["top_level"] for p in self.probe_signals.values()][::-1]) + ) + + self.run_state_machine(m) + self.run_triggers(m) + + # Wire internal modules + m.d.comb += [ + self.registers.addr_i.eq(self.addr_i), + self.registers.data_i.eq(self.data_i), + self.registers.rw_i.eq(self.rw_i), + self.registers.valid_i.eq(self.valid_i), + self.sample_mem.addr_i.eq(self.registers.addr_o), + self.sample_mem.data_i.eq(self.registers.data_o), + self.sample_mem.rw_i.eq(self.registers.rw_o), + self.sample_mem.valid_i.eq(self.registers.valid_o), + self.addr_o.eq(self.sample_mem.addr_o), + self.data_o.eq(self.sample_mem.data_o), + self.rw_o.eq(self.sample_mem.rw_o), + self.valid_o.eq(self.sample_mem.valid_o), + ] + + return m + + def get_top_level_ports(self): + return [p["top_level"] for p in self.probe_signals.values()] + + def get_max_addr(self): + return self.sample_mem.get_max_addr() + + def set_triggers(self): + # reset all triggers to zero + for name in self.probe_signals.keys(): + self.registers.set_probe(name + "_op", 0) + self.registers.set_probe(name + "_arg", 0) + + # set triggers + for trigger in self.config["triggers"]: + components = trigger.strip().split(" ") + + # Handle triggers that don't need an argument + if len(components) == 2: + name, op = components + self.registers.set_probe(name + "_op", self.operations[op]) + + # Handle triggers that do need an argument + elif len(components) == 3: + name, op, arg = components + self.registers.set_probe(name + "_op", self.operations[op]) + self.registers.set_probe(name + "_arg", int(arg)) + + def capture(self, verbose=False): + print_if_verbose = lambda x: print(x) if verbose else None + + # If core is not in IDLE state, request that it return to IDLE + print_if_verbose(" -> Resetting core...") + state = self.registers.get_probe("state") + if state != self.states["IDLE"]: + self.registers.set_probe("request_stop", 0) + self.registers.set_probe("request_stop", 1) + self.registers.set_probe("request_stop", 0) + + if self.registers.get_probe("state") != self.states["IDLE"]: + raise ValueError("Logic analyzer did not reset to IDLE state.") + + # Set triggers + print_if_verbose(" -> Setting triggers...") + self.set_triggers() + + # Set trigger mode, default to single-shot if user didn't specify a mode + print_if_verbose(" -> Setting trigger mode...") + if "trigger_mode" in self.config: + self.registers.set_probe("trigger_mode", self.config["trigger_mode"]) + + else: + self.registers.set_probe("trigger_mode", self.trigger_modes["SINGLE_SHOT"]) + + # Set trigger location + print_if_verbose(" -> Setting trigger location...") + self.registers.set_probe("trigger_loc", self.config["trigger_loc"]) + + # Send a start request to the state machine + print_if_verbose(" -> Starting capture...") + self.registers.set_probe("request_start", 1) + self.registers.set_probe("request_start", 0) + + # Poll the state machine's state, and wait for the capture to complete + print_if_verbose(" -> Waiting for capture to complete...") + while self.registers.get_probe("state") != self.states["CAPTURED"]: + pass + + # Read out the entirety of the sample memory + print_if_verbose(" -> Reading sample memory contents...") + addrs = list(range(self.config["sample_depth"])) + raw_capture = self.sample_mem.read_from_user_addr(addrs) + + # Revolve the memory around the read_pointer, such that all the beginning + # of the caputure is at the first element + print_if_verbose(" -> Checking read pointer and revolving memory...") + read_pointer = self.registers.get_probe("read_pointer") + + data = raw_capture[read_pointer:] + raw_capture[:read_pointer] + return LogicAnalyzerCapture(data, self.config) + + +class LogicAnalyzerCapture: + def __init__(self, data, config): + self.data = data + self.config = config + + def get_trigger_loc(self): + return self.config["trigger_loc"] + + def get_trace(self, probe_name): + # sum up the widths of all the probes below this one + lower = 0 + for name, width in self.config["probes"].items(): + if name == probe_name: + break + + lower += width + + # add the width of the probe we'd like + upper = lower + self.config["probes"][probe_name] + + total_probe_width = sum(self.config["probes"].values()) + binary = [f"{d:0{total_probe_width}b}" for d in self.data] + return [int(b[lower:upper], 2) for b in binary] + + def export_vcd(self, path): + from vcd import VCDWriter + from datetime import datetime + + # Use the same datetime format that iVerilog uses + timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y") + vcd_file = open(path, "w") + + with VCDWriter(vcd_file, "10 ns", timestamp, "manta") as writer: + # each probe has a name, width, and writer associated with it + signals = [] + for name, width in self.config["probes"].items(): + signal = { + "name": name, + "width": width, + "data": self.get_trace(name), + "var": writer.register_var("manta", name, "wire", size=width), + } + signals.append(signal) + + clock = writer.register_var("manta", "clk", "wire", size=1) + trigger = writer.register_var("manta", "trigger", "wire", size=1) + + # add the data to each probe in the vcd file + for timestamp in range(0, 2 * len(self.data)): + # run the clock + writer.change(clock, timestamp, timestamp % 2 == 0) + + # set the trigger + triggered = (timestamp // 2) >= self.get_trigger_loc() + writer.change(trigger, timestamp, triggered) + + # add other signals + for signal in signals: + var = signal["var"] + sample = signal["data"][timestamp // 2] + + writer.change(var, timestamp, sample) + + vcd_file.close() + + def export_playback_module(self, path): + return LogicAnalyzerPlayback(self.data, self.config) + + def export_playback_verilog(self, path): + la = LogicAnalyzerPlayback(self.data, self.config) + from amaranth.back import verilog + + with open(path, "w") as f: + f.write( + verilog.convert( + la, + name="logic_analyzer_playback", + ports=la.get_top_level_ports(), + strip_internal_attrs=True, + ) + ) + + +class LogicAnalyzerPlayback(Elaboratable): + def __init__(self, data, config): + self.data = data + self.config = config + + # State Machine + self.enable = Signal(1) + self.done = Signal(1) + + # Top-Level Probe signals + self.top_level_probes = {} + for name, width in self.config["probes"].items(): + self.top_level_probes[name] = Signal(width, name=name) + + # Instantiate memory + self.mem = Memory( + depth=self.config["sample_depth"], + width=sum(self.config["probes"].values()), + init=self.data, + ) + + self.read_port = self.mem.read_port() + + def elaborate(self, platform): + m = Module() + m.submodules["mem"] = self.mem + m.d.comb += self.read_port.en.eq(1) + + # Assign the probe values by part-selecting from the data port + lower = 0 + for name, width in reversed(self.config["probes"].items()): + signal = self.top_level_probes[name] + + # Set output probe to zero if we're not + with m.If(~self.done): + m.d.comb += signal.eq(self.read_port.data[lower : lower + width]) + + with m.Else(): + m.d.comb += signal.eq(0) + + lower += width + + # Iterate through the samples if saved + with m.If((self.enable) & (~self.done)): + with m.If(self.read_port.addr < (self.config["sample_depth"] - 1)): + m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1) + + with m.Else(): + m.d.sync += self.done.eq(1) + + return m + + def get_top_level_ports(self): + return [self.enable, self.done] + list(self.top_level_probes.values()) diff --git a/src/manta/manta.py b/src/manta/manta.py new file mode 100644 index 0000000..073f55a --- /dev/null +++ b/src/manta/manta.py @@ -0,0 +1,170 @@ +from amaranth import * +from warnings import warn +from .uart import UARTInterface + +# from .ethernet import EthernetInterface +from .io_core import IOCore +from .memory_core import ReadOnlyMemoryCore +from .logic_analyzer_core import LogicAnalyzerCore + + +class Manta(Elaboratable): + def __init__(self, config): + # load config from either a configuration file or a dictionary. Users primarily use the + # config file, but the dictionary is included for internal tests. + + if isinstance(config, str): + self.config = self.read_config_file(config) + + if isinstance(config, dict): + self.config = config + + self.check_config() + + self.interface = self.get_interface() + self.cores = self.get_cores() + self.add_friendly_core_names() + + def read_config_file(self, path): + """ + Take path to configuration file, and retun the configuration as a python list/dict object. + """ + + extension = path.split(".")[-1] + + if "json" in extension: + with open(path, "r") as f: + import json + + return json.load(f) + + elif "yaml" in extension or "yml" in extension: + with open(path, "r") as f: + import yaml + + return yaml.safe_load(f) + + else: + raise ValueError("Unable to recognize configuration file extension.") + + def check_config(self): + if "cores" not in self.config: + raise ValueError("No cores specified in configuration file.") + + if not len(self.config["cores"]) > 0: + raise ValueError("Must specify at least one core.") + + for name, attrs in self.config["cores"].items(): + # make sure core type is specified + if "type" not in attrs: + raise ValueError(f"No type specified for core {name}.") + + if attrs["type"] not in ["logic_analyzer", "io", "memory_read_only"]: + raise ValueError(f"Unrecognized core type specified for {name}.") + + def get_interface(self): + if "uart" in self.config: + return UARTInterface(self.config["uart"]) + + elif "ethernet" in self.config: + return EthernetInterface(self.config["ethernet"]) + + else: + raise ValueError("Unrecognized interface specified.") + + def get_cores(self): + """ """ + + cores = {} + base_addr = 0 + for name, attrs in self.config["cores"].items(): + if attrs["type"] == "io": + core = IOCore(attrs, base_addr, self.interface) + + elif attrs["type"] == "logic_analyzer": + core = LogicAnalyzerCore(attrs, base_addr, self.interface) + + elif attrs["type"] == "memory_read_only": + core = ReadOnlyMemoryCore(attrs, base_addr, self.interface) + + # make sure we're not out of address space + if core.get_max_addr() > (2**16) - 1: + raise ValueError( + f"Ran out of address space to allocate to core {name}." + ) + + # Make the next core's base address start one address after the previous one's + base_addr = core.get_max_addr() + 1 + cores[name] = core + + return cores + + def add_friendly_core_names(self): + """ + Add cores to the instance under a friendly name - ie, a core named `my_core` belonging + to a Manta instance `m` could be obtained with `m.cores["my_core"]`, but this allows + it to be obtained with `m.my_core`. Which is way nicer. + """ + + for name, instance in self.cores.items(): + if not hasattr(self, name): + setattr(self, name, instance) + + else: + raise ValueError( + "Cannot add object to Manta instance - name is already taken!" + ) + + def elaborate(self, platform): + # make a module object + # add all the submodules + # connect them together, which consists of: + # connect interface to first core + # connect cores to each other + # connect interface to last core + + m = Module() + + # Add interface as submodule + m.submodules["interface"] = self.interface + + # Add all cores as submodules + for name, instance in self.cores.items(): + m.submodules[name] = instance + + # Connect first/last cores to interface output/input respectively + core_instances = list(self.cores.values()) + first_core = core_instances[0] + last_core = core_instances[-1] + m.d.comb += [ + first_core.addr_i.eq(self.interface.addr_o), + first_core.data_i.eq(self.interface.data_o), + first_core.rw_i.eq(self.interface.rw_o), + first_core.valid_i.eq(self.interface.valid_o), + self.interface.addr_i.eq(last_core.addr_o), + self.interface.data_i.eq(last_core.data_o), + self.interface.rw_i.eq(last_core.rw_o), + self.interface.valid_i.eq(last_core.valid_o), + ] + + # Connect output of ith core to input of (i+1)th core + for i in range(len(core_instances) - 1): + ith_core = core_instances[i] + i_plus_oneth_core = core_instances[i + 1] + + m.d.comb += [ + i_plus_oneth_core.addr_i.eq(ith_core.addr_o), + i_plus_oneth_core.data_i.eq(ith_core.data_o), + i_plus_oneth_core.rw_i.eq(ith_core.rw_o), + i_plus_oneth_core.valid_i.eq(ith_core.valid_o), + ] + + return m + + def get_top_level_ports(self): + ports = self.interface.get_top_level_ports() + + for name, instance in self.cores.items(): + ports += instance.get_top_level_ports() + + return ports diff --git a/src/manta/manta_def_tmpl.v b/src/manta/manta_def_tmpl.v deleted file mode 100644 index 252a858..0000000 --- a/src/manta/manta_def_tmpl.v +++ /dev/null @@ -1,34 +0,0 @@ -/* -This module was generated with Manta /* VERSION */ on /* TIMESTAMP */ by /* USER */ - -If this breaks or if you've got spicy formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! - -manta manta_inst ( - .clk(clk), - - /* EX_INST_PORTS */); - -*/ - -module manta ( - input wire clk, - - /* TOP_LEVEL_PORTS */); - - - /* INTERFACE_RX */ - - /* CORE_CHAIN */ - - /* INTERFACE_TX */ - -endmodule - -/* ---- Module Definitions ---- */ - -/* MODULE_DEFS */ \ No newline at end of file diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py new file mode 100644 index 0000000..cf4d9ae --- /dev/null +++ b/src/manta/memory_core.py @@ -0,0 +1,205 @@ +from amaranth import * +from warnings import warn +from .utils import * +from math import ceil + + +class ReadOnlyMemoryCore(Elaboratable): + def __init__(self, config, base_addr, interface): + self.config = config + self.base_addr = base_addr + self.interface = interface + + self.check_config(config) + + self.depth = self.config["depth"] + self.width = self.config["width"] + self.max_addr = self.base_addr + (self.depth * ceil(self.width / 16)) + + self.define_signals() + self.define_mems() + + def check_config(self, config): + # Check for unrecognized options + valid_options = ["type", "depth", "width"] + for option in config: + if option not in valid_options: + warn(f"Ignoring unrecognized option '{option}' in memory core.") + + # Check depth is provided and positive + if "depth" not in config: + raise ValueError("Depth of memory core must be specified.") + + if not isinstance(config["depth"], int): + raise ValueError("Depth of memory core must be an integer.") + + if config["depth"] <= 0: + raise ValueError("Depth of memory core must be positive. ") + + # Check width is provided and positive + if "width" not in config: + raise ValueError("Width of memory core must be specified.") + + if not isinstance(config["width"], int): + raise ValueError("Width of memory core must be an integer.") + + if config["width"] <= 0: + raise ValueError("Width of memory core must be positive. ") + + def define_signals(self): + # Bus Input + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal(1) + self.valid_i = Signal(1) + + # Bus Pipelining + self.addr_pipe = [Signal(16) for _ in range(3)] + self.data_pipe = [Signal(16) for _ in range(3)] + self.rw_pipe = [Signal(1) for _ in range(3)] + self.valid_pipe = [Signal(1) for _ in range(3)] + + # Bus Output + self.addr_o = Signal(16, reset=0) + self.data_o = Signal(16, reset=0) + self.rw_o = Signal(1, reset=0) + self.valid_o = Signal(1, reset=0) + + # User Port + self.user_addr = Signal(range(self.depth)) + self.user_data = Signal(self.width) + self.user_we = Signal(1) + + def pipeline_bus(self, m): + # Pipelining + m.d.sync += self.addr_pipe[0].eq(self.addr_i) + m.d.sync += self.data_pipe[0].eq(self.data_i) + m.d.sync += self.rw_pipe[0].eq(self.rw_i) + m.d.sync += self.valid_pipe[0].eq(self.valid_i) + + for i in range(1, 3): + m.d.sync += self.addr_pipe[i].eq(self.addr_pipe[i - 1]) + m.d.sync += self.data_pipe[i].eq(self.data_pipe[i - 1]) + m.d.sync += self.rw_pipe[i].eq(self.rw_pipe[i - 1]) + m.d.sync += self.valid_pipe[i].eq(self.valid_pipe[i - 1]) + + m.d.sync += self.addr_o.eq(self.addr_pipe[2]) + m.d.sync += self.data_o.eq(self.data_pipe[2]) + m.d.sync += self.rw_o.eq(self.rw_pipe[2]) + m.d.sync += self.valid_o.eq(self.valid_pipe[2]) + + def define_mems(self): + # ok there's three cases: + # 1. integer number of 16 bit mems + # 2. integer number of 16 bit mems + partial mem + # 3. just the partial mem (width < 16) + + # Only one, partial-width memory is needed + if self.width < 16: + self.mems = [Memory(depth=self.depth, width=self.width)] + + # Only full-width memories are needed + elif self.width % 16 == 0: + self.mems = [ + Memory(depth=self.depth, width=16) for _ in range(self.width // 16) + ] + + # Both full-width and partial memories are needed + else: + self.mems = [ + Memory(depth=self.depth, width=16) for i in range(self.width // 16) + ] + self.mems += [Memory(depth=self.depth, width=self.width % 16)] + + def handle_read_ports(self, m): + # These are tied to the bus + for i, mem in enumerate(self.mems): + read_port = mem.read_port() + m.d.comb += read_port.en.eq(1) + + start_addr = self.base_addr + (i * self.depth) + stop_addr = start_addr + self.depth - 1 + + # Throw BRAM operations into the front of the pipeline + with m.If( + (self.valid_i) + & (~self.rw_i) + & (self.addr_i >= start_addr) + & (self.addr_i <= stop_addr) + ): + m.d.sync += read_port.addr.eq(self.addr_i - start_addr) + + # Pull BRAM reads from the back of the pipeline + with m.If( + (self.valid_pipe[2]) + & (~self.rw_pipe[2]) + & (self.addr_pipe[2] >= start_addr) + & (self.addr_pipe[2] <= stop_addr) + ): + m.d.sync += self.data_o.eq(read_port.data) + + def handle_write_ports(self, m): + # These are given to the user + for i, mem in enumerate(self.mems): + write_port = mem.write_port() + + m.d.comb += write_port.addr.eq(self.user_addr) + m.d.comb += write_port.data.eq(self.user_data[16 * i : 16 * (i + 1)]) + m.d.comb += write_port.en.eq(self.user_we) + + def elaborate(self, platform): + m = Module() + + # Add memories as submodules + for i, mem in enumerate(self.mems): + m.submodules[f"mem_{i}"] = mem + + self.pipeline_bus(m) + self.handle_read_ports(m) + self.handle_write_ports(m) + return m + + def get_top_level_ports(self): + return [self.user_addr, self.user_data, self.user_we] + + def get_max_addr(self): + return self.max_addr + + def read_from_user_addr(self, addrs): + """ + Read the memory stored at the provided address, as seen from the user side. + """ + + # Convert user address space to bus address space + # (for instance, for a core with base address 10 and width 33, + # reading from address 4 is actually a read from address 14 and address 14 + depth, and address 14 + 2*depth) + + if isinstance(addrs, int): + return self.read_from_user_addr([addrs])[0] + + bus_addrs = [] + for addr in addrs: + bus_addrs += [ + addr + self.base_addr + i * self.depth for i in range(len(self.mems)) + ] + + datas = self.interface.read(bus_addrs) + data_chunks = split_into_chunks(datas, len(self.mems)) + return [words_to_value(chunk) for chunk in data_chunks] + + # def write_to_user_addr(self, addrs, datas): + # """ + # Read from the address + # """ + + # bus_addrs = [] + # for addr in addrs: + # bus_addrs += [ + # addr + self.base_addr + i * self.depth for i in range(len(self.mems)) + # ] + + # bus_datas = [] + # for data in datas: + # bus_datas += value_to_words(data) + + # self.interface.write(bus_addrs, bus_datas) diff --git a/src/manta/uart.py b/src/manta/uart.py new file mode 100644 index 0000000..cba6337 --- /dev/null +++ b/src/manta/uart.py @@ -0,0 +1,583 @@ +from amaranth import * +from amaranth.lib.data import ArrayLayout +from warnings import warn +from .utils import * +from serial import Serial + + +class UARTInterface(Elaboratable): + def __init__(self, config): + self.config = config + self.check_config(self.config) + + self.port = config["port"] + self.clock_freq = config["clock_freq"] + self.baudrate = config["baudrate"] + self.clocks_per_baud = int(self.clock_freq // self.baudrate) + + self.define_signals() + + # Set chunk_size, which is the max amount of bytes that the core will + # dump to the OS driver at a time. Since the FPGA will return bytes + # almost instantaneously, this prevents the OS's input buffer from + # overflowing, and dropping bytes. + self.chunk_size = 256 # in bytes + if "chunk_size" in config: + self.chunk_size = config["chunk_size"] + + def check_config(self, config): + # Warn if unrecognized options have been given + recognized_options = ["port", "clock_freq", "baudrate", "chunk_size"] + for option in config: + if option not in recognized_options: + warn( + f"Ignoring unrecognized option '{option}' in UART interface config." + ) + + # Ensure a serial port has been given + if "port" not in config: + raise ValueError("No serial port provided to UART interface.") + + # Ensure clock frequency is provided and positive + if "clock_freq" not in config: + raise ValueError("No clock frequency provided to UART interface.") + + if config["clock_freq"] <= 0: + raise ValueError("Non-positive clock frequency provided to UART interface.") + + # Check that baudrate is provided and positive + if "baudrate" not in config: + raise ValueError("No baudrate provided to UART interface.") + + if config["baudrate"] <= 0: + raise ValueError("Non-positive baudrate provided to UART interface.") + + # Confirm the actual baudrate is within 5% of the target baudrate + clock_freq = config["clock_freq"] + baudrate = config["baudrate"] + clocks_per_baud = clock_freq // baudrate + actual_baudrate = clock_freq / clocks_per_baud + error = 100 * abs(actual_baudrate - baudrate) / baudrate + + if error > 5: + raise ValueError( + "UART interface is unable to match targeted baudrate with specified clock frequency." + ) + + def get_serial_device(self): + """ + Return an open PySerial serial device if one exists, otherwise, open one. + """ + if hasattr(self, "serial_device"): + return self.serial_device + + else: + if self.port != "auto": + self.serial_device = Serial(self.port, self.baudrate, timeout=1) + return self.serial_device + + else: + # Try to autodetect which port to use based on the PID/VID of the device attached. + # This looks for the PID/VID of the FT2232, the primary chip used on the icestick + # and Digilent dev boards. However, folks will likely want to connect other things + # in the future, so in the future we'll probably want to look for other chips as + # well. + + # The FT2232 exposes two serial ports - and for whatever reason it usually has the + # 0th device used for JTAG programming, and the 1st used for UART. So we'll grab + # the 1st. + + import serial.tools.list_ports + + ports = [] + for port in serial.tools.list_ports.comports(): + if (port.vid == 0x403) and (port.pid == 0x6010): + ports.append(port) + + if len(ports) != 2: + raise ValueError( + f"Expected to see two serial ports for FT2232 device, but instead see {len(ports)}." + ) + + if ports[0].serial_number != ports[1].serial_number: + raise ValueError( + f"Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices." + ) + + if ports[0].location > ports[1].location: + chosen_port = ports[0].device + + else: + chosen_port = ports[1].device + + self.serial_device = Serial(chosen_port, self.baudrate, timeout=1) + return self.serial_device + + def get_top_level_ports(self): + return [self.rx, self.tx] + + def read(self, addrs): + """ + Read the data stored in a set of address on Manta's internal memory. Addresses + must be specified as either integers or a list of integers. + """ + + # Handle a single integer address + if isinstance(addrs, int): + return self.read([addrs])[0] + + # Make sure all list elements are integers + if not all(isinstance(a, int) for a in addrs): + raise ValueError("Read address must be an integer or list of integers.") + + # Send read requests, and get responses + ser = self.get_serial_device() + addr_chunks = split_into_chunks(addrs, self.chunk_size) + datas = [] + + for addr_chunk in addr_chunks: + # Encode addrs into read requests + bytes_out = b"".join([f"R{a:04X}\r\n".encode("ascii") for a in addr_chunk]) + ser.write(bytes_out) + + # Read responses have the same length as read requests + bytes_in = ser.read(len(bytes_out)) + + if len(bytes_in) != len(bytes_out): + raise ValueError( + f"Only got {len(bytes_in)} out of {len(bytes_out)} bytes." + ) + + # Split received bytes into individual responses and decode + responses = split_into_chunks(bytes_in, 7) + data_chunk = [self.decode_read_response(r) for r in responses] + datas += data_chunk + + return datas + + def write(self, addrs, datas): + """ + Write the provided data into the provided addresses in Manta's internal memory. + Addresses and data must be specified as either integers or a list of integers. + """ + + # Handle a single integer address and data + if isinstance(addrs, int) and isinstance(datas, int): + return self.write([addrs], [datas]) + + # Make sure address and datas are all integers + if not isinstance(addrs, list) or not isinstance(datas, list): + raise ValueError( + "Write addresses and data must be an integer or list of integers." + ) + + if not all(isinstance(a, int) for a in addrs): + raise ValueError("Write addresses must be all be integers.") + + if not all(isinstance(d, int) for d in datas): + raise ValueError("Write data must all be integers.") + + # I'm not sure if it's necessary to split outputs into chunks + # I think the output buffer doesn't really drop stuff, just the input buffer + + # Encode addrs and datas into write requests + bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, datas)]) + bytes_out = bytes_out.encode("ascii") + ser = self.get_serial_device() + ser.write(bytes_out) + + def decode_read_response(self, response_bytes): + """ + Check that read response is formatted properly, and extract the encoded data if so. + """ + + # Make sure response is not empty + if response_bytes is None: + raise ValueError("Unable to decode read response - no bytes received.") + + # Make sure response is properly encoded + response_ascii = response_bytes.decode("ascii") + + if len(response_ascii) != 7: + raise ValueError( + "Unable to decode read response - wrong number of bytes received." + ) + + if response_ascii[0] != "D": + raise ValueError("Unable to decode read response - incorrect preamble.") + + for i in range(1, 5): + if response_ascii[i] not in "0123456789ABCDEF": + raise ValueError("Unable to decode read response - invalid data byte.") + + if response_ascii[5] != "\r": + raise ValueError("Unable to decode read response - incorrect EOL.") + + if response_ascii[6] != "\n": + raise ValueError("Unable to decode read response - incorrect EOL.") + + return int(response_ascii[1:5], 16) + + def define_signals(self): + self.rx = Signal() + self.tx = Signal() + + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal() + self.valid_o = Signal() + + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + def elaborate(self, platform): + # fancy submoduling and such goes in here + m = Module() + + m.submodules["uart_rx"] = uart_rx = UARTReceiver(self.clocks_per_baud) + m.submodules["bridge_rx"] = bridge_rx = RecieveBridge() + m.submodules["bridge_tx"] = bridge_tx = TransmitBridge() + m.submodules["uart_tx"] = uart_tx = UARTTransmitter(self.clocks_per_baud) + + m.d.comb += [ + # UART RX -> Internal Bus + uart_rx.rx.eq(self.rx), + bridge_rx.data_i.eq(uart_rx.data_o), + bridge_rx.valid_i.eq(uart_rx.valid_o), + self.data_o.eq(bridge_rx.data_o), + self.addr_o.eq(bridge_rx.addr_o), + self.rw_o.eq(bridge_rx.rw_o), + self.valid_o.eq(bridge_rx.valid_o), + # Internal Bus -> UART TX + bridge_tx.data_i.eq(self.data_i), + bridge_tx.rw_i.eq(self.rw_i), + bridge_tx.valid_i.eq(self.valid_i), + uart_tx.data_i.eq(bridge_tx.data_o), + uart_tx.start_i.eq(bridge_tx.start_o), + bridge_tx.done_i.eq(uart_tx.done_o), + self.tx.eq(uart_tx.tx), + ] + return m + + +class UARTReceiver(Elaboratable): + def __init__(self, clocks_per_baud): + self.clocks_per_baud = clocks_per_baud + + # Top-Level Ports + self.rx = Signal() + self.data_o = Signal(8, reset=0) + self.valid_o = Signal(1, reset=0) + + # Internal Signals + self.busy = Signal() + self.bit_index = Signal(range(10)) + self.baud_counter = Signal(range(2 * clocks_per_baud)) + + self.rx_d = Signal() + self.rx_q = Signal() + self.rx_q_prev = Signal() + + def elaborate(self, platform): + m = Module() + + # Two Flip-Flop Synchronizer + m.d.sync += [ + self.rx_d.eq(self.rx), + self.rx_q.eq(self.rx_d), + self.rx_q_prev.eq(self.rx_q), + ] + + m.d.sync += self.valid_o.eq(0) + + with m.If(~self.busy): + with m.If((~self.rx_q) & (self.rx_q_prev)): + m.d.sync += self.busy.eq(1) + m.d.sync += self.bit_index.eq(8) + m.d.sync += self.baud_counter.eq( + self.clocks_per_baud + (self.clocks_per_baud // 2) - 2 + ) + + with m.Else(): + with m.If(self.baud_counter == 0): + with m.If(self.bit_index == 0): + m.d.sync += self.valid_o.eq(1) + m.d.sync += self.busy.eq(0) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.baud_counter.eq(0) + + with m.Else(): + # m.d.sync += self.data_o.eq(Cat(self.rx_q, self.data_o[0:7])) + m.d.sync += self.data_o.eq(Cat(self.data_o[1:8], self.rx_q)) + m.d.sync += self.bit_index.eq(self.bit_index - 1) + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + + with m.Else(): + m.d.sync += self.baud_counter.eq(self.baud_counter - 1) + + return m + + +class RecieveBridge(Elaboratable): + def __init__(self): + # Top-Level Ports + self.data_i = Signal(8) + self.valid_i = Signal() + + self.addr_o = Signal(16, reset=0) + self.data_o = Signal(16, reset=0) + self.rw_o = Signal(1, reset=0) + self.valid_o = Signal(1, reset=0) + + # State Machine + self.IDLE_STATE = 0 + self.READ_STATE = 1 + self.WRITE_STATE = 2 + + # Internal Signals + self.buffer = Signal(ArrayLayout(4, 8), reset_less=True) + self.state = Signal(2, reset=self.IDLE_STATE) + self.byte_num = Signal(4, reset=0) + self.is_eol = Signal() + self.is_ascii_hex = Signal() + self.from_ascii_hex = Signal(8) + + def drive_ascii_signals(self, m): + # Decode 0-9 + with m.If((self.data_i >= 0x30) & (self.data_i <= 0x39)): + m.d.comb += self.is_ascii_hex.eq(1) + m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x30) + + # Decode A-F + with m.Elif((self.data_i >= 0x41) & (self.data_i <= 0x46)): + m.d.comb += self.is_ascii_hex.eq(1) + m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x41 + 10) + + with m.Else(): + m.d.comb += self.is_ascii_hex.eq(0) + m.d.comb += self.from_ascii_hex.eq(0) + + with m.If((self.data_i == ord("\r")) | (self.data_i == ord("\n"))): + m.d.comb += self.is_eol.eq(1) + + with m.Else(): + m.d.comb += self.is_eol.eq(0) + + def drive_output_bus(self, m): + with m.If( + (self.state == self.READ_STATE) & (self.byte_num == 4) & (self.is_eol) + ): + m.d.comb += self.addr_o.eq( + Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) + ) + m.d.comb += self.data_o.eq(0) + m.d.comb += self.valid_o.eq(1) + m.d.comb += self.rw_o.eq(0) + + with m.Elif( + (self.state == self.WRITE_STATE) & (self.byte_num == 8) & (self.is_eol) + ): + m.d.comb += self.addr_o.eq( + Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) + ) + m.d.comb += self.data_o.eq( + Cat(self.buffer[7], self.buffer[6], self.buffer[5], self.buffer[4]) + ) + m.d.comb += self.valid_o.eq(1) + m.d.comb += self.rw_o.eq(1) + + with m.Else(): + m.d.comb += self.addr_o.eq(0) + m.d.comb += self.data_o.eq(0) + m.d.comb += self.rw_o.eq(0) + m.d.comb += self.valid_o.eq(0) + + def drive_fsm(self, m): + with m.If(self.valid_i): + with m.If(self.state == self.IDLE_STATE): + m.d.sync += self.byte_num.eq(0) + + with m.If(self.data_i == ord("R")): + m.d.sync += self.state.eq(self.READ_STATE) + + with m.Elif(self.data_i == ord("W")): + m.d.sync += self.state.eq(self.WRITE_STATE) + + with m.If(self.state == self.READ_STATE): + # buffer bytes if we don't have enough + with m.If(self.byte_num < 4): + # if bytes aren't valid ASCII then return to IDLE state + with m.If(self.is_ascii_hex == 0): + m.d.sync += self.state.eq(self.IDLE_STATE) + + # otherwise buffer them + with m.Else(): + m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) + m.d.sync += self.byte_num.eq(self.byte_num + 1) + + with m.Else(): + m.d.sync += self.state.eq(self.IDLE_STATE) + + with m.If(self.state == self.WRITE_STATE): + # buffer bytes if we don't have enough + with m.If(self.byte_num < 8): + # if bytes aren't valid ASCII then return to IDLE state + with m.If(self.is_ascii_hex == 0): + m.d.sync += self.state.eq(self.IDLE_STATE) + + # otherwise buffer them + with m.Else(): + m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) + m.d.sync += self.byte_num.eq(self.byte_num + 1) + + with m.Else(): + m.d.sync += self.state.eq(self.IDLE_STATE) + pass + + def elaborate(self, platform): + m = Module() + + self.drive_ascii_signals(m) + self.drive_output_bus(m) + self.drive_fsm(m) + + return m + + +class UARTTransmitter(Elaboratable): + def __init__(self, clocks_per_baud): + self.clocks_per_baud = clocks_per_baud + + # Top-Level Ports + self.data_i = Signal(8) + self.start_i = Signal() + self.done_o = Signal(reset=1) + + self.tx = Signal(reset=1) + + # Internal Signals + self.baud_counter = Signal(range(clocks_per_baud)) + self.buffer = Signal(9) + self.bit_index = Signal(4) + + def elaborate(self, platform): + m = Module() + + with m.If((self.start_i) & (self.done_o)): + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.done_o.eq(0) + m.d.sync += self.tx.eq(0) + + with m.Elif(~self.done_o): + m.d.sync += self.baud_counter.eq(self.baud_counter - 1) + m.d.sync += self.done_o.eq((self.baud_counter == 1) & (self.bit_index == 9)) + + # A baud period has elapsed + with m.If(self.baud_counter == 0): + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + + # Clock out another bit if there are any left + with m.If(self.bit_index < 9): + m.d.sync += self.tx.eq(self.buffer.bit_select(self.bit_index, 1)) + m.d.sync += self.bit_index.eq(self.bit_index + 1) + + # Byte has been sent, send out next one or go to idle + with m.Else(): + with m.If(self.start_i): + m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.tx.eq(0) + + with m.Else(): + m.d.sync += self.done_o.eq(1) + return m + + +class TransmitBridge(Elaboratable): + def __init__(self): + # Top-Level Ports + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + self.data_o = Signal(8, reset=0) + self.start_o = Signal(1) + self.done_i = Signal() + + # Internal Signals + self.buffer = Signal(16, reset=0) + self.count = Signal(4, reset=0) + self.busy = Signal(1, reset=0) + self.to_ascii_hex = Signal(8) + self.n = Signal(4) + + def elaborate(self, platform): + m = Module() + + m.d.comb += self.start_o.eq(self.busy) + + with m.If(~self.busy): + with m.If((self.valid_i) & (~self.rw_i)): + m.d.sync += self.busy.eq(1) + m.d.sync += self.buffer.eq(self.data_i) + + with m.Else(): + # uart_tx is transmitting a byte: + with m.If(self.done_i): + m.d.sync += self.count.eq(self.count + 1) + + # Message has been transmitted + with m.If(self.count > 5): + m.d.sync += self.count.eq(0) + + # Go back to idle, or transmit next message + with m.If((self.valid_i) & (~self.rw_i)): + m.d.sync += self.buffer.eq(self.data_i) + + with m.Else(): + m.d.sync += self.busy.eq(0) + + # define to_ascii_hex + with m.If(self.n < 10): + m.d.comb += self.to_ascii_hex.eq(self.n + 0x30) + with m.Else(): + m.d.comb += self.to_ascii_hex.eq(self.n + 0x41 - 10) + + # run the sequence + with m.If(self.count == 0): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("D")) + + with m.Elif(self.count == 1): + m.d.comb += self.n.eq(self.buffer[12:16]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 2): + m.d.comb += self.n.eq(self.buffer[8:12]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 3): + m.d.comb += self.n.eq(self.buffer[4:8]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 4): + m.d.comb += self.n.eq(self.buffer[0:4]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 5): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("\r")) + + with m.Elif(self.count == 6): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("\n")) + + with m.Else(): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(0) + + return m diff --git a/src/manta/uart_iface/__init__.py b/src/manta/uart_iface/__init__.py deleted file mode 100644 index 98f2ffc..0000000 --- a/src/manta/uart_iface/__init__.py +++ /dev/null @@ -1,186 +0,0 @@ -from ..utils import * - -class UARTInterface: - def __init__(self, config): - # Warn if unrecognized options have been given - for option in config: - if option not in ["port", "clock_freq", "baudrate", "chunk_size", "verbose"]: - print(f"Warning: Ignoring unrecognized option '{option}' in UART interface.") - - # Obtain port. Try to automatically detect port if "auto" is specified - assert "port" in config, "No serial port provided to UART core." - self.port = config["port"] - - # Check that clock frequency is provided and positive - assert "clock_freq" in config, "Clock frequency not provided to UART core." - assert config["clock_freq"] > 0, "Clock frequency must be positive." - self.clock_freq = config["clock_freq"] - - # Check that baudrate is provided and positive - assert "baudrate" in config, "Baudrate not provided to UART core." - assert config["baudrate"] > 0, "Baudrate must be positive." - self.baudrate = config["baudrate"] - - # Confirm core clock is sufficiently fast - clocks_per_baud = self.clock_freq // self.baudrate - assert clocks_per_baud >= 2 - self.clocks_per_baud = clocks_per_baud - - # Confirm we can match baudrate suffeciently well - actual_baudrate = self.clock_freq / clocks_per_baud - baudrate_error = 100 * abs(actual_baudrate - self.baudrate) / self.baudrate - assert baudrate_error <= 5, \ - "Unable to match target baudrate - they differ by {baudrate_error}%" - - # Set chunk_size, which is the max amount of bytes that get dumped - # to the OS driver at a time - self.chunk_size = 256 - if "chunk_size" in config: - self.chunk_size = config["chunk_size"] - - # Set verbosity - self.verbose = False - if "verbose" in config: - self.verbose = config["verbose"] - - def open_port_if_not_alredy_open(self): - if self.port == "auto": - self.port = self.autodetect_port() - - if not hasattr(self, "ser"): - import serial - self.ser = serial.Serial(self.port, self.baudrate) - - def autodetect_port(self): - # as far as I know the FT2232 is the only chip used on the icestick/digilent boards, so just look for that - import serial.tools.list_ports - - recognized_devices = [] - for port in serial.tools.list_ports.comports(): - if (port.vid == 0x403) and (port.pid == 0x6010): - recognized_devices.append(port) - - # board manufacturers seem to always make the 0th serial - # interface on the FT2232 be for programming over JTAG, - # and then the 1st to be for UART. as a result, we always - # grab the device with the larger location - - rd = recognized_devices - assert len(recognized_devices) == 2, f"Expected to see two serial ports for FT2232 device, but instead see {len(recognized_devices)}." - assert rd[0].serial_number == rd[1].serial_number, "Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices." - return rd[0].device if rd[0].location > rd[1].location else rd[1].device - - def decode_response(self, response): - """Make sure reponse from FPGA has the correct format, and return data contained within if so.""" - assert response is not None, "No reponse received." - - response_str = response.decode('ascii') - assert response_str[0] == 'D', "Bad message recieved, incorrect preamble." - assert response_str[-2] == '\r', "Bad message received, incorrect EOL." - assert response_str[-1] == '\n', "Bad message received, incorrect EOL." - assert len(response_str) == 7, f"Wrong number of bytes received, expecting 7 but got {len(response)}." - - return int(response_str[1:5], 16) - - - def read(self, addr): - # Perform type checks, output list of addresses - if isinstance(addr, int): - addrs = [addr] - - elif isinstance(addr, list): - assert all(isinstance(a, int) for a in addr), \ - "Read addresses must be integer or list of integers." - addrs = addr - - else: - raise ValueError("Read addresses must be integer or list of integers.") - - # send data in chunks because the reponses will fill up the OS's - # input buffer in no time flat - self.open_port_if_not_alredy_open() - - inbound_bytes = b"" - for i in range(0, len(addrs), self.chunk_size): - addr_chunk = addrs[i:i+self.chunk_size] - - outbound_bytes = [f"R{addr:04X}\r\n".encode('ascii') for addr in addr_chunk] - outbound_bytes = b"".join(outbound_bytes) - - self.ser.write(outbound_bytes) - - inbound_bytes += self.ser.read(len(outbound_bytes)) - - data = [] - for i in range(0, len(inbound_bytes), 7): - response = inbound_bytes[i:i+7] - data.append(self.decode_response(response)) - - if isinstance(addr, int): - return data[0] - - else: - return data - - def write(self, addr, data): - # Perform type checks, output list of addresses - if isinstance(addr, int): - assert isinstance(data, int), \ - "Data must also be integer if address is integer." - addrs = [addr] - datas = [data] - - elif isinstance(addr, list): - assert all(isinstance(a, int) for a in addr), \ - "Write addresses must be integer or list of integers." - - assert all(isinstance(d, int) for d in data), \ - "Write data must be integer or list of integers." - - assert len(addr) == len(data), \ - "There must be equal number of write addresses and data." - - addrs = addr - datas = data - - else: - raise ValueError("Write addresses and data must be integer or list of integers.") - - # send data in chunks because the reponses will fill up the OS's - # input buffer in no time flat - self.open_port_if_not_alredy_open() - - for i in range(0, len(addrs), self.chunk_size): - addr_chunk = addrs[i:i+self.chunk_size] - data_chunk = datas[i:i+self.chunk_size] - - - outbound_bytes = [f"W{a:04X}{d:04X}\r\n" for a, d in zip(addr_chunk, data_chunk)] - outbound_bytes = [ob.encode('ascii') for ob in outbound_bytes] - outbound_bytes = b"".join(outbound_bytes) - - self.ser.write(outbound_bytes) - - def hdl_top_level_ports(self): - # this should return the probes that we want to connect to top-level, but like as a string of verilog - return ["input wire rx", "output reg tx"] - - def rx_hdl_def(self): - uart_rx_def = VerilogManipulator("uart_iface/uart_rx.v").get_hdl() - bridge_rx_def = VerilogManipulator("uart_iface/bridge_rx.v").get_hdl() - return uart_rx_def + '\n' + bridge_rx_def - - def tx_hdl_def(self): - uart_tx_def = VerilogManipulator("uart_iface/uart_tx.v").get_hdl() - bridge_tx_def = VerilogManipulator("uart_iface/bridge_tx.v").get_hdl() - return bridge_tx_def + '\n' + uart_tx_def - - def rx_hdl_inst(self): - rx = VerilogManipulator("uart_iface/uart_rx_bridge_rx_inst_tmpl.v") - rx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */") - return rx.get_hdl() - - def tx_hdl_inst(self): - tx = VerilogManipulator("uart_iface/uart_tx_bridge_tx_inst_tmpl.v") - tx.sub(self.clocks_per_baud, "/* CLOCKS_PER_BAUD */") - return tx.get_hdl() \ No newline at end of file diff --git a/src/manta/uart_iface/bridge_rx.v b/src/manta/uart_iface/bridge_rx.v deleted file mode 100644 index 995b1ab..0000000 --- a/src/manta/uart_iface/bridge_rx.v +++ /dev/null @@ -1,150 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module bridge_rx ( - input wire clk, - - input wire [7:0] data_i, - input wire valid_i, - - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o); - - initial addr_o = 0; - initial data_o = 0; - initial rw_o = 0; - initial valid_o = 0; - - function [3:0] from_ascii_hex; - // convert an ascii char encoding a hex value to - // the corresponding hex value - input [7:0] c; - - if ((c >= 8'h30) && (c <= 8'h39)) from_ascii_hex = c - 8'h30; - else if ((c >= 8'h41) && (c <= 8'h46)) from_ascii_hex = c - 8'h41 + 'd10; - else from_ascii_hex = 0; - endfunction - - function is_ascii_hex; - // checks if a byte is an ascii char encoding a hex digit - input [7:0] c; - - if ((c >= 8'h30) && (c <= 8'h39)) is_ascii_hex = 1; // 0-9 - else if ((c >= 8'h41) && (c <= 8'h46)) is_ascii_hex = 1; // A-F - else is_ascii_hex = 0; - endfunction - - reg [7:0] buffer [7:0]; // = 0; // todo: see if sby will tolerate packed arrays? - - localparam IDLE = 0; - localparam READ = 1; - localparam WRITE = 2; - reg [1:0] state = 0; - reg [3:0] byte_num = 0; - - always @(posedge clk) begin - addr_o <= 0; - data_o <= 0; - rw_o <= 0; - valid_o <= 0; - - if (state == IDLE) begin - byte_num <= 0; - if (valid_i) begin - if (data_i == "R") state <= READ; - if (data_i == "W") state <= WRITE; - end - end - - else begin - if (valid_i) begin - // buffer bytes regardless of if they're good - byte_num <= byte_num + 1; - buffer[byte_num] <= data_i; - - // current transaction specifies a read operation - if(state == READ) begin - - // go to idle if anything doesn't make sense - if(byte_num < 4) begin - if(!is_ascii_hex(data_i)) state <= IDLE; - end - - else if(byte_num == 4) begin - state <= IDLE; - - // put data on the bus if the last byte looks good - if((data_i == 8'h0D) || (data_i == 8'h0A)) begin - addr_o <= (from_ascii_hex(buffer[0]) << 12) | - (from_ascii_hex(buffer[1]) << 8) | - (from_ascii_hex(buffer[2]) << 4) | - (from_ascii_hex(buffer[3])); - data_o <= 0; - rw_o <= 0; - valid_o <= 1; - end - end - end - - // current transaction specifies a write transaction - if(state == WRITE) begin - - // go to idle if anything doesn't make sense - if(byte_num < 8) begin - if(!is_ascii_hex(data_i)) state <= IDLE; - end - - else if(byte_num == 8) begin - state <= IDLE; - - // put data on the bus if the last byte looks good - if((data_i == 8'h0A) || (data_i == 8'h0D)) begin - addr_o <= (from_ascii_hex(buffer[0]) << 12) | - (from_ascii_hex(buffer[1]) << 8) | - (from_ascii_hex(buffer[2]) << 4) | - (from_ascii_hex(buffer[3])); - data_o <= (from_ascii_hex(buffer[4]) << 12) | - (from_ascii_hex(buffer[5]) << 8) | - (from_ascii_hex(buffer[6]) << 4) | - (from_ascii_hex(buffer[7])); - rw_o <= 1; - valid_o <= 1; - end - end - end - end - end - end - -`ifdef FORMAL - always @(posedge clk) begin - // covers - find_any_write_transaction: cover(rw_o == 1); - find_any_read_transaction: cover(rw_o == 0); - - find_specific_write_transaction: - cover(data_o == 16'h1234 && addr_o == 16'h5678 && rw_o == 1 && valid_o == 1); - - find_specific_read_transaction: - cover(addr_o == 16'h1234 && rw_o == 0 && valid_o == 1); - - find_spacey_write_transaction: - cover((rw_o == 1) && ($past(valid_i, 3) == 0)); - - // asserts - no_back_to_back_transactions: - assert( ~(valid_o && $past(valid_o)) ); - - no_invalid_states: - assert(state == IDLE || state == READ || state == WRITE); - - byte_counter_only_increases: - assert(byte_num == $past(byte_num) || byte_num == $past(byte_num) + 1 || byte_num == 0); - end -`endif // FORMAL -endmodule - - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/uart_iface/bridge_tx.v b/src/manta/uart_iface/bridge_tx.v deleted file mode 100644 index 70bbf0d..0000000 --- a/src/manta/uart_iface/bridge_tx.v +++ /dev/null @@ -1,70 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module bridge_tx ( - input wire clk, - - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - output reg [7:0] data_o, - output reg start_o, - input wire done_i); - - function [7:0] to_ascii_hex; - // convert a number from 0-15 into the corresponding ascii char - input [3:0] n; - to_ascii_hex = (n < 10) ? (n + 8'h30) : (n + 8'h41 - 'd10); - endfunction - - localparam PREAMBLE = "D"; - localparam CR = 8'h0D; - localparam LF = 8'h0A; - - reg busy = 0; - reg [15:0] buffer = 0; - reg [3:0] count = 0; - - assign start_o = busy; - - always @(posedge clk) begin - // idle until valid read transaction arrives on bus - if (!busy) begin - if (valid_i && !rw_i) begin - busy <= 1; - buffer <= data_i; - end - end - - if (busy) begin - // uart module is done transmitting a byte - if(done_i) begin - count <= count + 1; - - // message has been transmitted - if (count > 5) begin - count <= 0; - - // go back to idle or transmit next message - if (valid_i && !rw_i) buffer <= data_i; - else busy <= 0; - end - end - end - end - - always @(*) begin - case (count) - 0: data_o = PREAMBLE; - 1: data_o = to_ascii_hex(buffer[15:12]); - 2: data_o = to_ascii_hex(buffer[11:8]); - 3: data_o = to_ascii_hex(buffer[7:4]); - 4: data_o = to_ascii_hex(buffer[3:0]); - 5: data_o = CR; - 6: data_o = LF; - default: data_o = 0; - endcase - end -endmodule -`default_nettype wire \ No newline at end of file diff --git a/src/manta/uart_iface/uart_rx.v b/src/manta/uart_iface/uart_rx.v deleted file mode 100644 index a4e8abb..0000000 --- a/src/manta/uart_iface/uart_rx.v +++ /dev/null @@ -1,62 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -// Modified from Dan Gisselquist's rx_uart module, -// available at https://zipcpu.com/tutorial/ex-09-uartrx.zip - -module uart_rx ( - input wire clk, - - input wire rx, - - output reg [7:0] data_o, - output reg valid_o); - - parameter CLOCKS_PER_BAUD = 0; - localparam IDLE = 0; - localparam BIT_ZERO = 1; - localparam STOP_BIT = 9; - - reg [3:0] state = IDLE; - reg [15:0] baud_counter = 0; - reg zero_baud_counter; - assign zero_baud_counter = (baud_counter == 0); - - // 2FF Synchronizer - reg ck_uart = 1; - reg q_uart = 1; - always @(posedge clk) - { ck_uart, q_uart } <= { q_uart, rx }; - - always @(posedge clk) - if (state == IDLE) begin - state <= IDLE; - baud_counter <= 0; - if (!ck_uart) begin - state <= BIT_ZERO; - baud_counter <= CLOCKS_PER_BAUD+CLOCKS_PER_BAUD/2-1'b1; - end - end - - else if (zero_baud_counter) begin - state <= state + 1; - baud_counter <= CLOCKS_PER_BAUD-1'b1; - if (state == STOP_BIT) begin - state <= IDLE; - baud_counter <= 0; - end - end - - else baud_counter <= baud_counter - 1'b1; - - always @(posedge clk) - if ( (zero_baud_counter) && (state != STOP_BIT) ) - data_o <= {ck_uart, data_o[7:1]}; - - initial valid_o = 1'b0; - always @(posedge clk) - valid_o <= ( (zero_baud_counter) && (state == STOP_BIT) ); - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v b/src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v deleted file mode 100644 index 8ff8dec..0000000 --- a/src/manta/uart_iface/uart_rx_bridge_rx_inst_tmpl.v +++ /dev/null @@ -1,20 +0,0 @@ -uart_rx #(.CLOCKS_PER_BAUD(/* CLOCKS_PER_BAUD */)) urx ( - .clk(clk), - .rx(rx), - - .data_o(urx_brx_data), - .valid_o(urx_brx_valid)); - -reg [7:0] urx_brx_data; -reg urx_brx_valid; - -bridge_rx brx ( - .clk(clk), - - .data_i(urx_brx_data), - .valid_i(urx_brx_valid), - - .addr_o(), - .data_o(), - .rw_o(), - .valid_o()); \ No newline at end of file diff --git a/src/manta/uart_iface/uart_tx.v b/src/manta/uart_iface/uart_tx.v deleted file mode 100644 index ea249a7..0000000 --- a/src/manta/uart_iface/uart_tx.v +++ /dev/null @@ -1,61 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module uart_tx ( - input wire clk, - - input wire [7:0] data_i, - input wire start_i, - output reg done_o, - - output reg tx); - - // this module supports only 8N1 serial at a configurable baudrate - parameter CLOCKS_PER_BAUD = 0; - reg [$clog2(CLOCKS_PER_BAUD)-1:0] baud_counter = 0; - - reg [8:0] buffer = 0; - reg [3:0] bit_index = 0; - - initial done_o = 1; - initial tx = 1; - - always @(posedge clk) begin - if (start_i && done_o) begin - baud_counter <= CLOCKS_PER_BAUD - 1; - buffer <= {1'b1, data_i}; - bit_index <= 0; - done_o <= 0; - tx <= 0; - end - - else if (!done_o) begin - baud_counter <= baud_counter - 1; - done_o <= (baud_counter == 1) && (bit_index == 9); - - // a baud period has elapsed - if (baud_counter == 0) begin - baud_counter <= CLOCKS_PER_BAUD - 1; - - // clock out another bit if there are any left - if (bit_index < 9) begin - tx <= buffer[bit_index]; - bit_index <= bit_index + 1; - end - - // byte has been sent, send out next one or go to idle - else begin - if(start_i) begin - buffer <= {1'b1, data_i}; - bit_index <= 0; - tx <= 0; - end - - else done_o <= 1; - end - end - end - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v b/src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v deleted file mode 100644 index bfe68b6..0000000 --- a/src/manta/uart_iface/uart_tx_bridge_tx_inst_tmpl.v +++ /dev/null @@ -1,23 +0,0 @@ -bridge_tx btx ( - .clk(clk), - - .data_i(), - .rw_i(), - .valid_i(), - - .data_o(btx_utx_data), - .start_o(btx_utx_start), - .done_i(utx_btx_done)); - -reg [7:0] btx_utx_data; -reg btx_utx_start; -reg utx_btx_done; - -uart_tx #(.CLOCKS_PER_BAUD(/* CLOCKS_PER_BAUD */)) utx ( - .clk(clk), - - .data_i(btx_utx_data), - .start_i(btx_utx_start), - .done_o(utx_btx_done), - - .tx(tx)); \ No newline at end of file diff --git a/src/manta/utils.py b/src/manta/utils.py index 67decc5..a40fa0a 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,124 +1,129 @@ -import pkgutil +from amaranth.sim import Simulator from math import ceil +import os -def pack_16bit_words(data): - """Takes a list of integers, interprets them as 16-bit integers, and - concatenates them together in little-endian order.""" + +def words_to_value(data): + """ + Takes a list of integers, interprets them as 16-bit integers, and + concatenates them together in little-endian order. + """ for d in data: - if d > 0: assert d < 2**16, "Unsigned integer too large." - if d < 0: assert d < 2**15, "Signed integer too large." + if d > 0 and d > 2**16 - 1: + raise ValueError("Unsigned integer too large.") - return int(''.join([f'{i:016b}' for i in data[::-1]]), 2) + if d < 0 and d < -(2**15 - 1): + raise ValueError("Signed integer too large.") -def unpack_16bit_words(data, n_words): - """Takes a integer, interprets it as a set of 16-bit integers - concatenated together, and splits it into a list of 16-bit numbers""" + return int("".join([f"{i:016b}" for i in data[::-1]]), 2) - assert isinstance(data, int), "Behavior is only defined for nonnegative integers." - assert data >= 0, "Behavior is only defined for nonnegative integers." + +def value_to_words(data, n_words): + """ + Takes a integer, interprets it as a set of 16-bit integers + concatenated together, and splits it into a list of 16-bit numbers. + """ + + if not isinstance(data, int) or data < 0: + raise ValueError("Behavior is only defined for nonnegative integers.") # convert to binary, split into 16-bit chunks, and then convert back to list of int - binary = f'{data:0b}'.zfill(n_words * 16) - return [int(binary[i:i+16], 2) for i in range(0, 16 * n_words, 16)][::-1] - -class VerilogManipulator: - def __init__(self, filepath=None): - if filepath is not None: - self.hdl = pkgutil.get_data(__name__, filepath).decode() - - # scrub any default_nettype or timescale directives from the source - self.hdl = self.hdl.replace("`default_nettype none", "") - self.hdl = self.hdl.replace("`default_nettype wire", "") - self.hdl = self.hdl.replace("`timescale 1ns/1ps", "") - self.hdl = self.hdl.strip() - - # python tries to be cute and automatically convert - # line endings on Windows, but Manta's source comes - # with (and injects) UNIX line endings, so Python - # ends up adding way too many line breaks, so we just - # undo anything it's done when we load the file - self.hdl = self.hdl.replace("\r\n", "\n") - - else: - self.hdl = None - - def sub(self, replace, find): - # sometimes we have integer inputs, want to accomodate - if isinstance(replace, str): - replace_str = replace - - elif isinstance(replace, int): - replace_str = str(replace) - - else: - raise ValueError("Only string and integer arguments supported.") + binary = f"{data:0b}".zfill(n_words * 16) + return [int(binary[i : i + 16], 2) for i in range(0, 16 * n_words, 16)][::-1] - # if the string being subbed in isn't multiline, just - # find-and-replace like normal: - if "\n" not in replace_str: - self.hdl = self.hdl.replace(find, replace_str) +def split_into_chunks(data, chunk_size): + """ + Split a list into a list of lists, where each sublist has length `chunk_size`. + If the list can't be evenly divided into chunks, then the last entry in the + returned list will have length less than `chunk_size`. + """ - # if the string being substituted in is multiline, - # make sure the replace text gets put at the same - # indentation level by adding whitespace to left - # of the line. - else: - for line in self.hdl.split("\n"): - if find in line: - # get whitespace that's on the left side of the line - whitespace = line.rstrip().replace(line.lstrip(), "") - - # add it to every line, except the first - replace_as_lines = replace_str.split("\n") - replace_with_whitespace = f"\n{whitespace}".join(replace_as_lines) - - # replace the first occurance in the HDL with it - self.hdl = self.hdl.replace(find, replace_with_whitespace, 1) - - def get_hdl(self): - return self.hdl - - def net_dec(self, nets, net_type, trailing_comma = False): - """Takes a dictonary of nets in the format {probe: width}, and generates - the net declarations that would go in a Verilog module definition. - - For example, calling net_dec({foo : 1, bar : 4}, "input wire") would produce: - - input wire foo, - input [3:0] wire bar - - Which you'd then slap into your module declaration, along with all the other - inputs and outputs the module needs.""" - - dec = [] - for name, width in nets.items(): - if width == 1: - dec.append(f"{net_type} {name}") - - else: - dec.append(f"{net_type} [{width-1}:0] {name}") - - dec = ",\n".join(dec) - dec = dec + "," if trailing_comma else dec - return dec - - def net_conn(self, nets, trailing_comma = False): - """Takes a dictionary of nets in the format {probe: width}, and generates - the net connections that would go in the Verilog module instantiation. - - For example, calling net_conn({foo: 1, bar: 4}) would produce: - - .foo(foo), - .bar(bar) - - Which you'd then slap into your module instantiation, along with all the other - module inputs and outputs that get connected elsewhere.""" + return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)] - conn = [f".{name}({name})" for name in nets] - conn = ",\n".join(conn) - conn = conn + "," if trailing_comma else conn +def simulate(top, testbench, vcd_path=None): + """ + Run a behavior simulation using Amaranth's built-in simulator `pysim`. Takes + the top-level module to simulate, the testbench process to run, and an optional + path to export a VCD file to. + """ + sim = Simulator(top) + sim.add_clock(1e-6) # 1 MHz + sim.add_sync_process(testbench) - return conn + if vcd_path is None: + sim.run() + + else: + with sim.write_vcd(vcd_path): + sim.run() + + +def verify_register(module, addr, expected_data): + """ + Read the contents of a register out over a module's bus connection, and verify + that it contains the expected data. + + Unfortunately because Amaranth uses generator functions to define processes, + this must be a generator function and thus cannot return a value - it must + yield the next timestep. This means that the comparision with the expected + value must occur inside this function and not somewhere else, it's not + possible to return a value from here, and compare it in the calling function. + """ + + # place read transaction on the bus + yield module.addr_i.eq(addr) + yield module.data_i.eq(0) + yield module.rw_i.eq(0) + yield module.valid_i.eq(1) + yield + yield module.addr_i.eq(0) + yield module.valid_i.eq(0) + + # wait for output to be valid + while not (yield module.valid_o): + yield + + # compare returned value with expected + data = yield (module.data_o) + if data != expected_data: + raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") + + +def write_register(module, addr, data): + """ + Write to a register over a module's bus connection, placing the contents of `data` + at `addr`. + """ + + yield module.addr_i.eq(addr) + yield module.data_i.eq(data) + yield module.rw_i.eq(1) + yield module.valid_i.eq(1) + yield + yield module.valid_i.eq(0) + yield + + +def xilinx_tools_installed(): + """ + Return whether Vivado is installed, by checking if the VIVADO environment variable is set. + + This variable should point to the binary itself, not just the folder it's located in + (ie, /tools/Xilinx/Vivado/2023.1/bin/vivado, not /tools/Xilinx/Vivado/2023.1/bin) + """ + return "VIVADO" in os.environ + + +def ice40_tools_installed(): + """ + Return whether the ice40 tools are installed, by checking if the YOSYS, NEXTPNR_ICE40, + ICEPACK, and ICEPROG environment variables are defined. + + # These variables should point to the binaries themselves, not just the folder it's located in + # (ie, /tools/oss-cad-suite/bin/yosys, not /tools/oss-cad-suite/bin/) + """ + tools = ["YOSYS", "NEXTPNR_ICE40", "ICEPACK", "ICEPROG"] + return all(tool in os.environ for tool in tools) diff --git a/test/auto_gen/invalid_configs/0_mangled_yaml.yaml b/test/auto_gen/invalid_configs/0_mangled_yaml.yaml deleted file mode 100644 index 866e678..0000000 --- a/test/auto_gen/invalid_configs/0_mangled_yaml.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: Q - btnr: 1 - btnc: 1 - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/auto_gen/invalid_configs/1_mangled_yaml.yaml b/test/auto_gen/invalid_configs/1_mangled_yaml.yaml deleted file mode 100644 index c786cdb..0000000 --- a/test/auto_gen/invalid_configs/1_mangled_yaml.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/auto_gen/invalid_configs/2_mangled_yaml.yaml b/test/auto_gen/invalid_configs/2_mangled_yaml.yaml deleted file mode 100644 index 9386d37..0000000 --- a/test/auto_gen/invalid_configs/2_mangled_yaml.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: randomstringthatsnotaninteger - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/auto_gen/run_tests.py b/test/auto_gen/run_tests.py deleted file mode 100644 index 3e5ec4c..0000000 --- a/test/auto_gen/run_tests.py +++ /dev/null @@ -1,56 +0,0 @@ -# try to build manta instances from valid and invalid configuration files - -from os import listdir -from os.path import isfile -from manta import Manta - - -# Valid Configurations - -# test that they make a python API without errors -# TODO: test that their verilog passes lint - -print(" ==== Testing valid configurations ====") -valid_configs_path = "test/auto_gen/valid_configs/" -for config_file in sorted(listdir(valid_configs_path)): - caught_exception = None - try: - m = Manta(valid_configs_path + config_file) - - except Exception as e: - caught_exception = e - - if caught_exception is None: - print(f" -> no exceptions correctly raised by config file {config_file}") - - else: - raise RuntimeError( - f"Configuration {config_file} shouldn't have raised an exception, but raised {caught_exception}" - ) - - -print("\n") - -# Invalid Configurations - -# test that they throw errors when generating a python API - -print(" ==== Testing invalid configurations ====") -invalid_configs_path = "test/auto_gen/invalid_configs/" -for config_file in sorted(listdir(invalid_configs_path)): - caught_exception = None - try: - m = Manta(invalid_configs_path + config_file) - - except Exception as e: - caught_exception = e - - if caught_exception is not None: - print( - f" -> exception correctly raised by config file {config_file}: {caught_exception}" - ) - - else: - raise RuntimeError( - f"Configuration {config_file} should have raised an exception, but did not!" - ) diff --git a/test/auto_gen/valid_configs/0_io_core.yaml b/test/auto_gen/valid_configs/0_io_core.yaml deleted file mode 100644 index 867efbe..0000000 --- a/test/auto_gen/valid_configs/0_io_core.yaml +++ /dev/null @@ -1,26 +0,0 @@ ---- -cores: - my_io_core: - type: io - - inputs: - btnu: 1 - btnd: 1 - btnl: 1 - btnr: 1 - btnc: 1 - sw: 16 - - outputs: - led: 16 - led16_b: 1 - led16_g: 1 - led16_r: 1 - led17_b: 1 - led17_g: 1 - led17_r: 1 - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/auto_gen/valid_configs/1_logic_analyzer.yaml b/test/auto_gen/valid_configs/1_logic_analyzer.yaml deleted file mode 100644 index 107efa8..0000000 --- a/test/auto_gen/valid_configs/1_logic_analyzer.yaml +++ /dev/null @@ -1,19 +0,0 @@ ---- -cores: - my_logic_analyzer: - type: logic_analyzer - sample_depth: 4096 - - probes: - larry: 1 - curly: 1 - moe: 1 - shemp: 4 - - triggers: - - larry && curly && ~moe - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/formal_verification/bridge_rx.sby b/test/formal_verification/bridge_rx.sby deleted file mode 100644 index 93a9ed9..0000000 --- a/test/formal_verification/bridge_rx.sby +++ /dev/null @@ -1,29 +0,0 @@ -[tasks] -basic bmc -nofullskip prove -cover -noverific cover -basic cover : default - -[options] -cover: -mode cover --- -prove: -mode prove --- -bmc: -mode bmc --- - -[engines] -smtbmc boolector - -[script] -nofullskip: read -define NO_FULL_SKIP=1 -noverific: read -noverific -read -formal bridge_rx.v -prep -top bridge_rx - -[files] -src/manta/uart_iface/bridge_rx.v \ No newline at end of file diff --git a/test/functional_sim/block_memory_tb.sv b/test/functional_sim/block_memory_tb.sv deleted file mode 100644 index 818ca3b..0000000 --- a/test/functional_sim/block_memory_tb.sv +++ /dev/null @@ -1,182 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -`define BRAM_DEPTH 256 -`define BRAM_WIDTH 33 -`define ADDR_WIDTH $clog2(`BRAM_DEPTH) - -task read_reg_bus_side ( - input [15:0] addr, - output [15:0] data - ); - - block_memory_tb.tb_bc_addr = addr; - block_memory_tb.tb_bc_rw = 0; - block_memory_tb.tb_bc_valid = 1; - #`CP - block_memory_tb.tb_bc_rw = 0; - block_memory_tb.tb_bc_valid = 0; - while (!block_memory_tb.bc_tb_valid) #`CP; - data = block_memory_tb.bc_tb_data; - - $display(" -> bus read 0x%h from addr 0x%h", data, addr); -endtask - -task write_reg_bus_side( - input [15:0] addr, - input [15:0] data - ); - - block_memory_tb.tb_bc_addr = addr; - block_memory_tb.tb_bc_data = data; - block_memory_tb.tb_bc_rw = 1; - block_memory_tb.tb_bc_valid = 1; - #`CP - block_memory_tb.tb_bc_rw = 0; - block_memory_tb.tb_bc_valid = 0; - while (!block_memory_tb.bc_tb_valid) #`CP; - - $display(" -> bus wrote 0x%h to addr 0x%h", data, addr); -endtask - -task write_and_verify_bus_side( - input [15:0] addr, - input [15:0] write_data - ); - - reg [15:0] read_data; - - write_reg_bus_side(addr, write_data); - read_reg_bus_side(addr, read_data); - assert(read_data == write_data) else $fatal(0, "data read does not match data written!"); -endtask - -task read_user_side( - input [`ADDR_WIDTH-1:0] addr - ); - - block_memory_tb.bram_user_we = 0; - block_memory_tb.bram_user_addr = addr; - #(2*`CP); - $display("user read 0x%h from addr 0x%h", block_memory_tb.bram_user_dout, addr); -endtask - -task write_user_side( - input [`ADDR_WIDTH-1:0] addr, - input [`BRAM_WIDTH-1:0] data - ); - - block_memory_tb.bram_user_we = 1; - block_memory_tb.bram_user_addr = addr; - block_memory_tb.bram_user_din = data; - #(2*`CP); - $display("user wrote 0x%h to addr 0x%h", data, addr); -endtask - - -module block_memory_tb; - - // boilerplate - logic clk; - integer test_num; - reg [15:0] read_value; - - // tb -> bram_core bus - logic [15:0] tb_bc_addr; - logic [15:0] tb_bc_data; - logic tb_bc_rw; - logic tb_bc_valid; - - // bram_core -> tb bus - logic [15:0] bc_tb_addr; - logic [15:0] bc_tb_data; - logic bc_tb_rw; - logic bc_tb_valid; - - // bram itself - localparam BRAM_DEPTH = `BRAM_DEPTH; - localparam BRAM_WIDTH = `BRAM_WIDTH; - localparam ADDR_WIDTH = $clog2(BRAM_DEPTH); - logic [ADDR_WIDTH-1:0] bram_user_addr = 0; - logic [BRAM_WIDTH-1:0] bram_user_din = 0; - logic [BRAM_WIDTH-1:0] bram_user_dout; - logic bram_user_we = 0; - - block_memory #(.DEPTH(BRAM_DEPTH), .WIDTH(BRAM_WIDTH)) block_mem ( - .clk(clk), - - .addr_i(tb_bc_addr), - .data_i(tb_bc_data), - .rw_i(tb_bc_rw), - .valid_i(tb_bc_valid), - - .addr_o(bc_tb_addr), - .data_o(bc_tb_data), - .rw_o(bc_tb_rw), - .valid_o(bc_tb_valid), - - .user_clk(clk), - .user_addr(bram_user_addr), - .user_din(bram_user_din), - .user_dout(bram_user_dout), - .user_we(bram_user_we)); - - always begin - #`HCP - clk = !clk; - end - - initial begin - $dumpfile("block_memory_tb.vcd"); - $dumpvars(0, block_memory_tb); - - // setup and reset - clk = 0; - test_num = 0; - - tb_bc_addr = 0; - tb_bc_data = 0; - tb_bc_rw = 0; - tb_bc_valid = 0; - - bram_user_addr = 0; - bram_user_din = 0; - bram_user_we = 0; - - #`HCP - - - - #(10*`CP); - - /* ==== Test 1 Begin ==== */ - $display("\n=== test 1: read/write from BRAM, verify ==="); - test_num = 1; - write_and_verify_bus_side(0, 'h6789); - write_and_verify_bus_side(1, 'h2345); - write_and_verify_bus_side(2, 'h0001); - - // now query what's on the the user side at address 0 - read_user_side(0); - - write_and_verify_bus_side(3, 'h1111); - write_and_verify_bus_side(4, 'h1111); - write_and_verify_bus_side(5, 'h0001); - - // now query what's on the the user side at address 0 - read_user_side(1); - - write_user_side(1, 0); - read_user_side(1); - - #(10*`CP); - - /* ==== Test 1 End ==== */ - - $finish(); - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/bridge_rx_tb.sv b/test/functional_sim/bridge_rx_tb.sv deleted file mode 100644 index 78b4049..0000000 --- a/test/functional_sim/bridge_rx_tb.sv +++ /dev/null @@ -1,185 +0,0 @@ -`default_nettype none -// `timescale 1ns/1ps - -`define CP 10 -`define HCP 5 - -task test_good_read_msg ( - input string message, - input [15:0] addr - ); - - bridge_rx_tb.tb_brx_valid = 1; - for(int i=0; i < $size(message); i++) begin - bridge_rx_tb.tb_brx_data = message [i]; - if(bridge_rx_tb.brx_tb_valid) begin - assert(bridge_rx_tb.brx_tb_addr == addr) else $fatal(0, "wrong addr!"); - assert(bridge_rx_tb.brx_tb_rw == 0) else $fatal(0, "wrong rw!"); - assert(bridge_rx_tb.brx_tb_data == 0) else $fatal(0, "wrong data!"); - end - #`CP; - end - bridge_rx_tb.tb_brx_valid = 0; -endtask - -task test_good_write_msg ( - input string message, - input [15:0] addr, - input [15:0] data - ); - - bridge_rx_tb.tb_brx_valid = 1; - for(int i=0; i < $size(message); i++) begin - bridge_rx_tb.tb_brx_data = message[i]; - if(bridge_rx_tb.brx_tb_valid) begin - assert(bridge_rx_tb.brx_tb_addr == addr) else $fatal(0, "wrong addr!"); - assert(bridge_rx_tb.brx_tb_rw == 1) else $fatal(0, "wrong rw!"); - assert(bridge_rx_tb.brx_tb_data == data) else $fatal(0, "wrong data!"); - end - #`CP; - end - bridge_rx_tb.tb_brx_valid = 0; -endtask - -task test_bad_msg ( - input string message - ); - - bridge_rx_tb.tb_brx_valid = 1; - for(int i=0; i < $size(message); i++) begin - bridge_rx_tb.tb_brx_data = message[i]; - assert(bridge_rx_tb.brx_tb_valid == 0) else $fatal(0, "wrong valid!"); - #`CP; - end - bridge_rx_tb.tb_brx_valid = 0; -endtask - - -module bridge_rx_tb; -// https://www.youtube.com/watch?v=WCOAr-96bGc - -//boilerplate -logic clk; -integer test_num; - -// uart inputs and outputs -logic [7:0] tb_brx_data; -logic tb_brx_valid; - -logic [15:0] brx_tb_addr; -logic [15:0] brx_tb_data; -logic brx_tb_rw; -logic brx_tb_valid; - -bridge_rx bridge_rx_uut( - .clk(clk), - - .data_i(tb_brx_data), - .valid_i(tb_brx_valid), - - .addr_o(brx_tb_addr), - .data_o(brx_tb_data), - .rw_o(brx_tb_rw), - .valid_o(brx_tb_valid)); - -always begin - #`HCP - clk = !clk; -end - -initial begin - $dumpfile("bridge_rx.vcd"); - $dumpvars(0, bridge_rx_tb); - - // setup and reset - clk = 0; - tb_brx_data = 0; - tb_brx_valid = 0; - test_num = 0; - #`CP - #`HCP - - test_num = test_num + 1; - $display("\n=== test %2d: transmit W12345678(CR)(LF) for baseline functionality ===", test_num); - test_good_write_msg("W12345678\r\n", 16'h1234, 16'h5678); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit WDEADBEEF(CR)(LF) for proper state reset ===", test_num); - test_good_write_msg("WDEADBEEF\r\n", 16'hDEAD, 16'hBEEF); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit RBABE(CR)(LF) for baseline functionality ===", test_num); - test_good_read_msg("RBABE\r\n", 16'hBABE); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R0000(CR) for EOL insensitivity ===", test_num); - test_good_read_msg("R0000\r", 16'hBABE); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R1234(LF) for EOL insensitivity ===", test_num); - test_good_read_msg("R1234\n", 16'h1234); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit WF00DBEEF(CR) for EOL insensitivity ===", test_num); - test_good_write_msg("WF00DBEEF\r", 16'hF00D, 16'hBEEF); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit WB0BACAFE(LF) for EOL insensitivity ===", test_num); - test_good_write_msg("WB0BACAFE\r", 16'hB0BA, 16'hCAFE); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R1234(LF)R5678 for back-to-back messages ===", test_num); - test_good_read_msg("R1234\r\n", 16'h1234); - test_good_read_msg("R5678\r\n", 16'h5678); - #(10*`CP); - - $display("\n\nIntentionally bad messages:"); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit RABC(CR)(LF) for message length ===", test_num); - test_bad_msg("RABC\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R12345(CR)(LF) for message length ===", test_num); - test_bad_msg("R12345\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit M(CR)(LF) for message length ===", test_num); - test_bad_msg("WABC\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit W123456789101112131415161718191201222(CR)(LF) for message length ===", test_num); - test_bad_msg("W123456789101112131415161718191201222\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit RABCG(CR)(LF) for invalid characters ===", test_num); - test_bad_msg("RABCG\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit WABC[]()##*@(CR)(LF) for invalid characters and message length ===", test_num); - test_bad_msg("WABC[]()##*@\r\n"); - #(10*`CP); - - test_num = test_num + 1; - $display("\n=== test %2d: transmit R(CR)(LF) for message length ===", test_num); - test_bad_msg("R\r\n"); - #(10*`CP); - - $finish(); -end - - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/bridge_tx_tb.sv b/test/functional_sim/bridge_tx_tb.sv deleted file mode 100644 index b55e6d2..0000000 --- a/test/functional_sim/bridge_tx_tb.sv +++ /dev/null @@ -1,116 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -`define CP 10 -`define HCP 5 - -module bridge_tx_tb; -// https://www.youtube.com/watch?v=WCOAr-96bGc - -// boilerplate -logic clk; -integer test_num; - -// tb -> bridge_tx signals -logic [15:0] tb_btx_data; -logic tb_btx_valid; - -// uart_tx -> tb signals -logic utx_tb_tx; - -bridge_tx btx ( - .clk(clk), - - .data_i(tb_btx_data), - .rw_i(1'b0), - .valid_i(tb_btx_valid), - - .data_o(btx_utx_data), - .start_o(btx_utx_start), - .done_i(utx_btx_done)); - -reg [7:0] btx_utx_data; -reg btx_utx_start; -reg utx_btx_done; - -uart_tx #(.CLOCKS_PER_BAUD(10)) utx ( - .clk(clk), - - .data_i(btx_utx_data), - .start_i(btx_utx_start), - .done_o(utx_btx_done), - - .tx(utx_tb_tx)); - -always begin - #`HCP - clk = !clk; -end - -initial begin - $dumpfile("bridge_tx.vcd"); - $dumpvars(0, bridge_tx_tb); - - // setup and reset - clk = 0; - test_num = 0; - - tb_btx_valid = 0; - tb_btx_data = 0; - #(10*`CP); - - /* ==== Test 1 Begin ==== */ - $display("\n=== test 1: receive 0x0123 for baseline functionality ==="); - test_num = 1; - tb_btx_data = 16'h0123; - tb_btx_valid = 1; - - #`CP; - tb_btx_valid = 0; - - #(100000*`CP); - /* ==== Test 1 End ==== */ - - /* ==== Test 2 Begin ==== */ - $display("\n=== test 2: receive 0x4567 for baseline functionality ==="); - test_num = 2; - tb_btx_data = 16'h4567; - tb_btx_valid = 1; - - #`CP; - tb_btx_valid = 0; - - #(100000*`CP); - /* ==== Test 2 End ==== */ - - /* ==== Test 3 Begin ==== */ - $display("\n=== test 3: receive 0x89AB for baseline functionality ==="); - test_num = 3; - tb_btx_data = 16'h89AB; - tb_btx_valid = 1; - - #`CP; - tb_btx_valid = 0; - - #(100000*`CP); - /* ==== Test 3 End ==== */ - - /* ==== Test 4 Begin ==== */ - $display("\n=== test 4: receive 0xCDEF for baseline functionality ==="); - test_num = 4; - tb_btx_data = 16'hCDEF; - tb_btx_valid = 1; - - #`CP; - tb_btx_valid = 0; - - #(100000*`CP); - /* ==== Test 4 End ==== */ - - $finish(); -end - - -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/ethernet_rx_tb.sv b/test/functional_sim/ethernet_rx_tb.sv deleted file mode 100644 index 89ee8d4..0000000 --- a/test/functional_sim/ethernet_rx_tb.sv +++ /dev/null @@ -1,98 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -`define FPGA_MAC 48'h69_69_5A_06_54_91 -`define HOST_MAC 48'h00_E0_4C_68_1E_0C -`define ETHERTYPE 16'h88_B5 - -module ethernet_rx_tb(); - - // https://www.youtube.com/watch?v=K35qOTQLNpA - logic clk; - - always begin - #5; - clk = !clk; - end - - logic crsdv; - logic [1:0] rxd; - - logic txen; - logic [1:0] txd; - - logic [39:0] mtx_payload; - logic mtx_start; - - mac_tx #( - .SRC_MAC(`HOST_MAC), - .DST_MAC(`FPGA_MAC), - .ETHERTYPE(`ETHERTYPE), - .PAYLOAD_LENGTH_BYTES(5) - ) mtx ( - .clk(clk), - - .payload(mtx_payload), - .start(mtx_start), - - .txen(txen), - .txd(txd)); - - assign rxd = txd; - assign crsdv = txen; - - logic [15:0] erx_addr; - logic [15:0] erx_data; - logic erx_rw; - logic erx_valid; - - ethernet_rx #( - .FPGA_MAC(`FPGA_MAC), - .ETHERTYPE(`ETHERTYPE) - ) erx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .addr_o(erx_addr), - .data_o(erx_data), - .rw_o(erx_rw), - .valid_o(erx_valid)); - - initial begin - $dumpfile("ethernet_rx_tb.vcd"); - $dumpvars(0, ethernet_rx_tb); - clk = 0; - mtx_payload = 0; - mtx_start = 0; - #50; - - // try to send a read request to the bus: - mtx_payload = 40'h01_0002_0001; - mtx_start = 1; - #10; - mtx_start = 0; - #10000; - - - - - // for (int i=0; i<32; i=i+1) begin - // mtx_payload = i; - // mtx_start = 0; - // #10; - // mtx_start = 1; - // #10; - // mtx_start = 0; - // while(!mrx_valid) #10; - - // #1000; - - // assert(mrx_payload == i) else $fatal(0, "data mismatch!"); - // end - $finish(); - end - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/ethernet_tx_tb.sv b/test/functional_sim/ethernet_tx_tb.sv deleted file mode 100644 index 0146753..0000000 --- a/test/functional_sim/ethernet_tx_tb.sv +++ /dev/null @@ -1,121 +0,0 @@ -`default_nettype none -//`timescale 1ns/1ps - -`define FPGA_MAC 48'h69_69_5A_06_54_91 -`define HOST_MAC 48'h00_E0_4C_68_1E_0C -`define ETHERTYPE 16'h88_B5 - -task send_on_etx_receive_on_mrx ( - input [15:0] data - ); - - ethernet_tx_tb.etx_data = data; - ethernet_tx_tb.etx_rw = 0; - ethernet_tx_tb.etx_valid = 0; - #10; - ethernet_tx_tb.etx_valid = 1; - #10; - ethernet_tx_tb.etx_valid = 0; - - while(!ethernet_tx_tb.mrx_valid) #10; - - $display(ethernet_tx_tb.mrx_payload); -endtask - -module ethernet_tx_tb(); - - // https://www.youtube.com/watch?v=K35qOTQLNpA - logic clk; - - always begin - #5; - clk = !clk; - end - - logic txen; - logic [1:0] txd; - - // ethernet tx - reg [15:0] etx_data; - reg etx_rw; - reg etx_valid; - - ethernet_tx #( - .FPGA_MAC(`FPGA_MAC), - .HOST_MAC(`HOST_MAC), - .ETHERTYPE(`ETHERTYPE) - ) etx ( - .clk(clk), - - .data_i(etx_data), - .rw_i(etx_rw), - .valid_i(etx_valid), - - .txen(txen), - .txd(txd)); - - // mac_rx, for decoding - logic crsdv; - logic [1:0] rxd; - - reg [55:0] mrx_payload; - reg mrx_valid; - - mac_rx #( - // this is the host mac since we're using mac_rx to impersonate - // the host computer, to which packets are currently addressed. - - .FPGA_MAC(`HOST_MAC), - .ETHERTYPE(`ETHERTYPE) - ) mrx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .payload(mrx_payload), - .valid(mrx_valid)); - - logic [15:0] where_ethertype_should_be; - logic [7:0] where_rw_should_be; - logic [15:0] where_addr_should_be; - logic [15:0] where_data_should_be; - assign {where_ethertype_should_be, where_rw_should_be, where_addr_should_be, where_data_should_be} = mrx_payload; - - assign rxd = txd; - assign crsdv = txen; - - initial begin - $dumpfile("ethernet_tx_tb.vcd"); - $dumpvars(0, ethernet_tx_tb); - clk = 0; - etx_data = 16'h6970; - etx_rw = 0; - etx_valid = 0; - #50; - - send_on_etx_receive_on_mrx(16'h6970); - - #10000; - - - - - // for (int i=0; i<32; i=i+1) begin - // mtx_payload = i; - // mtx_start = 0; - // #10; - // mtx_start = 1; - // #10; - // mtx_start = 0; - // while(!mrx_valid) #10; - - // #1000; - - // assert(mrx_payload == i) else $fatal(0, "data mismatch!"); - // end - $finish(); - end - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/io_core_tb/io_core.v b/test/functional_sim/io_core_tb/io_core.v deleted file mode 100644 index 8f8daa7..0000000 --- a/test/functional_sim/io_core_tb/io_core.v +++ /dev/null @@ -1,118 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -module io_core( - input wire bus_clk, - input wire user_clk, - - // inputs - input wire probe0, - input wire [1:0] probe1, - input wire [7:0] probe2, - input wire [19:0] probe3, - - // outputs - output reg probe4, - output reg [1:0] probe5, - output reg [7:0] probe6, - output reg [19:0] probe7, - - // input port - input wire [15:0] addr_i, - input wire [15:0] data_i, - input wire rw_i, - input wire valid_i, - - // output port - output reg [15:0] addr_o, - output reg [15:0] data_o, - output reg rw_o, - output reg valid_o - ); - - parameter BASE_ADDR = 0; - - reg strobe = 0; - - // configure buffers - // inputs - reg probe0_buf = 0; - reg [1:0] probe1_buf = 0; - reg [7:0] probe2_buf = 0; - reg [19:0] probe3_buf = 0; - - // outputs - reg probe4_buf = 1; // PROBE4_INITIAL_VALUE; - reg [1:0] probe5_buf = 3; // PROBE5_INITIAL_VALUE; - reg [7:0] probe6_buf = 6; // PROBE6_INITIAL_VALUE; - reg [19:0] probe7_buf = 7; // PROBE7_INITIAL_VALUE; - - initial begin - probe4 = 1; // PROBE4_INITIAL_VALUE; - probe5 = 3; // PROBE5_INITIAL_VALUE; - probe6 = 6; // PROBE6_INITIAL_VALUE; - probe7 = 7; // PROBE7_INITIAL_VALUE; - end - - // synchronize buffers and probes on strobe - always @(posedge user_clk) begin - if(strobe) begin - // update input buffers from input probes - probe0_buf <= probe0; - probe1_buf <= probe1; - probe2_buf <= probe2; - probe3_buf <= probe3; - - // update output buffers from output probes - probe4 <= probe4_buf; - probe5 <= probe5_buf; - probe6 <= probe6_buf; - probe7 <= probe7_buf; - end - end - - - // handle bus operations - always @(posedge bus_clk) begin - addr_o <= addr_i; - data_o <= data_i; - rw_o <= rw_i; - valid_o <= valid_i; - - // check if address is valid - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + 10)) begin - - if(!rw_i) begin // reads - case (addr_i) - BASE_ADDR + 0: data_o <= strobe; - - BASE_ADDR + 1: data_o <= probe0_buf; // width 1 - BASE_ADDR + 2: data_o <= probe1_buf; // width 2 - BASE_ADDR + 3: data_o <= probe2_buf; // width 8 - BASE_ADDR + 4: data_o <= probe3_buf[15:0]; // width 20 - BASE_ADDR + 5: data_o <= probe3_buf[19:16]; - - BASE_ADDR + 6: data_o <= probe4_buf; // width 1 - BASE_ADDR + 7: data_o <= probe5_buf; // width 2 - BASE_ADDR + 8: data_o <= probe6_buf; // width 8 - BASE_ADDR + 9: data_o <= probe7_buf[15:0]; // width 20 - BASE_ADDR + 10: data_o <= probe7_buf[19:16]; - endcase - end - - else begin // writes - case (addr_i) - BASE_ADDR + 0: strobe <= data_i[0]; - - BASE_ADDR + 6: probe4_buf <= data_i[0]; - BASE_ADDR + 7: probe5_buf <= data_i[1:0]; - BASE_ADDR + 8: probe6_buf <= data_i[7:0]; - BASE_ADDR + 9: probe7_buf[15:0] <= data_i; - BASE_ADDR + 10: probe7_buf[19:16] <= data_i[3:0]; - endcase - end - end - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/io_core_tb/io_core_tb.sv b/test/functional_sim/io_core_tb/io_core_tb.sv deleted file mode 100644 index 3a1caef..0000000 --- a/test/functional_sim/io_core_tb/io_core_tb.sv +++ /dev/null @@ -1,277 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -task read_reg ( - input [15:0] addr, - output [15:0] data, - input string desc - ); - - io_core_tb.tb_io_addr = addr; - io_core_tb.tb_io_rw = 0; - io_core_tb.tb_io_valid = 1; - #`CP - io_core_tb.tb_io_valid = 0; - while (!io_core_tb.io_tb_valid) #`CP; - data = io_core_tb.io_tb_data; - - $display(" -> read 0x%h from addr 0x%h (%s)", data, addr, desc); -endtask - -task write_reg( - input [15:0] addr, - input [15:0] data, - input string desc - ); - - io_core_tb.tb_io_addr = addr; - io_core_tb.tb_io_data = data; - io_core_tb.tb_io_rw = 1; - io_core_tb.tb_io_valid = 1; - #`CP - io_core_tb.tb_io_valid = 0; - while (!io_core_tb.io_tb_valid) #`CP; - - $display(" -> wrote 0x%h to addr 0x%h (%s)", data, addr, desc); -endtask - -task write_and_verify( - input [15:0] addr, - input [15:0] write_data, - input string desc - ); - - reg [15:0] read_data; - - write_reg(addr, write_data, desc); - read_reg(addr, read_data, desc); - assert(read_data == write_data) else $fatal(0, "data read does not match data written!"); -endtask - -// task read_all_reg(); -// string desc; -// for(int i = 0; i < (io_core_tb.la.block_mem.MAX_ADDR); i++) begin - -// if(i == io_core_tb.la.fsm_registers.BASE_ADDR) desc = "FSM"; -// if(i == io_core_tb.la.trig_blk.BASE_ADDR) desc = "TRIG BLK"; -// if(i == io_core_tb.la.block_mem.BASE_ADDR) desc = "SAMPLE MEM"; - -// read_reg(i, io_core_tb.read_value, desc); -// end -// endtask - -module io_core_tb; - - // boilerplate - logic clk; - integer test_num; - - // inputs - logic probe0; - logic [1:0] probe1; - logic [7:0] probe2; - logic [19:0] probe3; - - // outputs - logic probe4; - logic [1:0] probe5; - logic [7:0] probe6; - logic [19:0] probe7; - - // tb -> io bus - logic [15:0] tb_io_addr; - logic [15:0] tb_io_data; - logic tb_io_rw; - logic tb_io_valid; - - // la -> io bus - logic [15:0] io_tb_addr; - logic [15:0] io_tb_data; - logic io_tb_rw; - logic io_tb_valid; - - - io_core #(.BASE_ADDR(0)) io( - .bus_clk(clk), - .user_clk(clk), - - // inputs - .probe0(probe0), - .probe1(probe1), - .probe2(probe2), - .probe3(probe3), - - // outputs - .probe4(probe4), - .probe5(probe5), - .probe6(probe6), - .probe7(probe7), - - // input port - .addr_i(tb_io_addr), - .data_i(tb_io_data), - .rw_i(tb_io_rw), - .valid_i(tb_io_valid), - - // output port - .addr_o(io_tb_addr), - .data_o(io_tb_data), - .rw_o(io_tb_rw), - .valid_o(io_tb_valid)); - - always begin - #`HCP - clk = !clk; - end - - logic [15:0] read_data; - - initial begin - $dumpfile("io_core_tb.vcd"); - $dumpvars(0, io_core_tb); - - // setup and reset - clk = 0; - test_num = 0; - - tb_io_addr = 0; - tb_io_data = 0; - tb_io_rw = 0; - tb_io_valid = 0; - - probe0 = 0; - probe1 = 1; - probe2 = 2; - probe3 = 3; - - // #`HCP - #(10*`CP); - - /* ==== Test 1 Begin ==== */ - $display("\n=== test 1: read initial register states ==="); - test_num = 1; - read_reg(0, read_data, "strobe"); - read_reg(1, read_data, "probe0"); - read_reg(2, read_data, "probe1"); - read_reg(3, read_data, "probe2"); - read_reg(4, read_data, "probe3[15:0]"); - read_reg(5, read_data, "probe3[19:16]"); - - read_reg(6, read_data, "probe4"); - read_reg(7, read_data, "probe5"); - read_reg(8, read_data, "probe6"); - read_reg(9, read_data, "probe7[15:0]"); - read_reg(10, read_data, "probe7[19:16]"); - #(10*`CP); - /* ==== Test 1 End ==== */ - - /* ==== Test 2 Begin ==== */ - $display("\n=== test 2: assert input buffers initialized correctly ==="); - test_num = 2; - read_reg(0, read_data, "strobe"); - assert(read_data == 0) else $fatal(0, "strobe does not initialize to zero!"); - assert(io.strobe == 0) else $fatal(0, "strobe does not initialize to zero!"); - - read_reg(1, read_data, "probe0"); - assert(read_data == 0) else $fatal(0, "probe0_buf does not initialize to zero!"); - assert(io.probe0_buf == 0) else $fatal(0, "probe0_buf does not initialize to zero!"); - - read_reg(2, read_data, "probe1"); - assert(read_data == 0) else $fatal(0, "probe1_buf does not initialize to zero!"); - assert(io.probe1_buf == 0) else $fatal(0, "probe1_buf does not initialize to zero!"); - - read_reg(3, read_data, "probe2"); - assert(read_data == 0) else $fatal(0, "probe2_buf does not initialize to zero!"); - assert(io.probe2_buf == 0) else $fatal(0, "probe2_buf does not initialize to zero!"); - - read_reg(4, read_data, "probe3[15:0]"); - assert(read_data == 0) else $fatal(0, "probe3_buf does not initialize to zero!"); - read_reg(5, read_data, "probe3[19:16]"); - assert(read_data == 0) else $fatal(0, "probe3_buf does not initialize to zero!"); - assert(io.probe3_buf == 0) else $fatal(0, "probe3_buf does not initialize to zero!"); - - #(10*`CP); - /* ==== Test 2 End ==== */ - - - /* ==== Test 3 Begin ==== */ - $display("\n=== test 3: assert outputs and output buffers initialized correctly ==="); - test_num = 3; - read_reg(6, read_data, "probe4"); - assert(read_data == 1) else $fatal(0, "probe4 does not initialize correctly!"); - assert(io.probe4_buf == 1) else $fatal(0, "probe4_buf does not initialize correctly!"); - assert(io.probe4 == 1) else $fatal(0, "probe4 does not initialize correctly!"); - - read_reg(7, read_data, "probe5"); - assert(read_data == 3) else $fatal(0, "probe5 does not initialize correctly!"); - assert(io.probe5_buf == 3) else $fatal(0, "probe5_buf does not initialize correctly!"); - assert(io.probe5 == 3) else $fatal(0, "probe5 does not initialize correctly!"); - - read_reg(8, read_data, "probe6"); - assert(read_data == 6) else $fatal(0, "probe6 does not initialize correctly!"); - assert(io.probe6_buf == 6) else $fatal(0, "probe6_buf does not initialize correctly!"); - assert(io.probe6 == 6) else $fatal(0, "probe6 does not initialize correctly!"); - - read_reg(9, read_data, "probe7[15:0]"); - assert(read_data == 7) else $fatal(0, "probe7 does not initialize correctly!"); - read_reg(10, read_data, "probe7[19:16]"); - assert(read_data == 0) else $fatal(0, "probe7 does not initialize correctly!"); - assert(io.probe7_buf == 7) else $fatal(0, "probe7_buf does not initialize correctly!"); - assert(io.probe7 == 7) else $fatal(0, "probe7 does not initialize correctly!"); - - - #(10*`CP); - /* ==== Test 3 End ==== */ - - /* ==== Test 4 Begin ==== */ - $display("\n=== test 4: write new output value to each output probe==="); - test_num = 4; - write_reg(6, 0, "probe4"); - assert(io.probe4_buf == 0) else $fatal(0, "probe4_buf does not update correctly!"); - assert(io.probe4 != 0) else $fatal(0, "probe4 updated without strobing!"); - - write_reg(7, 0, "probe5"); - assert(io.probe5_buf == 0) else $fatal(0, "probe5_buf does not update correctly!"); - assert(io.probe5 != 0) else $fatal(0, "probe5 updated without strobing!"); - - write_reg(8, 0, "probe6"); - assert(io.probe6_buf == 0) else $fatal(0, "probe6_buf does not update correctly!"); - assert(io.probe6 != 0) else $fatal(0, "probe6 updated without strobing!"); - - write_reg(9, 0, "probe7[15:0]"); - write_reg(10, 0, "probe7[19:16]"); - assert(io.probe7_buf == 0) else $fatal(0, "probe7_buf does not update correctly!"); - assert(io.probe7 != 0) else $fatal(0, "probe7 updated without strobing!"); - #(10*`CP); - /* ==== Test 4 End ==== */ - - /* ==== Test 5 Begin ==== */ - $display("\n=== test 5: strobe core, check that inputs and outputs updated ==="); - test_num = 5; - - write_reg(0, 1, "strobe"); - write_reg(0, 0, "strobe"); - - assert(io.probe4 == 0) else $fatal(0, "probe4 did not update correctly!"); - assert(io.probe5 == 0) else $fatal(0, "probe5 did not update correctly!"); - assert(io.probe6 == 0) else $fatal(0, "probe6 did not update correctly!"); - assert(io.probe7 == 0) else $fatal(0, "probe7 did not update correctly!"); - - assert(io.probe0_buf == 0) else $fatal(0, "probe0_buf did not update correctly!"); - assert(io.probe1_buf == 1) else $fatal(0, "probe1_buf did not update correctly!"); - assert(io.probe2_buf == 2) else $fatal(0, "probe2_buf did not update correctly!"); - assert(io.probe3_buf == 3) else $fatal(0, "probe3_buf did not update correctly!"); - assert(io.probe4_buf == 0) else $fatal(0, "probe4_buf did not update correctly!"); - assert(io.probe5_buf == 0) else $fatal(0, "probe5_buf did not update correctly!"); - assert(io.probe6_buf == 0) else $fatal(0, "probe6_buf did not update correctly!"); - assert(io.probe7_buf == 0) else $fatal(0, "probe7_buf did not update correctly!"); - /* ==== Test 5 End ==== */ - - - $finish(); - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv deleted file mode 100644 index 36288de..0000000 --- a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv +++ /dev/null @@ -1,257 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -task read_reg ( - input [15:0] addr, - output [15:0] data, - input string desc - ); - - logic_analyzer_tb.tb_la_addr = addr; - logic_analyzer_tb.tb_la_rw = 0; - logic_analyzer_tb.tb_la_valid = 1; - #`CP - logic_analyzer_tb.tb_la_valid = 0; - while (!logic_analyzer_tb.la_tb_valid) #`CP; - data = logic_analyzer_tb.la_tb_data; - - $display(" -> read 0x%h from addr 0x%h (%s)", data, addr, desc); -endtask - -task write_reg( - input [15:0] addr, - input [15:0] data, - input string desc - ); - - logic_analyzer_tb.tb_la_addr = addr; - logic_analyzer_tb.tb_la_data = data; - logic_analyzer_tb.tb_la_rw = 1; - logic_analyzer_tb.tb_la_valid = 1; - #`CP - logic_analyzer_tb.tb_la_valid = 0; - while (!logic_analyzer_tb.la_tb_valid) #`CP; - - $display(" -> wrote 0x%h to addr 0x%h (%s)", data, addr, desc); -endtask - -task write_and_verify( - input [15:0] addr, - input [15:0] write_data, - input string desc - ); - - reg [15:0] read_data; - - write_reg(addr, write_data, desc); - read_reg(addr, read_data, desc); - assert(read_data == write_data) else $fatal(0, "data read does not match data written!"); -endtask - -task read_all_reg(); - string desc; - for(int i = 0; i < (logic_analyzer_tb.la.block_mem.MAX_ADDR); i++) begin - - if(i == logic_analyzer_tb.la.fsm_registers.BASE_ADDR) desc = "FSM"; - if(i == logic_analyzer_tb.la.trig_blk.BASE_ADDR) desc = "TRIG BLK"; - if(i == logic_analyzer_tb.la.block_mem.BASE_ADDR) desc = "SAMPLE MEM"; - - read_reg(i, logic_analyzer_tb.read_value, desc); - end -endtask - -module logic_analyzer_tb; - - // boilerplate - logic clk; - integer test_num; - - // signal generator - logic larry; - logic curly; - logic moe; - logic [3:0] shemp; - - // tb -> la bus - logic [15:0] tb_la_addr; - logic [15:0] tb_la_data; - logic tb_la_rw; - logic tb_la_valid; - - // la -> tb bus - logic [15:0] la_tb_addr; - logic [15:0] la_tb_data; - logic la_tb_rw; - logic la_tb_valid; - - - logic_analyzer la( - .clk(clk), - - // probes - .larry(larry), - .curly(curly), - .moe(moe), - .shemp(shemp), - - // input port - .addr_i(tb_la_addr), - .data_i(tb_la_data), - .rw_i(tb_la_rw), - .valid_i(tb_la_valid), - - // output port - .addr_o(la_tb_addr), - .data_o(la_tb_data), - .rw_o(la_tb_rw), - .valid_o(la_tb_valid)); - - always begin - #`HCP - clk = !clk; - end - - reg [15:0] read_value; - - initial begin - $dumpfile("logic_analyzer_tb.vcd"); - $dumpvars(0, logic_analyzer_tb); - - // setup and reset - clk = 0; - test_num = 0; - - tb_la_addr = 0; - tb_la_data = 0; - tb_la_rw = 0; - tb_la_valid = 0; - - larry = 0; - curly = 0; - moe = 0; - shemp = 0; - #`HCP - #(10*`CP); - - - // /* ==== Test 2 Begin ==== */ - // $display("\n=== test 2: read/write to trigger block registers, verify ==="); - // test_num = 2; - - // // larry - // write_and_verify(3, 0, "larry_op"); - // write_and_verify(3, 2, "larry_op"); - // write_and_verify(3, 0, "larry_op"); - - // write_and_verify(4, 0, "larry_arg"); - // write_and_verify(4, 1, "larry_arg"); - // write_and_verify(4, 0, "larry_arg"); - - // // curly - // write_and_verify(5, 0, "curly_op"); - // write_and_verify(5, 3, "curly_op"); - // write_and_verify(5, 0, "curly_op"); - - // write_and_verify(6, 0, "curly_arg"); - // write_and_verify(6, 1, "curly_arg"); - // write_and_verify(6, 0, "curly_arg"); - - // // moe - // write_and_verify(7, 0, "moe_op"); - // write_and_verify(7, 5, "moe_op"); - // write_and_verify(7, 0, "moe_op"); - - // write_and_verify(8, 0, "moe_arg"); - // write_and_verify(8, 1, "moe_arg"); - // write_and_verify(8, 0, "moe_arg"); - - // // shemp - // write_and_verify(9, 0, "shemp_op"); - // write_and_verify(9, 7, "shemp_op"); - // write_and_verify(9, 0, "shemp_op"); - - // write_and_verify(10, 0, "shemp_arg"); - // write_and_verify(10, 7, "shemp_arg"); - // write_and_verify(10, 0, "shemp_arg"); - - // #(10*`CP); - - // /* ==== Test 2 End ==== */ - - - /* ==== Test 4 Begin ==== */ - $display("\n=== test 4: verify FSM does move out of IDLE when running ==="); - test_num = 4; - - $display(" -> setting up trigger (larry == 1)"); - write_reg(la.trig_blk.BASE_ADDR + 0, 8, "larry_op"); - write_reg(la.trig_blk.BASE_ADDR + 1, 1, "larry_arg"); - - $display(" -> requesting start"); - write_reg(3, 1, "request_start"); - write_reg(3, 0, "request_start"); - #`CP - - $display(" -> set larry = 1"); - larry = 1; - - // read - $display(" -> la core is in state 0x%h", la.fsm_registers.state); - $display(" -> wait a clock cycle"); - #`CP - $display(" -> la core is in state 0x%h", la.fsm_registers.state); - - // run until the FILLED state is reached - $display(" -> wait until FILLED state is reached"); - while (la.fsm_registers.state != la.la_controller.CAPTURED) begin - {larry, curly, moe, shemp} = {larry, curly, moe, shemp} + 1; - #`CP; - end - - $display(" -> read from sample memory:"); - read_all_reg(); - - #(200*`CP); - /* ==== Test 4 End ==== */ - - // /* ==== Test 5 Begin ==== */ - // $display("\n=== test 5: change trigger to fire on shemp > 3, and verify ==="); - // test_num = 5; - - // write_and_verify(9, 6, "shemp_op"); // set operation to GT - // write_and_verify(10, 3, "shemp_arg"); // set argument to 3 - - // assert( (la.fsm_registers.state == la.la_controller.IDLE) || (la.fsm_registers.state == la.la_controller.CAPTURED) ) - // else $fatal(0, "core is running when it shouldn't be!"); - - // larry = 0; - // curly = 0; - // moe = 0; - // shemp = 0; - - // // start the core - // // TODO: start the core - - // shemp = 4; - // $display(" -> set shemp = 4"); - - // // run until the FILLED state is reached - // $display(" -> wait until FILLED state is reached"); - // while (la.fsm_registers.state != la.la_controller.CAPTURED) begin - // {larry, curly, moe, shemp} = {larry, curly, moe, shemp} + 2; - // #`CP; - // end - - // $display(" -> read from sample memory:"); - // read_all_reg(); - - // #(10*`CP); - // /* ==== Test 5 End ==== */ - - $finish(); - end -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/logic_analyzer_tb/manta.yaml b/test/functional_sim/logic_analyzer_tb/manta.yaml deleted file mode 100644 index cbd04c1..0000000 --- a/test/functional_sim/logic_analyzer_tb/manta.yaml +++ /dev/null @@ -1,19 +0,0 @@ ---- -cores: - logic_analyzer: - type: logic_analyzer - sample_depth: 128 - - probes: - larry: 1 - curly: 1 - moe: 1 - shemp: 4 - - triggers: - - larry && curly && ~moe - -uart: - port: "auto" - baudrate: 115200 - clock_freq: 100000000 \ No newline at end of file diff --git a/test/functional_sim/mac_tb.sv b/test/functional_sim/mac_tb.sv deleted file mode 100644 index c812fc2..0000000 --- a/test/functional_sim/mac_tb.sv +++ /dev/null @@ -1,86 +0,0 @@ -`default_nettype none -`timescale 1ns/1ps - -`define FPGA_MAC 48'h69_69_5A_06_54_91 -`define HOST_MAC 48'h00_E0_4C_68_1E_0C -`define ETHERTYPE 16'h88_B5 - - -module mac_tb(); - logic clk; - - always begin - #5; - clk = !clk; - end - - logic crsdv; - logic [1:0] rxd; - - logic txen; - logic [1:0] txd; - - // this testbench makes sure that our rx pipeline is good, - // so we'll have mtx simulate the host machine and blast - // 5 bytes (plus padding) onto our fake RMII - logic [39:0] mtx_payload; - logic mtx_start; - - logic [39:0] mrx_payload; - logic mrx_valid; - - mac_tx #( - .SRC_MAC(`HOST_MAC), - .DST_MAC(`FPGA_MAC), - .ETHERTYPE(`ETHERTYPE), - .PAYLOAD_LENGTH_BYTES(5) - ) mtx ( - .clk(clk), - - .payload(mtx_payload), - .start(mtx_start), - - .txen(txen), - .txd(txd)); - - assign rxd = txd; - assign crsdv = txen; - - mac_rx #( - .FPGA_MAC(`FPGA_MAC), - .ETHERTYPE(`ETHERTYPE) - ) mrx ( - .clk(clk), - - .crsdv(crsdv), - .rxd(rxd), - - .payload(mrx_payload), - .valid(mrx_valid)); - - initial begin - $dumpfile("mac_tb.vcd"); - $dumpvars(0, mac_tb); - clk = 0; - mtx_payload = 0; - mtx_start = 0; - #10; - - for (int i=0; i<32; i=i+1) begin - mtx_payload = i; - mtx_start = 0; - #10; - mtx_start = 1; - #10; - mtx_start = 0; - while(!mrx_valid) #10; - - #1000; - - assert(mrx_payload == i) else $fatal(0, "data mismatch!"); - end - $finish(); - end - -endmodule -`default_nettype wire \ No newline at end of file diff --git a/test/functional_sim/uart_rx_tb.sv b/test/functional_sim/uart_rx_tb.sv deleted file mode 100644 index 9993eb3..0000000 --- a/test/functional_sim/uart_rx_tb.sv +++ /dev/null @@ -1,94 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -task automatic test_receive ( - input [7:0] data, - input integer CLOCKS_PER_BAUD - ); - - // send a byte to uart_rx, and check that it receives properly - - integer data_bit = 0; - logic valid_has_been_asserted = 0; - - for(int i=0; i < (10*CLOCKS_PER_BAUD); i++) begin - - // clock out data bits on each baud period - data_bit = i / CLOCKS_PER_BAUD; - if (data_bit == 0) uart_rx_tb.tb_urx_rx = 0; - else if ((data_bit > 0) && (data_bit < 9)) uart_rx_tb.tb_urx_rx = data[data_bit-1]; - else uart_rx_tb.tb_urx_rx = 1; - - - // every cycle, run checks on uart_rx: - - // make sure valid isn't asserted before end of byte - if (data_bit < 9) begin - assert(uart_rx_tb.urx_tb_valid == 0) else $fatal(0, "valid asserted before end of byte!"); - end - - // make sure valid is only asserted once - if (valid_has_been_asserted) begin - assert(uart_rx_tb.urx_tb_valid == 0) else $fatal(0, "valid asserted more than once!"); - end - - // make sure byte is presented once last bit has been clocked out - if (uart_rx_tb.urx_tb_valid) begin - assert(data_bit == 9) else $fatal(0, "byte presented before it is complete"); - assert(uart_rx_tb.urx_tb_data == data) else $fatal(0, "wrong data!"); - valid_has_been_asserted = 1; - end - - #`CP; - end - - // make sure valid was asserted at some point - assert (valid_has_been_asserted) else $fatal(0, "valid not asserted!"); -endtask - -module uart_rx_tb(); - logic clk; - integer test_num; - - logic tb_urx_rx; - logic [7:0] urx_tb_data; - logic urx_tb_valid; - uart_rx #(.CLOCKS_PER_BAUD(10)) urx ( - .clk(clk), - .rx(tb_urx_rx), - .data_o(urx_tb_data), - .valid_o(urx_tb_valid)); - - always begin - #`HCP - clk = !clk; - end - - initial begin - $dumpfile("uart_rx_tb.vcd"); - $dumpvars(0, uart_rx_tb); - clk = 0; - test_num = 0; - tb_urx_rx = 1; - #`HCP; - - // test all possible bytes - test_num = test_num + 1; - for(int i=0; i < 256; i++) begin - test_receive(i, 10); - #(100*`CP); - end - - // test all possible bytes (no delay between them) - test_num = test_num + 1; - for(int i=0; i < 256; i++) begin - test_receive(i, 10); - end - - $finish(); - end -endmodule - -`default_nettype wire diff --git a/test/functional_sim/uart_tx_tb.sv b/test/functional_sim/uart_tx_tb.sv deleted file mode 100644 index 308069e..0000000 --- a/test/functional_sim/uart_tx_tb.sv +++ /dev/null @@ -1,99 +0,0 @@ -`default_nettype none - -`define CP 10 -`define HCP 5 - -task automatic transmit_byte ( - input [7:0] data, - input integer CLOCKS_PER_BAUD - ); - - // send a byte from uart_tx, and check that it transmits properly - - integer data_bit = 0; - for(int i=0; i < (10*CLOCKS_PER_BAUD)-1; i++) begin - - // check that data bit is correct on every baud period - data_bit = i / CLOCKS_PER_BAUD; - if (data_bit == 0) begin - assert(uart_tx_tb.utx_tb_tx == 0) else $fatal(0, "wrong start bit!"); - end - - else if ((data_bit > 0) && (data_bit < 9)) begin - assert(uart_tx_tb.utx_tb_tx == data[data_bit-1]) else $fatal(0, "wrong data bit!"); - end - - else begin - assert(uart_tx_tb.utx_tb_tx == 1) else $fatal(0, "wrong stop bit!"); - end - - - // check that done is not asserted during transmisison - assert(!uart_tx_tb.utx_tb_done) else $fatal(0, "wrong done!"); - #`CP; - end - - // assert that done is asserted at end of transmission - assert(uart_tx_tb.utx_tb_done) else $fatal(0, "wrong done!"); -endtask - -module uart_tx_tb(); - logic clk; - integer test_num; - - logic [7:0] tb_utx_data; - logic tb_utx_start; - logic utx_tb_done; - logic utx_tb_tx; - - uart_tx #(.CLOCKS_PER_BAUD(10)) utx ( - .clk(clk), - - .data_i(tb_utx_data), - .start_i(tb_utx_start), - .done_o(utx_tb_done), - - .tx(utx_tb_tx)); - - always begin - #`HCP - clk = !clk; - end - - initial begin - $dumpfile("uart_tx_tb.vcd"); - $dumpvars(0, uart_tx_tb); - clk = 0; - test_num = 0; - - tb_utx_data = 0; - tb_utx_start = 0; - #`HCP; - - // test all possible bytes - test_num = test_num + 1; - for(int i=0; i < 256; i++) begin - tb_utx_start = 1; - tb_utx_data = i; - #`CP; - tb_utx_start = 0; - tb_utx_data = 0; - transmit_byte(i, 10); - #(100*`CP); - end - - // test all possible bytes (no delay between them) - test_num = test_num + 1; - for(int i=0; i < 256; i++) begin - tb_utx_start = 1; - tb_utx_data = i; - #`CP; - tb_utx_data = 0; - transmit_byte(i, 10); - end - - $finish(); - end -endmodule - -`default_nettype wire diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py new file mode 100644 index 0000000..89c3d4d --- /dev/null +++ b/test/test_bridge_rx_sim.py @@ -0,0 +1,120 @@ +from amaranth.sim import Simulator +from manta.uart import RecieveBridge +from manta.utils import * + + +bridge_rx = RecieveBridge() + + +def verify_read_decoding(bytes, addr): + """ + Send a series of bytes to the receive bridge, and verify that the bridge places + a read request with the appropriate address on the internal bus. + """ + valid_asserted = False + yield bridge_rx.valid_i.eq(1) + + for i, byte in enumerate(bytes): + yield bridge_rx.data_i.eq(byte) + + if (yield bridge_rx.valid_o) and (i > 0): + valid_asserted = True + if (yield bridge_rx.addr_o) != addr: + raise ValueError("wrong addr!") + + if (yield bridge_rx.rw_o) != 0: + raise ValueError("wrong rw!") + + if (yield bridge_rx.data_o) != 0: + raise ValueError("wrong data!") + + yield + + yield bridge_rx.valid_i.eq(0) + yield bridge_rx.data_i.eq(0) + + if not valid_asserted and not (yield bridge_rx.valid_o): + raise ValueError("Bridge failed to output valid message.") + + +def verify_write_decoding(bytes, addr, data): + """ + Send a series of bytes to the receive bridge, and verify that the bridge places + a write request with the appropriate address and data on the internal bus. + """ + valid_asserted = False + yield bridge_rx.valid_i.eq(1) + + for i, byte in enumerate(bytes): + yield bridge_rx.data_i.eq(byte) + + if (yield bridge_rx.valid_o) and (i > 0): + valid_asserted = True + if (yield bridge_rx.addr_o) != addr: + raise ValueError("wrong addr!") + + if (yield bridge_rx.rw_o) != 1: + raise ValueError("wrong rw!") + + if (yield bridge_rx.data_o) != data: + raise ValueError("wrong data!") + + yield + + yield bridge_rx.valid_i.eq(0) + yield bridge_rx.data_i.eq(0) + + if not valid_asserted and not (yield bridge_rx.valid_o): + raise ValueError("Bridge failed to output valid message.") + + +def verify_bad_bytes(bytes): + """ + Send a series of bytes to the receive bridge, and verify that the bridge does not + place any transaction on the internal bus. + """ + yield bridge_rx.valid_i.eq(1) + + for byte in bytes: + yield bridge_rx.data_i.eq(byte) + + if (yield bridge_rx.valid_o): + raise ValueError("Bridge decoded invalid message.") + + yield + + yield bridge_rx.valid_i.eq(0) + + +def test_read_decode(): + def testbench(): + yield from verify_read_decoding(b"R0000\r\n", 0x0000) + yield from verify_read_decoding(b"R1234\r\n", 0x1234) + yield from verify_read_decoding(b"RBABE\r\n", 0xBABE) + yield from verify_read_decoding(b"R5678\n", 0x5678) + yield from verify_read_decoding(b"R9ABC\r", 0x9ABC) + + simulate(bridge_rx, testbench) + + +def test_write_decode(): + def testbench(): + yield from verify_write_decoding(b"W12345678\r\n", 0x1234, 0x5678) + yield from verify_write_decoding(b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF) + yield from verify_write_decoding(b"WDEADBEEF\r", 0xDEAD, 0xBEEF) + yield from verify_write_decoding(b"WB0BACAFE\n", 0xB0BA, 0xCAFE) + + simulate(bridge_rx, testbench) + + +def test_no_decode(): + def testbench(): + yield from verify_bad_bytes(b"RABC\r\n") + yield from verify_bad_bytes(b"R12345\r\n") + yield from verify_bad_bytes(b"M\r\n") + yield from verify_bad_bytes(b"W123456789101112131415161718191201222\r\n") + yield from verify_bad_bytes(b"RABCG\r\n") + yield from verify_bad_bytes(b"WABC[]()##*@\r\n") + yield from verify_bad_bytes(b"R\r\n") + + simulate(bridge_rx, testbench) diff --git a/test/test_bridge_tx_sim.py b/test/test_bridge_tx_sim.py new file mode 100644 index 0000000..9a1568d --- /dev/null +++ b/test/test_bridge_tx_sim.py @@ -0,0 +1,67 @@ +from amaranth.sim import Simulator +from manta.uart import TransmitBridge +from manta.utils import * +from random import randint, sample + + +bridge_tx = TransmitBridge() + + +def verify_encoding(data, bytes): + """ + Place a read response on the internal bus, and verify that the sequence of bytes + sent from TransmitBridge matches the provided bytestring `bytes`. + + This function also models an ideal UARTTransmitter module, which begins transmitting + bytes when `start` is asserted, and reports when it is done by asserting `done`. + """ + + # Place a read response on the internal bus + yield bridge_tx.data_i.eq(data) + yield bridge_tx.valid_i.eq(1) + yield bridge_tx.rw_i.eq(0) + yield bridge_tx.done_i.eq(1) + + yield + + yield bridge_tx.data_i.eq(0) + yield bridge_tx.valid_i.eq(0) + yield bridge_tx.rw_i.eq(0) + + yield + + # Model the UARTTransmitter + sent_bytes = b"" + iters = 0 + + while len(sent_bytes) < len(bytes): + # If start_o is asserted, set done_i to zero, then delay, then set it back to one + if (yield bridge_tx.start_o): + yield bridge_tx.done_i.eq(0) + sent_bytes += (yield bridge_tx.data_o).to_bytes(1, "big") + + yield bridge_tx.done_i.eq(0) + for _ in range(10): + yield + + yield bridge_tx.done_i.eq(1) + yield + + # Time out if not enough bytes after trying to get bytes 15 times + iters += 1 + if iters > 15: + raise ValueError("Timed out waiting for bytes.") + + # Verify bytes sent from ReceiveBridge match expected_bytes + if sent_bytes != bytes: + raise ValueError(f"Received {sent_bytes} instead of {bytes}.") + + +def test_some_random_values(): + def testbench(): + for i in sample(range(0xFFFF), k=5000): + expected = f"D{i:04X}\r\n".encode("ascii") + print(i) + yield from verify_encoding(i, expected) + + simulate(bridge_tx, testbench) diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py new file mode 100644 index 0000000..25f0b2c --- /dev/null +++ b/test/test_io_core_hw.py @@ -0,0 +1,129 @@ +from amaranth import * +from amaranth_boards.nexys4ddr import Nexys4DDRPlatform +from amaranth_boards.icestick import ICEStickPlatform +from manta import Manta +from manta.utils import * +import pytest +from random import randint + + +class IOCoreLoopbackTest(Elaboratable): + def __init__(self, platform, port): + self.platform = platform + self.port = port + + self.config = self.platform_specific_config() + self.m = Manta(self.config) + + def platform_specific_config(self): + return { + "cores": { + "io_core": { + "type": "io", + "inputs": {"probe0": 1, "probe1": 2, "probe2": 8, "probe3": 20}, + "outputs": { + "probe4": {"width": 1, "initial_value": 1}, + "probe5": { + "width": 2, + "initial_value": 2, + }, + "probe6": 8, + "probe7": {"width": 20, "initial_value": 65538}, + }, + } + }, + "uart": { + "port": self.port, + "baudrate": 3e6, + "clock_freq": self.platform.default_clk_frequency, + }, + } + + def elaborate(self, platform): + m = Module() + m.submodules["manta"] = self.m + + uart_pins = platform.request("uart") + + m.d.comb += [ + self.m.io_core.probe0.eq(self.m.io_core.probe4), + self.m.io_core.probe1.eq(self.m.io_core.probe5), + self.m.io_core.probe2.eq(self.m.io_core.probe6), + self.m.io_core.probe3.eq(self.m.io_core.probe7), + self.m.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.m.interface.tx), + ] + + return m + + def build_and_program(self): + self.platform.build(self, do_program=True) + + def verify_output_probe_initial_values(self): + """ + Test that all output probes take their expected initial values. + We can't really test for the same of input probes, since the + strobe register pulses every time the get_probe() method is called. + """ + + # Test that all output probes take their initial values + inputs = self.config["cores"]["io_core"]["inputs"] + outputs = self.config["cores"]["io_core"]["outputs"] + + for name, attrs in outputs.items(): + actual = self.m.io_core.get_probe(name) + + if isinstance(attrs, dict): + if "initial_value" in attrs: + expected = attrs["initial_value"] + + else: + expected = 0 + + if actual != expected: + raise ValueError( + f"Output probe {name} took initial value of {actual} instead of {expected}." + ) + + def verify_probes_update(self): + """ + This design ties all the output probes to input probes, so this + test sets the outputs to random values, and verifies the inputs match + """ + inputs = self.config["cores"]["io_core"]["inputs"] + outputs = self.config["cores"]["io_core"]["outputs"] + + # The config is specified in such a way that the first output is + # connected to the first output, the second output is connected + # to the second input, and so on... + for input, output in zip(inputs, outputs): + width = self.config["cores"]["io_core"]["inputs"][input] + value = randint(0, 2**width - 1) + + self.m.io_core.set_probe(output, value) + readback = self.m.io_core.get_probe(input) + + if readback != value: + raise ValueError( + f"Reading {output} through {input} yielded {readback} instead of {value}!" + ) + + else: + print( + f"Reading {output} through {input} yielded {readback} as expected." + ) + + def verify(self): + self.build_and_program() + self.verify_output_probe_initial_values() + self.verify_probes_update() + + +@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") +def test_output_probe_initial_values_xilinx(): + IOCoreLoopbackTest(Nexys4DDRPlatform(), "/dev/ttyUSB2").verify() + + +@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") +def test_output_probe_initial_values_ice40(): + IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB1").verify() diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py new file mode 100644 index 0000000..5ef1405 --- /dev/null +++ b/test/test_io_core_sim.py @@ -0,0 +1,155 @@ +from amaranth.sim import Simulator +from manta.io_core import IOCore +from manta.utils import * +from random import randint + +config = { + "type": "io", + "inputs": {"probe0": 1, "probe1": 2, "probe2": 8, "probe3": 20}, + "outputs": { + "probe4": {"width": 1, "initial_value": 1}, + "probe5": {"width": 2, "initial_value": 2}, + "probe6": 8, + "probe7": {"width": 20, "initial_value": 65538}, + }, +} + +io_core = IOCore(config, base_addr=0, interface=None) + + +def pulse_strobe_register(): + strobe_addr = io_core.mmap["strobe"]["addrs"][0] + yield from write_register(io_core, strobe_addr, 0) + yield from write_register(io_core, strobe_addr, 1) + yield from write_register(io_core, strobe_addr, 0) + + +def test_output_probe_initial_values(): + def testbench(): + # Verify all output probes initialize to the values in the config + for name, attrs in config["outputs"].items(): + initial_value = 0 + if isinstance(attrs, dict): + if "initial_value" in attrs: + initial_value = attrs["initial_value"] + + output_probe = getattr(io_core, name) + value = yield output_probe + + if value != initial_value: + raise ValueError( + f"Output probe {name} initialized to {value} instead of {initial_value}" + ) + + else: + print(f"Output probe {name} initialized to {value} as expected.") + + simulate(io_core, testbench) + + +def test_input_probe_buffer_initial_value(): + def testbench(): + # Verify all input probe buffers initialize to zero + for name, width in config["inputs"].items(): + addrs = io_core.mmap[name + "_buf"]["addrs"] + + for addr in addrs: + yield from verify_register(io_core, addr, 0) + + simulate(io_core, testbench) + + +def test_output_probe_buffer_initial_value(): + def testbench(): + # Verify all output probe buffers initialize to the values in the config + for name, attrs in config["outputs"].items(): + addrs = io_core.mmap[name + "_buf"]["addrs"] + + datas = [0] * len(addrs) + if isinstance(attrs, dict): + if "initial_value" in attrs: + datas = value_to_words(attrs["initial_value"], len(addrs)) + + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) + + simulate(io_core, testbench) + + +def test_output_probes_are_writeable(): + def testbench(): + for name, attrs in config["outputs"].items(): + if isinstance(attrs, dict): + width = attrs["width"] + else: + width = attrs + + addrs = io_core.mmap[name + "_buf"]["addrs"] + test_value = randint(0, (2**width) - 1) + datas = value_to_words(test_value, len(addrs)) + + # write value to registers + for addr, data in zip(addrs, datas): + yield from write_register(io_core, addr, data) + + # read value back from registers + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) + + simulate(io_core, testbench) + + +def test_output_probes_update(): + def testbench(): + for name, attrs in config["outputs"].items(): + if isinstance(attrs, dict): + width = attrs["width"] + else: + width = attrs + + addrs = io_core.mmap[name + "_buf"]["addrs"] + test_value = randint(0, (2**width) - 1) + datas = value_to_words(test_value, len(addrs)) + + # write value to registers + for addr, data in zip(addrs, datas): + yield from write_register(io_core, addr, data) + + # pulse strobe register + yield from pulse_strobe_register() + + # check that outputs took updated value + output_probe = getattr(io_core, name) + value = yield (output_probe) + + if value != test_value: + raise ValueError( + f"Output probe {name} took value {value} instead of {test_value} after pulsing strobe." + ) + + else: + print(f"Output probe {name} took value {value} after pulsing strobe.") + + simulate(io_core, testbench) + + +def test_input_probes_update(): + def testbench(): + for name, width in config["inputs"].items(): + test_value = randint(0, (2**width) - 1) + + # set input probe value + input_probe = getattr(io_core, name) + yield input_probe.eq(test_value) + + # pulse strobe register + yield from pulse_strobe_register() + + # check that values are as expected once read back + addrs = io_core.mmap[name + "_buf"]["addrs"] + datas = value_to_words(test_value, len(addrs)) + + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) + + simulate(io_core, testbench) diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py new file mode 100644 index 0000000..1b6b063 --- /dev/null +++ b/test/test_logic_analyzer_hw.py @@ -0,0 +1,84 @@ +from amaranth import * +from amaranth_boards.nexys4ddr import Nexys4DDRPlatform +from amaranth_boards.icestick import ICEStickPlatform +from manta import Manta +from manta.utils import * +import pytest + + +class LogicAnalyzerCounterTest(Elaboratable): + def __init__(self, platform, port): + self.platform = platform + self.port = port + + self.config = self.platform_specific_config() + self.m = Manta(self.config) + + def platform_specific_config(self): + return { + "cores": { + "la": { + "type": "logic_analyzer", + "sample_depth": 1024, + "trigger_loc": 500, + "probes": {"larry": 1, "curly": 3, "moe": 9}, + "triggers": ["moe RISING"], + }, + }, + "uart": { + "port": self.port, + "baudrate": 3e6, + "clock_freq": self.platform.default_clk_frequency, + }, + } + + def elaborate(self, platform): + m = Module() + m.submodules["manta"] = self.m + uart_pins = platform.request("uart") + + larry = self.m.la.probe_signals["larry"]["top_level"] + curly = self.m.la.probe_signals["curly"]["top_level"] + moe = self.m.la.probe_signals["moe"]["top_level"] + + m.d.sync += larry.eq(larry + 1) + m.d.sync += curly.eq(curly + 1) + m.d.sync += moe.eq(moe + 1) + + m.d.comb += [ + self.m.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.m.interface.tx), + ] + + return m + + def build_and_program(self): + self.platform.build(self, do_program=True) + + def verify(self): + self.build_and_program() + cap = self.m.la.capture() + + # check that VCD export works + cap.export_vcd("out.vcd") + + # check that Verilog export works + cap.export_playback_verilog("out.v") + + # verify that each signal is just a counter modulo the width of the signal + for name, width in self.m.la.config["probes"].items(): + trace = cap.get_trace(name) + + for i in range(len(trace) - 1): + if trace[i + 1] != (trace[i] + 1) % (2**width): + raise ValueError("Bad counter!") + + +@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") +def test_mem_core_xilinx(): + LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB2").verify() + + +@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") +def test_mem_core_ice40(): + LogicAnalyzerCounterTest(ICEStickPlatform(), "/dev/ttyUSB1").verify() diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py new file mode 100644 index 0000000..b35e682 --- /dev/null +++ b/test/test_logic_analyzer_sim.py @@ -0,0 +1,140 @@ +from amaranth.sim import Simulator +from manta.logic_analyzer_core import LogicAnalyzerCore +from manta.utils import * +from random import sample + +config = { + "type": "logic_analyzer", + "sample_depth": 1024, + "trigger_loc": 500, + "probes": {"larry": 1, "curly": 3, "moe": 9}, + "triggers": ["moe RISING"], +} + +# class SimulatedBusInterface(): +# def __init__(self, core): +# self.core = core + +# def write(self, addrs, datas): +# # Handle a single integer address and data +# if isinstance(addrs, int) and isinstance(datas, int): +# return self.write([addrs], [datas]) + +# # Make sure address and datas are all integers +# if not isinstance(addrs, list) or not isinstance(datas, list): +# raise ValueError( +# "Write addresses and data must be an integer or list of integers." +# ) + +# if not all(isinstance(a, int) for a in addrs): +# raise ValueError("Write addresses must be all be integers.") + +# if not all(isinstance(d, int) for d in datas): +# raise ValueError("Write data must all be integers.") + +# # I'm not sure if it's necessary to split outputs into chunks +# # I think the output buffer doesn't really drop stuff, just the input buffer + +# for addr, data in zip(addrs, datas): +# yield from write_register(self.core, addr, data) + +# def read(self, addrs): +# # Handle a single integer address +# if isinstance(addrs, int): +# return self.read([addrs])[0] + +# # Make sure all list elements are integers +# if not all(isinstance(a, int) for a in addrs): +# raise ValueError("Read address must be an integer or list of integers.") + +# datas = [] +# for addr in addrs: +# yield la.addr_i.eq(addr) +# yield la.data_i.eq(0) +# yield la.rw_i.eq(0) +# yield la.valid_i.eq(1) +# yield +# yield la.addr_i.eq(0) +# yield la.valid_i.eq(0) + +# # wait for output to be valid +# while not (yield la.valid_o): +# yield + +# datas.append( (yield la.data_o) ) + +# return datas + +la = LogicAnalyzerCore(config, base_addr=0, interface=None) +# interface = SimulatedBusInterface(la) +# la.registers.interface = interface # unironically the least cursed part of this +# la.sample_mem.interface = interface # unironically the least cursed part of this + + +def print_data_at_addr(addr): + # place read transaction on the bus + yield la.addr_i.eq(addr) + yield la.data_i.eq(0) + yield la.rw_i.eq(0) + yield la.valid_i.eq(1) + yield + yield la.addr_i.eq(0) + yield la.valid_i.eq(0) + + # wait for output to be valid + while not (yield la.valid_o): + yield + + print(f"addr: {hex(addr)} data: {hex((yield la.data_o))}") + + +def set_logic_analyzer_register(name, data): + addr = la.registers.mmap[f"{name}_buf"]["addrs"][0] + + yield from write_register(la, 0, 0) + yield from write_register(la, addr, data) + yield from write_register(la, 0, 1) + yield from write_register(la, 0, 0) + + +def test_do_you_fucking_work(): + def testbench(): + # # ok nice what happens if we try to run the core, which includes: + yield from set_logic_analyzer_register("request_stop", 1) + yield from set_logic_analyzer_register("request_stop", 0) + + # setting triggers + yield from set_logic_analyzer_register("curly_op", la.operations["EQ"]) + yield from set_logic_analyzer_register("curly_arg", 4) + + # setting trigger mode + yield from set_logic_analyzer_register( + "trigger_mode", 0 + ) # right now this is not actually respected...oops + + # setting trigger location + yield from set_logic_analyzer_register("trigger_loc", 500) + + # starting capture + yield from set_logic_analyzer_register("request_start", 1) + yield from set_logic_analyzer_register("request_start", 0) + + # wait a few hundred clock cycles, see what happens + for _ in range(700): + yield + + # provide the trigger condition + yield la.probe_signals["curly"]["top_level"].eq(4) + + for _ in range(700): + yield + + # dump sample memory contents + yield from write_register(la, 0, 0) + yield from write_register(la, 0, 1) + yield from write_register(la, 0, 0) + + for addr in range(la.get_max_addr()): + yield from print_data_at_addr(addr) + + simulate(la, testbench, "la_core.vcd") diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py new file mode 100644 index 0000000..cb3c1de --- /dev/null +++ b/test/test_mem_core_hw.py @@ -0,0 +1,114 @@ +from amaranth import * +from amaranth_boards.nexys4ddr import Nexys4DDRPlatform +from amaranth_boards.icestick import ICEStickPlatform +from manta import Manta +from manta.utils import * +import pytest +from random import randint, sample +from math import ceil, log2 + +""" +Fundamentally we want a function to generate a configuration (as a dictionary) +for a memory core given the width, depth, and platform. This could be a random +configuration, or a standard one. +""" + + +class MemoryCoreLoopbackTest(Elaboratable): + def __init__(self, platform, width, depth, port): + self.platform = platform + self.width = width + self.depth = depth + self.port = port + + self.config = self.platform_specific_config() + self.m = Manta(self.config) + + def platform_specific_config(self): + return { + "cores": { + "mem_core": { + "type": "memory_read_only", + "width": self.width, + "depth": self.depth, + }, + "io_core": { + "type": "io", + "outputs": { + "addr": ceil(log2(self.depth)), + "data": self.width, + "we": 1, + }, + }, + }, + "uart": { + "port": self.port, + "baudrate": 3e6, + "clock_freq": self.platform.default_clk_frequency, + }, + } + + def elaborate(self, platform): + m = Module() + m.submodules["manta"] = self.m + + uart_pins = platform.request("uart") + + m.d.comb += [ + self.m.mem_core.user_addr.eq(self.m.io_core.addr), + self.m.mem_core.user_data.eq(self.m.io_core.data), + self.m.mem_core.user_we.eq(self.m.io_core.we), + self.m.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.m.interface.tx), + ] + + return m + + def build_and_program(self): + self.platform.build(self, do_program=True) + + def write_user_side(self, addr, data): + self.m.io_core.set_probe("we", 0) + self.m.io_core.set_probe("addr", addr) + self.m.io_core.set_probe("data", data) + self.m.io_core.set_probe("we", 1) + self.m.io_core.set_probe("we", 0) + + def verify_register(self, addr, expected_data): + data = self.m.mem_core.read_from_user_addr(addr) + + if data != expected_data: + raise ValueError( + f"Memory read from {hex(addr)} returned {hex(data)} instead of {hex(expected_data)}." + ) + + def verify(self): + self.build_and_program() + + # Read and write randomly from the bus side + for addr in sample(range(self.depth), k=self.depth): + data = randint(0, 2**self.width - 1) + self.write_user_side(addr, data) + self.verify_register(addr, data) + + +@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") +def test_mem_core_xilinx(): + MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, "/dev/ttyUSB2").verify() + + +@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") +def test_mem_core_ice40(): + port = "/dev/ttyUSB1" + MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 2, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 2, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 14, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 14, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 16, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 16, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 33, 512, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), 33, 1024, port).verify() diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py new file mode 100644 index 0000000..675991f --- /dev/null +++ b/test/test_mem_core_sim.py @@ -0,0 +1,45 @@ +from manta.memory_core import ReadOnlyMemoryCore +from manta.utils import * +from random import randint, sample + + +def fill_mem_from_user_port(mem_core, depth): + for i in range(depth): + yield mem_core.user_addr.eq(i) + yield mem_core.user_data.eq(i) + yield mem_core.user_we.eq(1) + yield + + yield mem_core.user_we.eq(0) + yield + + +def verify_mem_core(width, depth, base_addr): + config = {"type": "memory", "width": width, "depth": depth} + mem_core = ReadOnlyMemoryCore(config, base_addr, interface=None) + + def testbench(): + yield from fill_mem_from_user_port(mem_core, depth) + + # Read from address sequentially + for i in range(depth): + yield from verify_register(mem_core, i + base_addr, i % (2**width)) + + # Read from addresses randomly + for i in sample(range(depth), k=depth): + yield from verify_register(mem_core, i + base_addr, i % (2**width)) + + simulate(mem_core, testbench) + + +def test_sweep_core_widths(): + for i in range(1, 64): + verify_mem_core(i, 128, 0) + + +def test_random_cores(): + for _ in range(5): + width = randint(0, 512) + depth = randint(0, 1024) + base_addr = randint(0, 2**16 - 1 - depth) + verify_mem_core(width, depth, base_addr) diff --git a/test/test_toolchains.py b/test/test_toolchains.py new file mode 100644 index 0000000..c21c26a --- /dev/null +++ b/test/test_toolchains.py @@ -0,0 +1,15 @@ +from amaranth_boards.test.blinky import * +from amaranth_boards.nexys4ddr import Nexys4DDRPlatform +from amaranth_boards.icestick import ICEStickPlatform +from manta.utils import * +import pytest + + +@pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") +def test_arty_a7_tools(): + Nexys4DDRPlatform().build(Blinky(), do_program=False) + + +@pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") +def test_ice40_tools(): + ICEStickPlatform().build(Blinky(), do_program=False) diff --git a/test/test_uart_rx_sim.py b/test/test_uart_rx_sim.py new file mode 100644 index 0000000..3604591 --- /dev/null +++ b/test/test_uart_rx_sim.py @@ -0,0 +1,65 @@ +from amaranth.sim import Simulator +from manta.uart import UARTReceiver +from manta.utils import * +from random import sample + + +uart_rx = UARTReceiver(clocks_per_baud=10) + + +def verify_receive(data): + # 8N1 serial, LSB sent first + data_bits = "0" + f"{data:08b}"[::-1] + "1" + data_bits = [int(bit) for bit in data_bits] + + valid_asserted_before = False + + for i in range(10 * uart_rx.clocks_per_baud): + bit_index = i // uart_rx.clocks_per_baud + + # Every cycle, run checks on uart_rx: + if (yield uart_rx.valid_o): + if (yield uart_rx.data_o) != data: + a = yield uart_rx.data_o + print(data_bits) + raise ValueError( + f"Incorrect byte presented - gave {hex(a)} instead of {hex(data)}!" + ) + + if bit_index != 9: + print(bit_index) + raise ValueError("Byte presented before it is complete!") + + if not valid_asserted_before: + valid_asserted_before = True + + else: + raise ValueError("Valid asserted more than once!") + + yield uart_rx.rx.eq(data_bits[bit_index]) + yield + + if not valid_asserted_before: + raise ValueError("Failed to assert valid!") + + +def test_all_possible_bytes(): + def testbench(): + yield uart_rx.rx.eq(1) + yield + + for i in range(0xFF): + yield from verify_receive(i) + + simulate(uart_rx, testbench) + + +def test_bytes_random_sample(): + def testbench(): + yield uart_rx.rx.eq(1) + yield + + for i in sample(range(0xFF), k=0xFF): + yield from verify_receive(i) + + simulate(uart_rx, testbench) diff --git a/test/test_uart_tx_sim.py b/test/test_uart_tx_sim.py new file mode 100644 index 0000000..c78d076 --- /dev/null +++ b/test/test_uart_tx_sim.py @@ -0,0 +1,57 @@ +from amaranth.sim import Simulator +from manta.uart import UARTTransmitter +from manta.utils import * +from random import sample + + +uart_tx = UARTTransmitter(clocks_per_baud=10) + + +def verify_bit_sequence(byte): + """ + Request a byte to be transmitted, and verify that the sequence of bits is correct. + """ + + # Request byte to be transmitted + yield uart_tx.data_i.eq(byte) + yield uart_tx.start_i.eq(1) + yield + yield uart_tx.data_i.eq(0) + yield uart_tx.start_i.eq(0) + yield + + # Check that data bit is correct on every clock baud period + + # 8N1 serial, LSB sent first + data_bits = "0" + f"{byte:08b}"[::-1] + "1" + data_bits = [int(bit) for bit in data_bits] + + for i in range(10 * uart_tx.clocks_per_baud): + bit_index = i // uart_tx.clocks_per_baud + + if (yield uart_tx.tx) != data_bits[bit_index]: + raise ValueError("Wrong bit in sequence!") + + if (yield uart_tx.done_o) and (bit_index != 9): + raise ValueError("Done asserted too early!") + + yield + + if not (yield uart_tx.done_o): + raise ValueError("Done not asserted at end of transmission!") + + +def test_all_possible_bytes(): + def testbench(): + for i in range(0xFF): + yield from verify_bit_sequence(i) + + simulate(uart_tx, testbench) + + +def test_bytes_random_sample(): + def testbench(): + for i in sample(range(0xFF), k=0xFF): + yield from verify_bit_sequence(i) + + simulate(uart_tx, testbench) diff --git a/test/test_verilog_gen.py b/test/test_verilog_gen.py new file mode 100644 index 0000000..65bed93 --- /dev/null +++ b/test/test_verilog_gen.py @@ -0,0 +1,14 @@ +from manta.cli import gen +from manta import Manta +import tempfile +import os + + +def test_verilog_gen(): + with tempfile.TemporaryDirectory() as tmp_dir: + print("Created temporary directory at", tmp_dir) + + gen("test/test_verilog_gen.yaml", tmp_dir + "/manta.v") + + if not os.path.isfile(tmp_dir + "/manta.v"): + raise ValueError("No Verilog file generated!") diff --git a/test/functional_sim/io_core_tb/manta.yaml b/test/test_verilog_gen.yaml similarity index 53% rename from test/functional_sim/io_core_tb/manta.yaml rename to test/test_verilog_gen.yaml index 975a96b..09feddc 100644 --- a/test/functional_sim/io_core_tb/manta.yaml +++ b/test/test_verilog_gen.yaml @@ -2,7 +2,6 @@ cores: io_core: type: io - user_clock: True inputs: probe0: 1 @@ -14,11 +13,15 @@ cores: probe4: width: 1 initial_value: 1 - probe5: 2 + probe5: + width: 2 + initial_value: 2 probe6: 8 - probe7: 20 + probe7: + width: 20 + initial_value: 65538 uart: - port: "auto" - baudrate: 3000000 - clock_freq: 100000000 + port: "/dev/ttyUSB1" + baudrate: 115200 + clock_freq: 12000000 From 0eddf129319d224b8fb2fc9ed3d68633a9c2972a Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 14:27:59 -0800 Subject: [PATCH 02/89] banish .DS_Store --- .DS_Store | Bin 6148 -> 0 bytes .gitignore | 6 ++++++ src/manta/cli.py | 4 +++- 3 files changed, 9 insertions(+), 1 deletion(-) delete mode 100644 .DS_Store diff --git a/.DS_Store b/.DS_Store deleted file mode 100644 index 81229e8d26382bd3469cb3d9bb2de3f1954844ac..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6148 zcmeH~Jqp4=5QS&dB4Cr!avKle4VIuM@B*S@B?yZB9^E%TjnP_yyn&f-XEsBUS7b9H zqQmpN5$Q#wgBxXSVPuMYE)TiO>2iLYjtb*@FJ*K=2U&T%hcRwa*e@u>x3=Er<$CqZN!+^)bZi z-VT<$t|nVB+C_8t(7dzS6a&*}7cEF&S{)2jfC`Khm`C2*`M-mIoBu~GOsN1B_%j7` zvE6S6yi}g8AFpTiLso6w;GkcQ@b(jc#E#+>+ztE17GO=bASy8a2)GOkRN$uyya2`( B5q1Co diff --git a/.gitignore b/.gitignore index 8fb17e5..e85d6af 100644 --- a/.gitignore +++ b/.gitignore @@ -1,9 +1,15 @@ +# Hidden files +.DS_Store +*.vscode/ + +# Python files venv/ manta.egg-info/ .pytest_cache __pycache__/ build/ +# Miscellaneous file types *.v *.sv *.vcd diff --git a/src/manta/cli.py b/src/manta/cli.py index d84eba5..4703523 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -2,7 +2,8 @@ from .manta import Manta from warnings import warn from sys import argv from pkg_resources import get_distribution -version = "v" + get_distribution('manta').version + +version = "v" + get_distribution("manta").version logo = f""" \033[96m (\.-./) @@ -26,6 +27,7 @@ Supported commands: help, ray display this splash screen (hehe...splash screen) """ + def help(): print(logo) From 11ad9fb56a0eedeb456fef003f8fd84b48f4effa Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 14:33:45 -0800 Subject: [PATCH 03/89] move badges to same line --- README.md | 1 - ethernet_test.yml | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 ethernet_test.yml diff --git a/README.md b/README.md index e49515c..495439f 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,6 @@ ## Manta: An In-Situ Debugging Tool for Programmable Hardware ![run_tests](https://github.com/fischermoseley/manta/actions/workflows/run_tests.yml/badge.svg) ![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg) - [![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0) [![Code style: black](https://img.shields.io/badge/code%20style-black-000000.svg)](https://github.com/psf/black) diff --git a/ethernet_test.yml b/ethernet_test.yml new file mode 100644 index 0000000..9ca6abf --- /dev/null +++ b/ethernet_test.yml @@ -0,0 +1,19 @@ +--- +cores: + io_core: + type: io + + inputs: + dhcp_done: 1 + dhcp_ip_address: 32 + dhcp_timeout: 1 + + outputs: + dhcp_start: 1 + ip_address: 32 + + +uart: + port: "/dev/ttyUSB1" + baudrate: 115200 + clock_freq: 12000000 From 34f6a5433037072c1718c8ba7196246215990c91 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 15:30:55 -0800 Subject: [PATCH 04/89] fix integer bounds, move to self-hosted runner --- .github/workflows/run_tests.yml | 12 +++++++----- src/manta/io_core.py | 22 ++++++++++++++++++++++ src/manta/utils.py | 2 +- 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index 331fb58..4964dbb 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -2,12 +2,14 @@ name: run_tests on: [push] jobs: all: - runs-on: ubuntu-latest + runs-on: self-hosted steps: - uses: actions/checkout@v3 - name: Install Manta from Source run: | + ls -lah + pwd python -m pip install -U pip # omitting the following commmand causes the version of setuptools @@ -19,13 +21,13 @@ jobs: python -m pip install ".[dev]" + - name: Run tests + run: | # export tool paths export VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado export YOSYS=/tools/oss-cad-suite/bin/yosys - export NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr_ice40 + export NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr-ice40 export ICEPACK=/tools/oss-cad-suite/bin/icepack export ICEPROG=/tools/oss-cad-suite/bin/iceprog - - - name: Run tests - run: make test \ No newline at end of file + make test \ No newline at end of file diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 97d869f..c12096a 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -237,6 +237,28 @@ class IOCore(Elaboratable): return self.max_addr def set_probe(self, probe_name, value): + # check that probe is an output probe + if probe_name not in self.config["outputs"]: + raise ValueError(f"Output probe '{probe_name}' not found.") + + # check that value is an integer + if not isinstance(value, int): + raise ValueError("Value must be an integer.") + + # get the width of the probe, make sure value isn't too large for the probe + attrs = self.config["outputs"][probe_name] + if isinstance(attrs, int): + width = attrs + + if isinstance(attrs, dict): + width = attrs["width"] + + if value > 0 and value > 2**width - 1: + raise ValueError("Unsigned integer too large.") + + if value < 0 and value < -(2 ** (width - 1)): + raise ValueError("Signed integer too large.") + # set value in buffer addrs = self.mmap[probe_name + "_buf"]["addrs"] datas = value_to_words(value, len(addrs)) diff --git a/src/manta/utils.py b/src/manta/utils.py index a40fa0a..068501d 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -13,7 +13,7 @@ def words_to_value(data): if d > 0 and d > 2**16 - 1: raise ValueError("Unsigned integer too large.") - if d < 0 and d < -(2**15 - 1): + if d < 0 and d < -(2**15): raise ValueError("Signed integer too large.") return int("".join([f"{i:016b}" for i in data[::-1]]), 2) From ac3bbf46b207861eb9b18d86db1737dff6c46466 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 15:33:31 -0800 Subject: [PATCH 05/89] testing self-hosted runner --- .github/workflows/run_tests.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index 4964dbb..8e864e6 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -10,7 +10,8 @@ jobs: run: | ls -lah pwd - python -m pip install -U pip + pip freeze + python3 -m pip install -U pip # omitting the following commmand causes the version of setuptools # used by python to get confused, and it doesn't detect the name From 17d2b8b1dad74dfe17ee8d4aa156f51bb052362a Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 15:41:01 -0800 Subject: [PATCH 06/89] make self-hosted runner install into a venv --- .github/workflows/run_tests.yml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index 8e864e6..c8929e5 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -8,9 +8,11 @@ jobs: - name: Install Manta from Source run: | - ls -lah - pwd - pip freeze + # Make venv + python3 -m venv venv/ + source venv/bin/activate + + # Update pip python3 -m pip install -U pip # omitting the following commmand causes the version of setuptools @@ -20,6 +22,7 @@ jobs: # https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377 export DEB_PYTHON_INSTALL_LAYOUT=deb_system + # Install Manta, with optional dev-only dependencies python -m pip install ".[dev]" - name: Run tests From 9867e369cb27452103e3662fef525a7973f8724d Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 17:57:21 -0800 Subject: [PATCH 07/89] update playback module, needs pipelining --- .github/workflows/run_tests.yml | 2 +- src/manta/cli.py | 27 +++++------------- src/manta/logic_analyzer_core.py | 48 ++++++++++++++++++++++---------- 3 files changed, 42 insertions(+), 35 deletions(-) diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index c8929e5..d87e932 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -23,7 +23,7 @@ jobs: export DEB_PYTHON_INSTALL_LAYOUT=deb_system # Install Manta, with optional dev-only dependencies - python -m pip install ".[dev]" + python3 -m pip install ".[dev]" - name: Run tests run: | diff --git a/src/manta/cli.py b/src/manta/cli.py index 4703523..4595f51 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -6,34 +6,21 @@ from pkg_resources import get_distribution version = "v" + get_distribution("manta").version logo = f""" -\033[96m (\.-./) -\033[96m / \\ -\033[96m .' : '. -\033[96m _.-'` ' `'-._ \033[34;49;1m | \033[34;49;1m Manta {version} \033[00m -\033[96m .-' : '-. \033[34;49;1m | \033[34;49;3m An In-Situ Debugging Tool for Programmable Hardware \033[00m -\033[96m ,'_.._ . _.._', \033[34;49;1m | \033[34;49m https://github.com/fischermoseley/manta \033[00m -\033[96m '` `'-. ' .-'` -\033[96m '. : .' \033[34;49;1m | \033[34;49;3m Originally created by Fischer Moseley \033[00m -\033[96m \_. ._/ -\033[96m \ |^| -\033[96m | | ; -\033[96m \\'.___.' / -\033[96m '-....-' \033[00m +Manta {version} -Supported commands: - gen [config_file] [verilog_file] generate a verilog file specifying the Manta module from a given configuration file, and save to the provided path - capture [config_file] [la_core_name] [vcd_file] [verilog_file] start a capture on the specified core, and save the results to a .vcd or .v file at the provided path(s) - ports list all available serial ports - help, ray display this splash screen (hehe...splash screen) +Usage: + gen [config_file] [verilog_file] Generate a verilog file specifying the Manta module from a given configuration file, and save to the provided path + capture [config_file] [la_core_name] [vcd_file] [verilog_file] Start a capture on the specified core, and save the results to a .vcd or .v file at the provided path(s) + ports List all available serial ports + help Display this help menu """ - def help(): print(logo) def wrong_args(): - raise ValueError('Wrong number of arguments, run "manta help" for usage.') + print('Wrong number of arguments, run "manta help" for usage.') def gen(config_path, output_path): diff --git a/src/manta/logic_analyzer_core.py b/src/manta/logic_analyzer_core.py index 4acedd5..cc59fc2 100644 --- a/src/manta/logic_analyzer_core.py +++ b/src/manta/logic_analyzer_core.py @@ -488,15 +488,15 @@ class LogicAnalyzerCapture: return LogicAnalyzerPlayback(self.data, self.config) def export_playback_verilog(self, path): - la = LogicAnalyzerPlayback(self.data, self.config) + lap = LogicAnalyzerPlayback(self.data, self.config) from amaranth.back import verilog with open(path, "w") as f: f.write( verilog.convert( - la, + lap, name="logic_analyzer_playback", - ports=la.get_top_level_ports(), + ports=lap.get_top_level_ports(), strip_internal_attrs=True, ) ) @@ -508,8 +508,13 @@ class LogicAnalyzerPlayback(Elaboratable): self.config = config # State Machine - self.enable = Signal(1) + self.start = Signal(1) self.done = Signal(1) + self.states = { + "IDLE" : 0, + "RUN" : 1, + "DONE" : 2 + } # Top-Level Probe signals self.top_level_probes = {} @@ -530,6 +535,31 @@ class LogicAnalyzerPlayback(Elaboratable): m.submodules["mem"] = self.mem m.d.comb += self.read_port.en.eq(1) + state = Signal(range(len(self.states))) + addr = self.read_port.addr + + # Run state machine + with m.If(state == self.states["IDLE"]): + with m.If(self.start): + m.d.sync += state.eq(self.states["RUN"]) + m.d.sync += addr.eq(0) + + with m.Elif(state == self.states["RUN"]): + with m.If(addr < self.config["sample_depth"]): + m.d.sync += addr.eq(addr + 1) + + with m.Else(): + m.d.sync += state.eq(self.states["DONE"]) + m.d.sync += self.done.eq(1) + + + with m.Else(state == self.states["DONE"]): + with m.If(self.start): + m.d.sync += self.done.eq(0) + m.d.sync += state.eq(self.states["RUN"]) + m.d.sync += addr.eq(0) + + # Assign the probe values by part-selecting from the data port lower = 0 for name, width in reversed(self.config["probes"].items()): @@ -544,15 +574,5 @@ class LogicAnalyzerPlayback(Elaboratable): lower += width - # Iterate through the samples if saved - with m.If((self.enable) & (~self.done)): - with m.If(self.read_port.addr < (self.config["sample_depth"] - 1)): - m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1) - - with m.Else(): - m.d.sync += self.done.eq(1) - - return m - def get_top_level_ports(self): return [self.enable, self.done] + list(self.top_level_probes.values()) From 90a5dba665cc7fa04e6c682ffd740d7c243af5b4 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 19:20:06 -0800 Subject: [PATCH 08/89] finish playback module pipelining --- pyproject.toml | 1 - src/manta/logic_analyzer_core.py | 42 ++++++++++---------------------- 2 files changed, 13 insertions(+), 30 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index 8e9b9e9..575c948 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -11,7 +11,6 @@ dependencies = [ "PyYAML", "pyserial", "pyvcd", - "scapy" ] requires-python = ">=3.7" diff --git a/src/manta/logic_analyzer_core.py b/src/manta/logic_analyzer_core.py index cc59fc2..b3915ee 100644 --- a/src/manta/logic_analyzer_core.py +++ b/src/manta/logic_analyzer_core.py @@ -509,12 +509,7 @@ class LogicAnalyzerPlayback(Elaboratable): # State Machine self.start = Signal(1) - self.done = Signal(1) - self.states = { - "IDLE" : 0, - "RUN" : 1, - "DONE" : 2 - } + self.idle = Signal(1, reset=1) # Top-Level Probe signals self.top_level_probes = {} @@ -528,37 +523,24 @@ class LogicAnalyzerPlayback(Elaboratable): init=self.data, ) - self.read_port = self.mem.read_port() + self.read_port = self.mem.read_port(domain="comb") def elaborate(self, platform): m = Module() m.submodules["mem"] = self.mem - m.d.comb += self.read_port.en.eq(1) - - state = Signal(range(len(self.states))) - addr = self.read_port.addr # Run state machine - with m.If(state == self.states["IDLE"]): + with m.If(self.idle): with m.If(self.start): - m.d.sync += state.eq(self.states["RUN"]) - m.d.sync += addr.eq(0) + m.d.sync += self.idle.eq(0) - with m.Elif(state == self.states["RUN"]): - with m.If(addr < self.config["sample_depth"]): - m.d.sync += addr.eq(addr + 1) + with m.Else(): + with m.If(self.read_port.addr == self.config["sample_depth"] - 1): + m.d.sync += self.idle.eq(1) + m.d.sync += self.read_port.addr.eq(0) with m.Else(): - m.d.sync += state.eq(self.states["DONE"]) - m.d.sync += self.done.eq(1) - - - with m.Else(state == self.states["DONE"]): - with m.If(self.start): - m.d.sync += self.done.eq(0) - m.d.sync += state.eq(self.states["RUN"]) - m.d.sync += addr.eq(0) - + m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1) # Assign the probe values by part-selecting from the data port lower = 0 @@ -566,7 +548,7 @@ class LogicAnalyzerPlayback(Elaboratable): signal = self.top_level_probes[name] # Set output probe to zero if we're not - with m.If(~self.done): + with m.If(~self.idle): m.d.comb += signal.eq(self.read_port.data[lower : lower + width]) with m.Else(): @@ -574,5 +556,7 @@ class LogicAnalyzerPlayback(Elaboratable): lower += width + return m + def get_top_level_ports(self): - return [self.enable, self.done] + list(self.top_level_probes.values()) + return [self.start, self.idle] + list(self.top_level_probes.values()) From d31aa2650e9b71e8d724f5e5d88d484cfb43d729 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 28 Dec 2023 21:46:44 -0800 Subject: [PATCH 09/89] switch playback to synchronous read ports, make things synthesizable --- src/manta/logic_analyzer_core.py | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/src/manta/logic_analyzer_core.py b/src/manta/logic_analyzer_core.py index b3915ee..5368c49 100644 --- a/src/manta/logic_analyzer_core.py +++ b/src/manta/logic_analyzer_core.py @@ -509,7 +509,7 @@ class LogicAnalyzerPlayback(Elaboratable): # State Machine self.start = Signal(1) - self.idle = Signal(1, reset=1) + self.valid = Signal(1) # Top-Level Probe signals self.top_level_probes = {} @@ -523,32 +523,39 @@ class LogicAnalyzerPlayback(Elaboratable): init=self.data, ) - self.read_port = self.mem.read_port(domain="comb") + self.read_port = self.mem.read_port() def elaborate(self, platform): m = Module() m.submodules["mem"] = self.mem - # Run state machine - with m.If(self.idle): + m.d.comb += self.read_port.en.eq(1) + + # State Machine + busy = Signal(1) + with m.If(~busy): with m.If(self.start): - m.d.sync += self.idle.eq(0) + m.d.sync += busy.eq(1) + # m.d.sync += self.read_port.addr.eq(1) with m.Else(): with m.If(self.read_port.addr == self.config["sample_depth"] - 1): - m.d.sync += self.idle.eq(1) + m.d.sync += busy.eq(0) m.d.sync += self.read_port.addr.eq(0) with m.Else(): m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1) + # Pipeline to accomodate for the 2-cycle latency in the RAM + m.d.sync += self.valid.eq(busy) + # Assign the probe values by part-selecting from the data port lower = 0 for name, width in reversed(self.config["probes"].items()): signal = self.top_level_probes[name] # Set output probe to zero if we're not - with m.If(~self.idle): + with m.If(self.valid): m.d.comb += signal.eq(self.read_port.data[lower : lower + width]) with m.Else(): @@ -559,4 +566,4 @@ class LogicAnalyzerPlayback(Elaboratable): return m def get_top_level_ports(self): - return [self.start, self.idle] + list(self.top_level_probes.values()) + return [self.start, self.valid] + list(self.top_level_probes.values()) From 07ae9cc2e83f92fc86f677f2c821c5a1fe046172 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 31 Dec 2023 20:07:47 -0800 Subject: [PATCH 10/89] get playback module from class method --- src/manta/logic_analyzer_core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/manta/logic_analyzer_core.py b/src/manta/logic_analyzer_core.py index 5368c49..245b467 100644 --- a/src/manta/logic_analyzer_core.py +++ b/src/manta/logic_analyzer_core.py @@ -484,11 +484,11 @@ class LogicAnalyzerCapture: vcd_file.close() - def export_playback_module(self, path): + def export_playback_module(self): return LogicAnalyzerPlayback(self.data, self.config) def export_playback_verilog(self, path): - lap = LogicAnalyzerPlayback(self.data, self.config) + lap = self.export_playback_module() from amaranth.back import verilog with open(path, "w") as f: From ee18e10ae18833c2dfc09e9345b08d8a63307cf7 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 3 Jan 2024 13:35:09 -0700 Subject: [PATCH 11/89] add immediate capture mode to logic analyzer --- src/manta/logic_analyzer_core.py | 106 +++++++++++++++++++------------ test/test_logic_analyzer_sim.py | 62 +----------------- 2 files changed, 66 insertions(+), 102 deletions(-) diff --git a/src/manta/logic_analyzer_core.py b/src/manta/logic_analyzer_core.py index 245b467..8b40794 100644 --- a/src/manta/logic_analyzer_core.py +++ b/src/manta/logic_analyzer_core.py @@ -247,61 +247,83 @@ class LogicAnalyzerCore(Elaboratable): Cat(attrs["triggered"] for attrs in self.probe_signals.values()).any() ) + def increment_mod_sample_depth(self, m, signal): + # m.d.sync += signal.eq((signal + 1) % self.config["sample_depth"]) + + with m.If(signal == self.config["sample_depth"] - 1): + m.d.sync += signal.eq(0) + + with m.Else(): + m.d.sync += signal.eq(signal + 1) + def run_state_machine(self, m): - self.prev_request_start = Signal(1) - self.prev_request_stop = Signal(1) + prev_request_start = Signal(1) + prev_request_stop = Signal(1) + + request_start = self.registers.request_start + request_stop = self.registers.request_stop + trigger_mode = self.registers.trigger_mode + trigger_loc = self.registers.trigger_loc + state = self.registers.state + rp = self.registers.read_pointer + wp = self.registers.write_pointer + we = self.sample_mem.user_we + + m.d.comb += self.sample_mem.user_addr.eq(wp) # Rising edge detection for start/stop requests - m.d.sync += self.prev_request_start.eq(self.registers.request_start) - m.d.sync += self.prev_request_stop.eq(self.registers.request_stop) + m.d.sync += prev_request_start.eq(request_start) + m.d.sync += prev_request_stop.eq(request_stop) - m.d.comb += self.sample_mem.user_addr.eq(self.registers.write_pointer) + with m.If(state == self.states["IDLE"]): + m.d.sync += wp.eq(0) + m.d.sync += rp.eq(0) + m.d.sync += we.eq(0) - with m.If(self.registers.state == self.states["IDLE"]): - m.d.sync += self.registers.write_pointer.eq(0) - m.d.sync += self.registers.read_pointer.eq(0) - m.d.sync += self.sample_mem.user_we.eq(0) # or something like this - - with m.If((self.registers.request_start) & (~self.prev_request_start)): - m.d.sync += self.registers.state.eq(self.states["MOVE_TO_POSITION"]) - - with m.Elif(self.registers.state == self.states["MOVE_TO_POSITION"]): - m.d.sync += self.registers.write_pointer.eq( - self.registers.write_pointer + 1 - ) - m.d.sync += self.sample_mem.user_we.eq(1) - - with m.If(self.registers.write_pointer == self.registers.trigger_loc): - with m.If(self.trig): - m.d.sync += self.registers.state.eq(self.states["CAPTURING"]) + with m.If((request_start) & (~prev_request_start)): + m.d.sync += we.eq(1) + with m.If(trigger_mode == self.trigger_modes["IMMEDIATE"]): + m.d.sync += state.eq(self.states["CAPTURING"]) with m.Else(): - m.d.sync += self.registers.state.eq(self.states["IN_POSITION"]) + with m.If(trigger_loc == 0): + m.d.sync += state.eq(self.states["IN_POSITION"]) - with m.Elif(self.registers.state == self.states["IN_POSITION"]): - m.d.sync += self.registers.write_pointer.eq( - (self.registers.write_pointer + 1) % self.config["sample_depth"] - ) - m.d.sync += self.registers.read_pointer.eq( - (self.registers.read_pointer + 1) % self.config["sample_depth"] - ) - m.d.sync += self.sample_mem.user_we.eq(1) + with m.Else(): + m.d.sync += state.eq(self.states["MOVE_TO_POSITION"]) + + m.d.sync += state.eq(self.states["MOVE_TO_POSITION"]) + + with m.Elif(state == self.states["MOVE_TO_POSITION"]): + m.d.sync += wp.eq(wp + 1) + + with m.If(wp == trigger_loc): + with m.If(self.trig): + m.d.sync += state.eq(self.states["CAPTURING"]) + + with m.Else(): + m.d.sync += state.eq(self.states["IN_POSITION"]) + self.increment_mod_sample_depth(m, rp) + + with m.Elif(state == self.states["IN_POSITION"]): + self.increment_mod_sample_depth(m, wp) with m.If(self.trig): - m.d.sync += self.registers.state.eq(self.states["CAPTURING"]) - - with m.Elif(self.registers.state == self.states["CAPTURING"]): - with m.If(self.registers.write_pointer == self.registers.read_pointer): - m.d.sync += self.sample_mem.user_we.eq(0) - m.d.sync += self.registers.state.eq(self.states["CAPTURED"]) + m.d.sync += state.eq(self.states["CAPTURING"]) with m.Else(): - m.d.sync += self.registers.write_pointer.eq( - (self.registers.write_pointer + 1) % self.config["sample_depth"] - ) + self.increment_mod_sample_depth(m, rp) - with m.If((self.registers.request_stop) & (~self.prev_request_stop)): - m.d.sync += self.registers.state.eq(self.states["IDLE"]) + with m.Elif(state == self.states["CAPTURING"]): + with m.If(wp == rp): + m.d.sync += we.eq(0) + m.d.sync += state.eq(self.states["CAPTURED"]) + + with m.Else(): + self.increment_mod_sample_depth(m, wp) + + with m.If((request_stop) & (~prev_request_stop)): + m.d.sync += state.eq(self.states["IDLE"]) def elaborate(self, platform): m = Module() diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index b35e682..0f37aae 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -6,70 +6,12 @@ from random import sample config = { "type": "logic_analyzer", "sample_depth": 1024, - "trigger_loc": 500, + "trigger_loc": 512, "probes": {"larry": 1, "curly": 3, "moe": 9}, "triggers": ["moe RISING"], } -# class SimulatedBusInterface(): -# def __init__(self, core): -# self.core = core - -# def write(self, addrs, datas): -# # Handle a single integer address and data -# if isinstance(addrs, int) and isinstance(datas, int): -# return self.write([addrs], [datas]) - -# # Make sure address and datas are all integers -# if not isinstance(addrs, list) or not isinstance(datas, list): -# raise ValueError( -# "Write addresses and data must be an integer or list of integers." -# ) - -# if not all(isinstance(a, int) for a in addrs): -# raise ValueError("Write addresses must be all be integers.") - -# if not all(isinstance(d, int) for d in datas): -# raise ValueError("Write data must all be integers.") - -# # I'm not sure if it's necessary to split outputs into chunks -# # I think the output buffer doesn't really drop stuff, just the input buffer - -# for addr, data in zip(addrs, datas): -# yield from write_register(self.core, addr, data) - -# def read(self, addrs): -# # Handle a single integer address -# if isinstance(addrs, int): -# return self.read([addrs])[0] - -# # Make sure all list elements are integers -# if not all(isinstance(a, int) for a in addrs): -# raise ValueError("Read address must be an integer or list of integers.") - -# datas = [] -# for addr in addrs: -# yield la.addr_i.eq(addr) -# yield la.data_i.eq(0) -# yield la.rw_i.eq(0) -# yield la.valid_i.eq(1) -# yield -# yield la.addr_i.eq(0) -# yield la.valid_i.eq(0) - -# # wait for output to be valid -# while not (yield la.valid_o): -# yield - -# datas.append( (yield la.data_o) ) - -# return datas - la = LogicAnalyzerCore(config, base_addr=0, interface=None) -# interface = SimulatedBusInterface(la) -# la.registers.interface = interface # unironically the least cursed part of this -# la.sample_mem.interface = interface # unironically the least cursed part of this - def print_data_at_addr(addr): # place read transaction on the bus @@ -113,7 +55,7 @@ def test_do_you_fucking_work(): ) # right now this is not actually respected...oops # setting trigger location - yield from set_logic_analyzer_register("trigger_loc", 500) + yield from set_logic_analyzer_register("trigger_loc", 511) # starting capture yield from set_logic_analyzer_register("request_start", 1) From a11605b2b7b15b1f8c55fee10aa385cb62ad1a34 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 5 Jan 2024 16:50:25 -0800 Subject: [PATCH 12/89] refactor logic analyzer --- src/manta/cli.py | 1 + src/manta/logic_analyzer/__init__.py | 351 +++++++++++++ src/manta/logic_analyzer/fsm.py | 126 +++++ src/manta/logic_analyzer/playback.py | 68 +++ src/manta/logic_analyzer/sample_mem.py | 11 + src/manta/logic_analyzer/trigger_block.py | 126 +++++ src/manta/logic_analyzer_core.py | 591 ---------------------- src/manta/manta.py | 2 +- test/test_logic_analyzer_sim.py | 42 +- 9 files changed, 712 insertions(+), 606 deletions(-) create mode 100644 src/manta/logic_analyzer/__init__.py create mode 100644 src/manta/logic_analyzer/fsm.py create mode 100644 src/manta/logic_analyzer/playback.py create mode 100644 src/manta/logic_analyzer/sample_mem.py create mode 100644 src/manta/logic_analyzer/trigger_block.py delete mode 100644 src/manta/logic_analyzer_core.py diff --git a/src/manta/cli.py b/src/manta/cli.py index 4595f51..7528cf8 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -15,6 +15,7 @@ Usage: help Display this help menu """ + def help(): print(logo) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py new file mode 100644 index 0000000..68d858d --- /dev/null +++ b/src/manta/logic_analyzer/__init__.py @@ -0,0 +1,351 @@ +from amaranth import * +from warnings import warn +from ..utils import * +from .trigger_block import LogicAnalyzerTriggerBlock +from .fsm import LogicAnalyzerFSM +from .sample_mem import LogicAnalyzerSampleMemory +from .playback import LogicAnalyzerPlayback + + +class LogicAnalyzerCore(Elaboratable): + """ """ + + def __init__(self, config, base_addr, interface): + self.config = config + self.check_config(config) + + # Bus Input + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal(1) + self.valid_i = Signal(1) + + # Bus Output + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal(1) + self.valid_o = Signal(1) + + self.probes = [ + Signal(width, name=name) for name, width in self.config["probes"].items() + ] + + # Submodules + self.fsm = LogicAnalyzerFSM(self.config, base_addr, interface) + self.trig_blk = LogicAnalyzerTriggerBlock( + self.config, self.fsm.get_max_addr() + 1, interface + ) + self.sample_mem = LogicAnalyzerSampleMemory( + self.config, self.trig_blk.get_max_addr() + 1, interface + ) + + # Top-Level Probes: + for name, width in self.config["probes"].items(): + if hasattr(self, name): + raise ValueError( + f"Unable to assign probe name '{name}' as it clashes with a reserved name in the backend. Please rename the probe." + ) + + setattr(self, name, Signal(width, name=name)) + + def check_config(self, config): + # Check for unrecognized options + valid_options = [ + "type", + "sample_depth", + "probes", + "triggers", + "trigger_loc", + "trigger_mode", + ] + for option in config: + if option not in valid_options: + warn(f"Ignoring unrecognized option '{option}' in Logic Analyzer.") + + # Check sample depth is provided and positive + if "sample_depth" not in config: + raise ValueError("Logic Analyzer must have sample_depth specified.") + + if not isinstance(config["sample_depth"], int): + raise ValueError("Logic Analyzer sample_depth must be an integer.") + + if config["sample_depth"] <= 0: + raise ValueError("Logic Analyzer sample_depth must be positive.") + + # Check probes + if "probes" not in config: + raise ValueError("Logic Analyzer must have at least one probe specified.") + + if len(config["probes"]) == 0: + raise ValueError("Logic Analyzer must have at least one probe specified.") + + for name, width in config["probes"].items(): + if width < 0: + raise ValueError(f"Width of probe {name} must be positive.") + + # Check triggers + if "triggers" not in config: + raise ValueError("Logic Analyzer must have at least one trigger specified.") + + if len(config["triggers"]) == 0: + raise ValueError("Logic Analyzer must have at least one trigger specified.") + + # Check trigger location + if "trigger_loc" in config: + if not isinstance(config["trigger_loc"], int): + raise ValueError("Trigger location must be an integer.") + + if config["trigger_loc"] < 0: + raise ValueError("Trigger location must be positive.") + + if config["trigger_loc"] > config["sample_depth"]: + raise ValueError("Trigger location cannot exceed sample depth.") + + # Check trigger mode, if provided + if "trigger_mode" in config: + valid_modes = ["single_shot", "incremental", "immediate"] + if config["trigger_mode"] not in valid_modes: + raise ValueError( + f"Unrecognized trigger mode {config['trigger_mode']} provided." + ) + + if config["trigger_mode"] == "incremental": + if "trigger_loc" in config: + warn( + "Ignoring option 'trigger_loc', as 'trigger_mode' is set to immediate, and there is no trigger condition to wait for." + ) + + # Check triggers themselves + for trigger in config["triggers"]: + if not isinstance(trigger, str): + raise ValueError("Trigger must be specified with a string.") + + # Trigger conditions may be composed of either two or three components, + # depending on the operation specified. In the case of operations that + # don't need an argument (like DISABLE, RISING, FALLING, CHANGING) or + # three statements in + + # Check the trigger operations + components = trigger.strip().split(" ") + if len(components) == 2: + name, op = components + if op not in ["DISABLE", "RISING", "FALLING", "CHANGING"]: + raise ValueError( + f"Unable to interpret trigger condition '{trigger}'." + ) + + elif len(components) == 3: + name, op, arg = components + if op not in ["GT", "LT", "GEQ", "LEQ", "EQ", "NEQ"]: + raise ValueError( + f"Unable to interpret trigger condition '{trigger}'." + ) + + else: + raise ValueError(f"Unable to interpret trigger condition '{trigger}'.") + + # Check probe names + if components[0] not in config["probes"]: + raise ValueError(f"Unknown probe name '{components[0]}' specified.") + + def elaborate(self, platform): + m = Module() + + # Add submodules + m.submodules["fsm"] = fsm = self.fsm + m.submodules["sample_mem"] = sample_mem = self.sample_mem + m.submodules["trig_blk"] = trig_blk = self.trig_blk + + # Concat all the probes together, and feed to input of sample memory + # (it is necessary to reverse the order such that first probe occupies + # the lowest location in memory) + m.d.comb += sample_mem.user_data.eq(Cat(self.probes[::-1])) + + # Wire bus connections between internal modules + m.d.comb += [ + # Bus Connections + fsm.addr_i.eq(self.addr_i), + fsm.data_i.eq(self.data_i), + fsm.rw_i.eq(self.rw_i), + fsm.valid_i.eq(self.valid_i), + trig_blk.addr_i.eq(fsm.addr_o), + trig_blk.data_i.eq(fsm.data_o), + trig_blk.rw_i.eq(fsm.rw_o), + trig_blk.valid_i.eq(fsm.valid_o), + sample_mem.addr_i.eq(trig_blk.addr_o), + sample_mem.data_i.eq(trig_blk.data_o), + sample_mem.rw_i.eq(trig_blk.rw_o), + sample_mem.valid_i.eq(trig_blk.valid_o), + self.addr_o.eq(sample_mem.addr_o), + self.data_o.eq(sample_mem.data_o), + self.rw_o.eq(sample_mem.rw_o), + self.valid_o.eq(sample_mem.valid_o), + # Non-bus Connections + fsm.trigger.eq(trig_blk.trig), + sample_mem.user_we.eq(fsm.write_enable), + ] + + return m + + def get_top_level_ports(self): + return self.probes + + def get_max_addr(self): + return self.sample_mem.get_max_addr() + + def set_triggers(self): + # reset all triggers to zero + for p in self.probes: + self.trig_blk.r.set_probe(p.name + "_op", 0) + self.trig_blk.r.set_probe(p.name + "_arg", 0) + + # set triggers + for trigger in self.config["triggers"]: + components = trigger.strip().split(" ") + + # Handle triggers that don't need an argument + if len(components) == 2: + name, op = components + self.trig_blk.r.set_probe(name + "_op", self.operations[op]) + + # Handle triggers that do need an argument + elif len(components) == 3: + name, op, arg = components + self.registers.set_probe(name + "_op", self.operations[op]) + self.registers.set_probe(name + "_arg", int(arg)) + + def capture(self, verbose=False): + print_if_verbose = lambda x: print(x) if verbose else None + + # If core is not in IDLE state, request that it return to IDLE + print_if_verbose(" -> Resetting core...") + state = self.registers.get_probe("state") + if state != self.states["IDLE"]: + self.registers.set_probe("request_stop", 0) + self.registers.set_probe("request_stop", 1) + self.registers.set_probe("request_stop", 0) + + if self.registers.get_probe("state") != self.states["IDLE"]: + raise ValueError("Logic analyzer did not reset to IDLE state.") + + # Set triggers + print_if_verbose(" -> Setting triggers...") + self.set_triggers() + + # Set trigger mode, default to single-shot if user didn't specify a mode + print_if_verbose(" -> Setting trigger mode...") + if "trigger_mode" in self.config: + self.registers.set_probe("trigger_mode", self.config["trigger_mode"]) + + else: + self.registers.set_probe("trigger_mode", self.trigger_modes["SINGLE_SHOT"]) + + # Set trigger location + print_if_verbose(" -> Setting trigger location...") + self.registers.set_probe("trigger_loc", self.config["trigger_loc"]) + + # Send a start request to the state machine + print_if_verbose(" -> Starting capture...") + self.registers.set_probe("request_start", 1) + self.registers.set_probe("request_start", 0) + + # Poll the state machine's state, and wait for the capture to complete + print_if_verbose(" -> Waiting for capture to complete...") + while self.registers.get_probe("state") != self.states["CAPTURED"]: + pass + + # Read out the entirety of the sample memory + print_if_verbose(" -> Reading sample memory contents...") + addrs = list(range(self.config["sample_depth"])) + raw_capture = self.sample_mem.read_from_user_addr(addrs) + + # Revolve the memory around the read_pointer, such that all the beginning + # of the caputure is at the first element + print_if_verbose(" -> Checking read pointer and revolving memory...") + read_pointer = self.registers.get_probe("read_pointer") + + data = raw_capture[read_pointer:] + raw_capture[:read_pointer] + return LogicAnalyzerCapture(data, self.config) + + +class LogicAnalyzerCapture: + def __init__(self, data, config): + self.data = data + self.config = config + + def get_trigger_loc(self): + return self.config["trigger_loc"] + + def get_trace(self, probe_name): + # sum up the widths of all the probes below this one + lower = 0 + for name, width in self.config["probes"].items(): + if name == probe_name: + break + + lower += width + + # add the width of the probe we'd like + upper = lower + self.config["probes"][probe_name] + + total_probe_width = sum(self.config["probes"].values()) + binary = [f"{d:0{total_probe_width}b}" for d in self.data] + return [int(b[lower:upper], 2) for b in binary] + + def export_vcd(self, path): + from vcd import VCDWriter + from datetime import datetime + + # Use the same datetime format that iVerilog uses + timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y") + vcd_file = open(path, "w") + + with VCDWriter(vcd_file, "10 ns", timestamp, "manta") as writer: + # each probe has a name, width, and writer associated with it + signals = [] + for name, width in self.config["probes"].items(): + signal = { + "name": name, + "width": width, + "data": self.get_trace(name), + "var": writer.register_var("manta", name, "wire", size=width), + } + signals.append(signal) + + clock = writer.register_var("manta", "clk", "wire", size=1) + trigger = writer.register_var("manta", "trigger", "wire", size=1) + + # add the data to each probe in the vcd file + for timestamp in range(0, 2 * len(self.data)): + # run the clock + writer.change(clock, timestamp, timestamp % 2 == 0) + + # set the trigger + triggered = (timestamp // 2) >= self.get_trigger_loc() + writer.change(trigger, timestamp, triggered) + + # add other signals + for signal in signals: + var = signal["var"] + sample = signal["data"][timestamp // 2] + + writer.change(var, timestamp, sample) + + vcd_file.close() + + def export_playback_module(self): + return LogicAnalyzerPlayback(self.data, self.config) + + def export_playback_verilog(self, path): + lap = self.export_playback_module() + from amaranth.back import verilog + + with open(path, "w") as f: + f.write( + verilog.convert( + lap, + name="logic_analyzer_playback", + ports=lap.get_top_level_ports(), + strip_internal_attrs=True, + ) + ) diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py new file mode 100644 index 0000000..b2f0059 --- /dev/null +++ b/src/manta/logic_analyzer/fsm.py @@ -0,0 +1,126 @@ +from amaranth import * +from math import ceil, log2 +from ..io_core import IOCore + + +class LogicAnalyzerFSM(Elaboratable): + """ """ + + def __init__(self, config, base_addr, interface): + self.config = config + self.states = { + "IDLE": 0, + "MOVE_TO_POSITION": 1, + "IN_POSITION": 2, + "CAPTURING": 3, + "CAPTURED": 4, + } + + self.trigger_modes = {"SINGLE_SHOT": 0, "INCREMENTAL": 1, "IMMEDIATE": 2} + + self.trigger = Signal(1) + self.write_enable = Signal(1) + + register_config = { + "inputs": { + "state": 4, + "read_pointer": ceil(log2(self.config["sample_depth"])), + "write_pointer": ceil(log2(self.config["sample_depth"])), + }, + "outputs": { + "trigger_location": ceil(log2(self.config["sample_depth"])), + "trigger_mode": 2, + "request_start": 1, + "request_stop": 1, + }, + } + + self.r = IOCore(register_config, base_addr, interface) + + # Bus Input + self.addr_i = self.r.addr_i + self.data_i = self.r.data_i + self.rw_i = self.r.rw_i + self.valid_i = self.r.valid_i + + # Bus Output + self.addr_o = self.r.addr_o + self.data_o = self.r.data_o + self.rw_o = self.r.rw_o + self.valid_o = self.r.valid_o + + def get_max_addr(self): + return self.r.get_max_addr() + + def increment_mod_sample_depth(self, m, signal): + # m.d.sync += signal.eq((signal + 1) % self.config["sample_depth"]) + + with m.If(signal == self.config["sample_depth"] - 1): + m.d.sync += signal.eq(0) + + with m.Else(): + m.d.sync += signal.eq(signal + 1) + + def elaborate(self, platform): + m = Module() + + m.submodules["registers"] = self.r + + prev_request_start = Signal(1) + prev_request_stop = Signal(1) + + # Rising edge detection for start/stop requests + m.d.sync += prev_request_start.eq(self.r.request_start) + m.d.sync += prev_request_stop.eq(self.r.request_stop) + + with m.If(self.r.state == self.states["IDLE"]): + m.d.sync += self.r.write_pointer.eq(0) + m.d.sync += self.r.read_pointer.eq(0) + m.d.sync += self.write_enable.eq(0) + + with m.If((self.r.request_start) & (~prev_request_start)): + m.d.sync += self.write_enable.eq(1) + with m.If(self.r.trigger_mode == self.trigger_modes["IMMEDIATE"]): + m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + + with m.Else(): + with m.If(self.r.trigger_location == 0): + m.d.sync += self.r.state.eq(self.states["IN_POSITION"]) + + with m.Else(): + m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) + + m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) + + with m.Elif(self.r.state == self.states["MOVE_TO_POSITION"]): + m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) + + with m.If(self.r.write_pointer == self.r.trigger_location): + with m.If(self.trigger): + m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + + with m.Else(): + m.d.sync += self.r.state.eq(self.states["IN_POSITION"]) + self.increment_mod_sample_depth(m, self.r.read_pointer) + + with m.Elif(self.r.state == self.states["IN_POSITION"]): + self.increment_mod_sample_depth(m, self.r.write_pointer) + + with m.If(self.trigger): + m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + + with m.Else(): + self.increment_mod_sample_depth(m, self.r.read_pointer) + + with m.Elif(self.r.state == self.states["CAPTURING"]): + with m.If(self.r.write_pointer == self.r.read_pointer): + m.d.sync += self.write_enable.eq(0) + m.d.sync += self.r.state.eq(self.states["CAPTURED"]) + + with m.Else(): + self.increment_mod_sample_depth(m, self.r.write_pointer) + + with m.If((self.r.request_stop) & (~prev_request_stop)): + m.d.sync += self.r.state.eq(self.states["IDLE"]) + + return m diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py new file mode 100644 index 0000000..d5eea8e --- /dev/null +++ b/src/manta/logic_analyzer/playback.py @@ -0,0 +1,68 @@ +from amaranth import * + + +class LogicAnalyzerPlayback(Elaboratable): + def __init__(self, data, config): + self.data = data + self.config = config + + # State Machine + self.start = Signal(1) + self.valid = Signal(1) + + # Top-Level Probe signals + self.top_level_probes = {} + for name, width in self.config["probes"].items(): + self.top_level_probes[name] = Signal(width, name=name) + + # Instantiate memory + self.mem = Memory( + depth=self.config["sample_depth"], + width=sum(self.config["probes"].values()), + init=self.data, + ) + + self.read_port = self.mem.read_port() + + def elaborate(self, platform): + m = Module() + m.submodules["mem"] = self.mem + + m.d.comb += self.read_port.en.eq(1) + + # State Machine + busy = Signal(1) + with m.If(~busy): + with m.If(self.start): + m.d.sync += busy.eq(1) + # m.d.sync += self.read_port.addr.eq(1) + + with m.Else(): + with m.If(self.read_port.addr == self.config["sample_depth"] - 1): + m.d.sync += busy.eq(0) + m.d.sync += self.read_port.addr.eq(0) + + with m.Else(): + m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1) + + # Pipeline to accomodate for the 2-cycle latency in the RAM + m.d.sync += self.valid.eq(busy) + + # Assign the probe values by part-selecting from the data port + lower = 0 + for name, width in reversed(self.config["probes"].items()): + signal = self.top_level_probes[name] + + # Set output probe to zero if we're not + with m.If(self.valid): + m.d.comb += signal.eq(self.read_port.data[lower : lower + width]) + + with m.Else(): + m.d.comb += signal.eq(0) + + lower += width + + return m + + def get_top_level_ports(self): + return [self.start, self.valid] + list(self.top_level_probes.values()) diff --git a/src/manta/logic_analyzer/sample_mem.py b/src/manta/logic_analyzer/sample_mem.py new file mode 100644 index 0000000..b6806fd --- /dev/null +++ b/src/manta/logic_analyzer/sample_mem.py @@ -0,0 +1,11 @@ +from amaranth import * +from ..memory_core import ReadOnlyMemoryCore + + +class LogicAnalyzerSampleMemory(ReadOnlyMemoryCore): + def __init__(self, config, base_addr, interface): + width = sum(config["probes"].values()) + depth = config["sample_depth"] + mem_config = {"width": width, "depth": depth} + + super().__init__(mem_config, base_addr, interface) diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py new file mode 100644 index 0000000..0958109 --- /dev/null +++ b/src/manta/logic_analyzer/trigger_block.py @@ -0,0 +1,126 @@ +from amaranth import * +from ..io_core import IOCore + + +class LogicAnalyzerTriggerBlock(Elaboratable): + """ """ + + def __init__(self, config, base_addr, interface): + self.config = config + + # Instantiate a bunch of trigger blocks + self.probes = [ + Signal(width, name=name) for name, width in self.config["probes"].items() + ] + self.triggers = [LogicAnalyzerTrigger(p) for p in self.probes] + + # Make IO core for everything + outputs = {} + for p in self.probes: + outputs[p.name + "_arg"] = p.width + outputs[p.name + "_op"] = 4 + + self.r = IOCore({"outputs": outputs}, base_addr, interface) + + # Bus Input + self.addr_i = self.r.addr_i + self.data_i = self.r.data_i + self.rw_i = self.r.rw_i + self.valid_i = self.r.valid_i + + # Bus Output + self.addr_o = self.r.addr_o + self.data_o = self.r.data_o + self.rw_o = self.r.rw_o + self.valid_o = self.r.valid_o + + # Global trigger. High if any probe is triggered. + self.trig = Signal(1) + + def get_max_addr(self): + return self.r.get_max_addr() + + def elaborate(self, platform): + m = Module() + + # Add IO Core as submodule + m.submodules["registers"] = self.r + + # Add triggers as submodules + for t in self.triggers: + m.submodules[t.signal.name + "_trigger"] = t + + for probe, trigger in zip(self.probes, self.triggers): + # Connect trigger input signals to top-level signals + m.d.comb += trigger.signal.eq(probe) + + # Connect IO core registers to triggers + m.d.comb += trigger.arg.eq(getattr(self.r, probe.name + "_arg")) + m.d.comb += trigger.op.eq(getattr(self.r, probe.name + "_op")) + + m.d.comb += self.trig.eq(Cat([t.triggered for t in self.triggers]).any()) + + return m + + +class LogicAnalyzerTrigger(Elaboratable): + def __init__(self, signal): + self.operations = { + "DISABLE": 0, + "RISING": 1, + "FALLING": 2, + "CHANGING": 3, + "GT": 4, + "LT": 5, + "GEQ": 6, + "LEQ": 7, + "EQ": 8, + "NEQ": 9, + } + + self.signal = signal + self.op = Signal(range(len(self.operations))) + self.arg = Signal().like(signal) + self.triggered = Signal(1) + + def elaborate(self, platform): + m = Module() + + # Save previous value to register for edge detection + prev = Signal().like(self.signal) + m.d.sync += prev.eq(self.signal) + + with m.If(self.op == self.operations["DISABLE"]): + m.d.comb += self.triggered.eq(0) + + with m.Elif(self.op == self.operations["RISING"]): + m.d.comb += self.triggered.eq((self.signal) & (~prev)) + + with m.Elif(self.op == self.operations["FALLING"]): + m.d.comb += self.triggered.eq((~self.signal) & (prev)) + + with m.Elif(self.op == self.operations["CHANGING"]): + m.d.comb += self.triggered.eq(self.signal != prev) + + with m.Elif(self.op == self.operations["GT"]): + m.d.comb += self.triggered.eq(self.signal > self.arg) + + with m.Elif(self.op == self.operations["LT"]): + m.d.comb += self.triggered.eq(self.signal < self.arg) + + with m.Elif(self.op == self.operations["GEQ"]): + m.d.comb += self.triggered.eq(self.signal >= self.arg) + + with m.Elif(self.op == self.operations["LEQ"]): + m.d.comb += self.triggered.eq(self.signal <= self.arg) + + with m.Elif(self.op == self.operations["EQ"]): + m.d.comb += self.triggered.eq(self.signal == self.arg) + + with m.Elif(self.op == self.operations["NEQ"]): + m.d.comb += self.triggered.eq(self.signal != self.arg) + + with m.Else(): + m.d.comb += self.triggered.eq(0) + + return m diff --git a/src/manta/logic_analyzer_core.py b/src/manta/logic_analyzer_core.py deleted file mode 100644 index 8b40794..0000000 --- a/src/manta/logic_analyzer_core.py +++ /dev/null @@ -1,591 +0,0 @@ -from amaranth import * -from warnings import warn -from .utils import * -from .io_core import IOCore -from .memory_core import ReadOnlyMemoryCore -from math import ceil, log2 - - -class LogicAnalyzerCore(Elaboratable): - """ """ - - def __init__(self, config, base_addr, interface): - self.config = config - self.base_addr = base_addr - self.interface = interface - - self.check_config(config) - - # State Machine Values - self.states = { - "IDLE": 0, - "MOVE_TO_POSITION": 1, - "IN_POSITION": 2, - "CAPTURING": 3, - "CAPTURED": 4, - } - - # Trigger Modes - self.trigger_modes = {"SINGLE_SHOT": 0, "INCREMENTAL": 1, "IMMEDIATE": 2} - - # Trigger operations - self.operations = { - "DISABLE": 0, - "RISING": 1, - "FALLING": 2, - "CHANGING": 3, - "GT": 4, - "LT": 5, - "GEQ": 6, - "LEQ": 7, - "EQ": 8, - "NEQ": 9, - } - - self.registers = self.make_registers(self.base_addr) - self.sample_mem = self.make_sample_mem(self.registers.max_addr) - self.define_signals() - - def check_config(self, config): - # Check for unrecognized options - valid_options = [ - "type", - "sample_depth", - "probes", - "triggers", - "trigger_loc", - "trigger_mode", - ] - for option in config: - if option not in valid_options: - warn(f"Ignoring unrecognized option '{option}' in Logic Analyzer.") - - # Check sample depth is provided and positive - if "sample_depth" not in config: - raise ValueError("Logic Analyzer must have sample_depth specified.") - - if not isinstance(config["sample_depth"], int): - raise ValueError("Logic Analyzer sample_depth must be an integer.") - - if config["sample_depth"] <= 0: - raise ValueError("Logic Analyzer sample_depth must be positive.") - - # Check probes - if "probes" not in config: - raise ValueError("Logic Analyzer must have at least one probe specified.") - - if len(config["probes"]) == 0: - raise ValueError("Logic Analyzer must have at least one probe specified.") - - for name, width in config["probes"].items(): - if width < 0: - raise ValueError(f"Width of probe {name} must be positive.") - - # Check triggers - if "triggers" not in config: - raise ValueError("Logic Analyzer must have at least one trigger specified.") - - if len(config["triggers"]) == 0: - raise ValueError("Logic Analyzer must have at least one trigger specified.") - - # Check trigger location - if "trigger_loc" in config: - if not isinstance(config["trigger_loc"], int): - raise ValueError("Trigger location must be an integer.") - - if config["trigger_loc"] < 0: - raise ValueError("Trigger location must be positive.") - - if config["trigger_loc"] > config["sample_depth"]: - raise ValueError("Trigger location cannot exceed sample depth.") - - # Check trigger mode - if "trigger_mode" in config: - valid_modes = ["single_shot", "incremental", "immediate"] - if config["trigger_mode"] not in valid_modes: - raise ValueError( - f"Unrecognized trigger mode {config['trigger_mode']} provided." - ) - - # Check triggers themselves - for trigger in config["triggers"]: - if not isinstance(trigger, str): - raise ValueError("Trigger must be specified with a string.") - - # Trigger conditions may be composed of either two or three components, - # depending on the operation specified. In the case of operations that - # don't need an argument (like DISABLE, RISING, FALLING, CHANGING) or - # three statements in - - # Check the trigger operations - components = trigger.strip().split(" ") - if len(components) == 2: - name, op = components - if op not in ["DISABLE", "RISING", "FALLING", "CHANGING"]: - raise ValueError( - f"Unable to interpret trigger condition '{trigger}'." - ) - - elif len(components) == 3: - name, op, arg = components - if op not in ["GT", "LT", "GEQ", "LEQ", "EQ", "NEQ"]: - raise ValueError( - f"Unable to interpret trigger condition '{trigger}'." - ) - - else: - raise ValueError(f"Unable to interpret trigger condition '{trigger}'.") - - # Check probe names - if components[0] not in config["probes"]: - raise ValueError(f"Unknown probe name '{components[0]}' specified.") - - def define_signals(self): - # Bus Input - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal(1) - self.valid_i = Signal(1) - - # Bus Output - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal(1) - self.valid_o = Signal(1) - - # Probes - self.probe_signals = {} - for name, width in self.config["probes"].items(): - self.probe_signals[name] = { - "top_level": Signal(width), - "prev": Signal(width), - "trigger_arg": getattr(self.registers, f"{name}_arg"), - "trigger_op": getattr(self.registers, f"{name}_op"), - "triggered": Signal(1), - } - - # Global trigger. High if any probe is triggered. - self.trig = Signal(1) - - def make_registers(self, base_addr): - # The logic analyzer uses an IO core to handle inputs to the FSM and trigger comparators - register_config = { - "inputs": { - "state": 4, - "read_pointer": ceil(log2(self.config["sample_depth"])), - "write_pointer": ceil(log2(self.config["sample_depth"])), - }, - "outputs": { - "trigger_loc": ceil(log2(self.config["sample_depth"])), - "trigger_mode": 2, - "request_start": 1, - "request_stop": 1, - }, - } - - for name, width in self.config["probes"].items(): - register_config["outputs"][name + "_arg"] = width - register_config["outputs"][name + "_op"] = 4 - - return IOCore(register_config, base_addr, self.interface) - - def make_sample_mem(self, base_addr): - sample_mem_config = { - "width": sum(self.config["probes"].values()), - "depth": self.config["sample_depth"], - } - - return ReadOnlyMemoryCore(sample_mem_config, base_addr, self.interface) - - def run_triggers(self, m): - # Run the trigger for each individual probe - for name, attrs in self.probe_signals.items(): - top_level = attrs["top_level"] - prev = attrs["prev"] - trigger_arg = attrs["trigger_arg"] - trigger_op = attrs["trigger_op"] - triggered = attrs["triggered"] - - # Save the previous value to a register so we can do rising/falling edge detection later! - m.d.sync += prev.eq(top_level) - - with m.If(trigger_op == self.operations["DISABLE"]): - m.d.comb += triggered.eq(0) - - with m.Elif(trigger_op == self.operations["RISING"]): - m.d.comb += triggered.eq((top_level) & (~prev)) - - with m.Elif(trigger_op == self.operations["FALLING"]): - m.d.comb += triggered.eq((~top_level) & (prev)) - - with m.Elif(trigger_op == self.operations["CHANGING"]): - m.d.comb += triggered.eq(top_level != prev) - - with m.Elif(trigger_op == self.operations["GT"]): - m.d.comb += triggered.eq(top_level > trigger_arg) - - with m.Elif(trigger_op == self.operations["LT"]): - m.d.comb += triggered.eq(top_level < trigger_arg) - - with m.Elif(trigger_op == self.operations["GEQ"]): - m.d.comb += triggered.eq(top_level >= trigger_arg) - - with m.Elif(trigger_op == self.operations["LEQ"]): - m.d.comb += triggered.eq(top_level <= trigger_arg) - - with m.Elif(trigger_op == self.operations["EQ"]): - m.d.comb += triggered.eq(top_level == trigger_arg) - - with m.Elif(trigger_op == self.operations["NEQ"]): - m.d.comb += triggered.eq(top_level != trigger_arg) - - with m.Else(): - m.d.comb += triggered.eq(0) - - # Combine all the triggers - m.d.comb += self.trig.eq( - Cat(attrs["triggered"] for attrs in self.probe_signals.values()).any() - ) - - def increment_mod_sample_depth(self, m, signal): - # m.d.sync += signal.eq((signal + 1) % self.config["sample_depth"]) - - with m.If(signal == self.config["sample_depth"] - 1): - m.d.sync += signal.eq(0) - - with m.Else(): - m.d.sync += signal.eq(signal + 1) - - def run_state_machine(self, m): - prev_request_start = Signal(1) - prev_request_stop = Signal(1) - - request_start = self.registers.request_start - request_stop = self.registers.request_stop - trigger_mode = self.registers.trigger_mode - trigger_loc = self.registers.trigger_loc - state = self.registers.state - rp = self.registers.read_pointer - wp = self.registers.write_pointer - we = self.sample_mem.user_we - - m.d.comb += self.sample_mem.user_addr.eq(wp) - - # Rising edge detection for start/stop requests - m.d.sync += prev_request_start.eq(request_start) - m.d.sync += prev_request_stop.eq(request_stop) - - with m.If(state == self.states["IDLE"]): - m.d.sync += wp.eq(0) - m.d.sync += rp.eq(0) - m.d.sync += we.eq(0) - - with m.If((request_start) & (~prev_request_start)): - m.d.sync += we.eq(1) - with m.If(trigger_mode == self.trigger_modes["IMMEDIATE"]): - m.d.sync += state.eq(self.states["CAPTURING"]) - - with m.Else(): - with m.If(trigger_loc == 0): - m.d.sync += state.eq(self.states["IN_POSITION"]) - - with m.Else(): - m.d.sync += state.eq(self.states["MOVE_TO_POSITION"]) - - m.d.sync += state.eq(self.states["MOVE_TO_POSITION"]) - - with m.Elif(state == self.states["MOVE_TO_POSITION"]): - m.d.sync += wp.eq(wp + 1) - - with m.If(wp == trigger_loc): - with m.If(self.trig): - m.d.sync += state.eq(self.states["CAPTURING"]) - - with m.Else(): - m.d.sync += state.eq(self.states["IN_POSITION"]) - self.increment_mod_sample_depth(m, rp) - - with m.Elif(state == self.states["IN_POSITION"]): - self.increment_mod_sample_depth(m, wp) - - with m.If(self.trig): - m.d.sync += state.eq(self.states["CAPTURING"]) - - with m.Else(): - self.increment_mod_sample_depth(m, rp) - - with m.Elif(state == self.states["CAPTURING"]): - with m.If(wp == rp): - m.d.sync += we.eq(0) - m.d.sync += state.eq(self.states["CAPTURED"]) - - with m.Else(): - self.increment_mod_sample_depth(m, wp) - - with m.If((request_stop) & (~prev_request_stop)): - m.d.sync += state.eq(self.states["IDLE"]) - - def elaborate(self, platform): - m = Module() - - # Add registers and sample memory as submodules - m.submodules["registers"] = self.registers - m.submodules["sample_mem"] = self.sample_mem - - # Concat all the probes together, and feed to input of sample memory - # (it is necessary to reverse the order such that first probe occupies - # the lowest location in memory) - m.d.comb += self.sample_mem.user_data.eq( - Cat([p["top_level"] for p in self.probe_signals.values()][::-1]) - ) - - self.run_state_machine(m) - self.run_triggers(m) - - # Wire internal modules - m.d.comb += [ - self.registers.addr_i.eq(self.addr_i), - self.registers.data_i.eq(self.data_i), - self.registers.rw_i.eq(self.rw_i), - self.registers.valid_i.eq(self.valid_i), - self.sample_mem.addr_i.eq(self.registers.addr_o), - self.sample_mem.data_i.eq(self.registers.data_o), - self.sample_mem.rw_i.eq(self.registers.rw_o), - self.sample_mem.valid_i.eq(self.registers.valid_o), - self.addr_o.eq(self.sample_mem.addr_o), - self.data_o.eq(self.sample_mem.data_o), - self.rw_o.eq(self.sample_mem.rw_o), - self.valid_o.eq(self.sample_mem.valid_o), - ] - - return m - - def get_top_level_ports(self): - return [p["top_level"] for p in self.probe_signals.values()] - - def get_max_addr(self): - return self.sample_mem.get_max_addr() - - def set_triggers(self): - # reset all triggers to zero - for name in self.probe_signals.keys(): - self.registers.set_probe(name + "_op", 0) - self.registers.set_probe(name + "_arg", 0) - - # set triggers - for trigger in self.config["triggers"]: - components = trigger.strip().split(" ") - - # Handle triggers that don't need an argument - if len(components) == 2: - name, op = components - self.registers.set_probe(name + "_op", self.operations[op]) - - # Handle triggers that do need an argument - elif len(components) == 3: - name, op, arg = components - self.registers.set_probe(name + "_op", self.operations[op]) - self.registers.set_probe(name + "_arg", int(arg)) - - def capture(self, verbose=False): - print_if_verbose = lambda x: print(x) if verbose else None - - # If core is not in IDLE state, request that it return to IDLE - print_if_verbose(" -> Resetting core...") - state = self.registers.get_probe("state") - if state != self.states["IDLE"]: - self.registers.set_probe("request_stop", 0) - self.registers.set_probe("request_stop", 1) - self.registers.set_probe("request_stop", 0) - - if self.registers.get_probe("state") != self.states["IDLE"]: - raise ValueError("Logic analyzer did not reset to IDLE state.") - - # Set triggers - print_if_verbose(" -> Setting triggers...") - self.set_triggers() - - # Set trigger mode, default to single-shot if user didn't specify a mode - print_if_verbose(" -> Setting trigger mode...") - if "trigger_mode" in self.config: - self.registers.set_probe("trigger_mode", self.config["trigger_mode"]) - - else: - self.registers.set_probe("trigger_mode", self.trigger_modes["SINGLE_SHOT"]) - - # Set trigger location - print_if_verbose(" -> Setting trigger location...") - self.registers.set_probe("trigger_loc", self.config["trigger_loc"]) - - # Send a start request to the state machine - print_if_verbose(" -> Starting capture...") - self.registers.set_probe("request_start", 1) - self.registers.set_probe("request_start", 0) - - # Poll the state machine's state, and wait for the capture to complete - print_if_verbose(" -> Waiting for capture to complete...") - while self.registers.get_probe("state") != self.states["CAPTURED"]: - pass - - # Read out the entirety of the sample memory - print_if_verbose(" -> Reading sample memory contents...") - addrs = list(range(self.config["sample_depth"])) - raw_capture = self.sample_mem.read_from_user_addr(addrs) - - # Revolve the memory around the read_pointer, such that all the beginning - # of the caputure is at the first element - print_if_verbose(" -> Checking read pointer and revolving memory...") - read_pointer = self.registers.get_probe("read_pointer") - - data = raw_capture[read_pointer:] + raw_capture[:read_pointer] - return LogicAnalyzerCapture(data, self.config) - - -class LogicAnalyzerCapture: - def __init__(self, data, config): - self.data = data - self.config = config - - def get_trigger_loc(self): - return self.config["trigger_loc"] - - def get_trace(self, probe_name): - # sum up the widths of all the probes below this one - lower = 0 - for name, width in self.config["probes"].items(): - if name == probe_name: - break - - lower += width - - # add the width of the probe we'd like - upper = lower + self.config["probes"][probe_name] - - total_probe_width = sum(self.config["probes"].values()) - binary = [f"{d:0{total_probe_width}b}" for d in self.data] - return [int(b[lower:upper], 2) for b in binary] - - def export_vcd(self, path): - from vcd import VCDWriter - from datetime import datetime - - # Use the same datetime format that iVerilog uses - timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y") - vcd_file = open(path, "w") - - with VCDWriter(vcd_file, "10 ns", timestamp, "manta") as writer: - # each probe has a name, width, and writer associated with it - signals = [] - for name, width in self.config["probes"].items(): - signal = { - "name": name, - "width": width, - "data": self.get_trace(name), - "var": writer.register_var("manta", name, "wire", size=width), - } - signals.append(signal) - - clock = writer.register_var("manta", "clk", "wire", size=1) - trigger = writer.register_var("manta", "trigger", "wire", size=1) - - # add the data to each probe in the vcd file - for timestamp in range(0, 2 * len(self.data)): - # run the clock - writer.change(clock, timestamp, timestamp % 2 == 0) - - # set the trigger - triggered = (timestamp // 2) >= self.get_trigger_loc() - writer.change(trigger, timestamp, triggered) - - # add other signals - for signal in signals: - var = signal["var"] - sample = signal["data"][timestamp // 2] - - writer.change(var, timestamp, sample) - - vcd_file.close() - - def export_playback_module(self): - return LogicAnalyzerPlayback(self.data, self.config) - - def export_playback_verilog(self, path): - lap = self.export_playback_module() - from amaranth.back import verilog - - with open(path, "w") as f: - f.write( - verilog.convert( - lap, - name="logic_analyzer_playback", - ports=lap.get_top_level_ports(), - strip_internal_attrs=True, - ) - ) - - -class LogicAnalyzerPlayback(Elaboratable): - def __init__(self, data, config): - self.data = data - self.config = config - - # State Machine - self.start = Signal(1) - self.valid = Signal(1) - - # Top-Level Probe signals - self.top_level_probes = {} - for name, width in self.config["probes"].items(): - self.top_level_probes[name] = Signal(width, name=name) - - # Instantiate memory - self.mem = Memory( - depth=self.config["sample_depth"], - width=sum(self.config["probes"].values()), - init=self.data, - ) - - self.read_port = self.mem.read_port() - - def elaborate(self, platform): - m = Module() - m.submodules["mem"] = self.mem - - m.d.comb += self.read_port.en.eq(1) - - # State Machine - busy = Signal(1) - with m.If(~busy): - with m.If(self.start): - m.d.sync += busy.eq(1) - # m.d.sync += self.read_port.addr.eq(1) - - with m.Else(): - with m.If(self.read_port.addr == self.config["sample_depth"] - 1): - m.d.sync += busy.eq(0) - m.d.sync += self.read_port.addr.eq(0) - - with m.Else(): - m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1) - - # Pipeline to accomodate for the 2-cycle latency in the RAM - m.d.sync += self.valid.eq(busy) - - # Assign the probe values by part-selecting from the data port - lower = 0 - for name, width in reversed(self.config["probes"].items()): - signal = self.top_level_probes[name] - - # Set output probe to zero if we're not - with m.If(self.valid): - m.d.comb += signal.eq(self.read_port.data[lower : lower + width]) - - with m.Else(): - m.d.comb += signal.eq(0) - - lower += width - - return m - - def get_top_level_ports(self): - return [self.start, self.valid] + list(self.top_level_probes.values()) diff --git a/src/manta/manta.py b/src/manta/manta.py index 073f55a..97f1b4c 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -5,7 +5,7 @@ from .uart import UARTInterface # from .ethernet import EthernetInterface from .io_core import IOCore from .memory_core import ReadOnlyMemoryCore -from .logic_analyzer_core import LogicAnalyzerCore +from .logic_analyzer import LogicAnalyzerCore class Manta(Elaboratable): diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index 0f37aae..01594dd 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -1,5 +1,5 @@ from amaranth.sim import Simulator -from manta.logic_analyzer_core import LogicAnalyzerCore +from manta.logic_analyzer import LogicAnalyzerCore from manta.utils import * from random import sample @@ -13,6 +13,7 @@ config = { la = LogicAnalyzerCore(config, base_addr=0, interface=None) + def print_data_at_addr(addr): # place read transaction on the bus yield la.addr_i.eq(addr) @@ -30,43 +31,56 @@ def print_data_at_addr(addr): print(f"addr: {hex(addr)} data: {hex((yield la.data_o))}") -def set_logic_analyzer_register(name, data): - addr = la.registers.mmap[f"{name}_buf"]["addrs"][0] +def set_fsm_register(name, data): + addr = la.fsm.r.mmap[f"{name}_buf"]["addrs"][0] yield from write_register(la, 0, 0) yield from write_register(la, addr, data) yield from write_register(la, 0, 1) yield from write_register(la, 0, 0) +def set_trig_blk_register(name, data): + addr = la.trig_blk.r.mmap[f"{name}_buf"]["addrs"][0] + + yield from write_register(la, 0, 0) + yield from write_register(la, addr, data) + yield from write_register(la, 0, 1) + yield from write_register(la, 0, 0) + +def set_probe(name, value): + probe = None + for p in la.probes: + if p.name == name: + probe = p + + yield p.eq(value) def test_do_you_fucking_work(): def testbench(): # # ok nice what happens if we try to run the core, which includes: - yield from set_logic_analyzer_register("request_stop", 1) - yield from set_logic_analyzer_register("request_stop", 0) + yield from set_fsm_register("request_stop", 1) + yield from set_fsm_register("request_stop", 0) # setting triggers - yield from set_logic_analyzer_register("curly_op", la.operations["EQ"]) - yield from set_logic_analyzer_register("curly_arg", 4) + yield from set_trig_blk_register("curly_op", la.trig_blk.triggers[0].operations["EQ"]) + yield from set_trig_blk_register("curly_arg", 4) # setting trigger mode - yield from set_logic_analyzer_register( - "trigger_mode", 0 - ) # right now this is not actually respected...oops + yield from set_fsm_register("trigger_mode", 0) # setting trigger location - yield from set_logic_analyzer_register("trigger_loc", 511) + yield from set_fsm_register("trigger_location", 511) # starting capture - yield from set_logic_analyzer_register("request_start", 1) - yield from set_logic_analyzer_register("request_start", 0) + yield from set_fsm_register("request_start", 1) + yield from set_fsm_register("request_start", 0) # wait a few hundred clock cycles, see what happens for _ in range(700): yield # provide the trigger condition - yield la.probe_signals["curly"]["top_level"].eq(4) + yield from set_probe("curly", 4) for _ in range(700): yield From 958ccadbd0a97df7fd5266794fb963986f48e0e0 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 5 Jan 2024 21:43:53 -0800 Subject: [PATCH 13/89] refactored logic analyzer working in sim --- src/manta/logic_analyzer/__init__.py | 3 ++- src/manta/logic_analyzer/trigger_block.py | 8 ++------ test/test_logic_analyzer_sim.py | 25 +++++++++++++++-------- 3 files changed, 20 insertions(+), 16 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 68d858d..90b610c 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -33,7 +33,7 @@ class LogicAnalyzerCore(Elaboratable): # Submodules self.fsm = LogicAnalyzerFSM(self.config, base_addr, interface) self.trig_blk = LogicAnalyzerTriggerBlock( - self.config, self.fsm.get_max_addr() + 1, interface + self.probes, self.fsm.get_max_addr() + 1, interface ) self.sample_mem = LogicAnalyzerSampleMemory( self.config, self.trig_blk.get_max_addr() + 1, interface @@ -182,6 +182,7 @@ class LogicAnalyzerCore(Elaboratable): self.valid_o.eq(sample_mem.valid_o), # Non-bus Connections fsm.trigger.eq(trig_blk.trig), + sample_mem.user_addr.eq(fsm.r.write_pointer), sample_mem.user_we.eq(fsm.write_enable), ] diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 0958109..b7a952b 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -5,13 +5,9 @@ from ..io_core import IOCore class LogicAnalyzerTriggerBlock(Elaboratable): """ """ - def __init__(self, config, base_addr, interface): - self.config = config - + def __init__(self, probes, base_addr, interface): # Instantiate a bunch of trigger blocks - self.probes = [ - Signal(width, name=name) for name, width in self.config["probes"].items() - ] + self.probes = probes self.triggers = [LogicAnalyzerTrigger(p) for p in self.probes] # Make IO core for everything diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index 01594dd..72622ed 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -33,19 +33,23 @@ def print_data_at_addr(addr): def set_fsm_register(name, data): addr = la.fsm.r.mmap[f"{name}_buf"]["addrs"][0] + strobe_addr = la.fsm.r.base_addr - yield from write_register(la, 0, 0) + yield from write_register(la, strobe_addr, 0) yield from write_register(la, addr, data) - yield from write_register(la, 0, 1) - yield from write_register(la, 0, 0) + yield from write_register(la, strobe_addr, 1) + yield from write_register(la, strobe_addr, 0) + def set_trig_blk_register(name, data): addr = la.trig_blk.r.mmap[f"{name}_buf"]["addrs"][0] + strobe_addr = la.trig_blk.r.base_addr - yield from write_register(la, 0, 0) + yield from write_register(la, strobe_addr, 0) yield from write_register(la, addr, data) - yield from write_register(la, 0, 1) - yield from write_register(la, 0, 0) + yield from write_register(la, strobe_addr, 1) + yield from write_register(la, strobe_addr, 0) + def set_probe(name, value): probe = None @@ -53,16 +57,19 @@ def set_probe(name, value): if p.name == name: probe = p - yield p.eq(value) + yield probe.eq(value) -def test_do_you_fucking_work(): + +def test_single_shot_capture(): def testbench(): # # ok nice what happens if we try to run the core, which includes: yield from set_fsm_register("request_stop", 1) yield from set_fsm_register("request_stop", 0) # setting triggers - yield from set_trig_blk_register("curly_op", la.trig_blk.triggers[0].operations["EQ"]) + yield from set_trig_blk_register( + "curly_op", la.trig_blk.triggers[0].operations["EQ"] + ) yield from set_trig_blk_register("curly_arg", 4) # setting trigger mode From 03a3ec6c9fd6b635998452543e7d2eed76f405a6 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 5 Jan 2024 22:11:49 -0800 Subject: [PATCH 14/89] update logic analyzer capture method --- src/manta/logic_analyzer/__init__.py | 69 +++++++++-------------- src/manta/logic_analyzer/trigger_block.py | 21 +++++++ 2 files changed, 47 insertions(+), 43 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 90b610c..c55b82b 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -55,7 +55,7 @@ class LogicAnalyzerCore(Elaboratable): "sample_depth", "probes", "triggers", - "trigger_loc", + "trigger_location", "trigger_mode", ] for option in config: @@ -91,14 +91,14 @@ class LogicAnalyzerCore(Elaboratable): raise ValueError("Logic Analyzer must have at least one trigger specified.") # Check trigger location - if "trigger_loc" in config: - if not isinstance(config["trigger_loc"], int): + if "trigger_location" in config: + if not isinstance(config["trigger_location"], int): raise ValueError("Trigger location must be an integer.") - if config["trigger_loc"] < 0: + if config["trigger_location"] < 0: raise ValueError("Trigger location must be positive.") - if config["trigger_loc"] > config["sample_depth"]: + if config["trigger_location"] > config["sample_depth"]: raise ValueError("Trigger location cannot exceed sample depth.") # Check trigger mode, if provided @@ -110,9 +110,9 @@ class LogicAnalyzerCore(Elaboratable): ) if config["trigger_mode"] == "incremental": - if "trigger_loc" in config: + if "trigger_location" in config: warn( - "Ignoring option 'trigger_loc', as 'trigger_mode' is set to immediate, and there is no trigger condition to wait for." + "Ignoring option 'trigger_location', as 'trigger_mode' is set to immediate, and there is no trigger condition to wait for." ) # Check triggers themselves @@ -194,65 +194,48 @@ class LogicAnalyzerCore(Elaboratable): def get_max_addr(self): return self.sample_mem.get_max_addr() - def set_triggers(self): - # reset all triggers to zero - for p in self.probes: - self.trig_blk.r.set_probe(p.name + "_op", 0) - self.trig_blk.r.set_probe(p.name + "_arg", 0) - - # set triggers - for trigger in self.config["triggers"]: - components = trigger.strip().split(" ") - - # Handle triggers that don't need an argument - if len(components) == 2: - name, op = components - self.trig_blk.r.set_probe(name + "_op", self.operations[op]) - - # Handle triggers that do need an argument - elif len(components) == 3: - name, op, arg = components - self.registers.set_probe(name + "_op", self.operations[op]) - self.registers.set_probe(name + "_arg", int(arg)) - def capture(self, verbose=False): print_if_verbose = lambda x: print(x) if verbose else None # If core is not in IDLE state, request that it return to IDLE print_if_verbose(" -> Resetting core...") - state = self.registers.get_probe("state") + state = self.fsm.r.get_probe("state") if state != self.states["IDLE"]: - self.registers.set_probe("request_stop", 0) - self.registers.set_probe("request_stop", 1) - self.registers.set_probe("request_stop", 0) + self.fsm.r.set_probe("request_stop", 0) + self.fsm.r.set_probe("request_stop", 1) + self.fsm.r.set_probe("request_stop", 0) - if self.registers.get_probe("state") != self.states["IDLE"]: + if self.fsm.r.get_probe("state") != self.fsm.states["IDLE"]: raise ValueError("Logic analyzer did not reset to IDLE state.") # Set triggers print_if_verbose(" -> Setting triggers...") - self.set_triggers() + self.trig_blk.set_triggers() # Set trigger mode, default to single-shot if user didn't specify a mode print_if_verbose(" -> Setting trigger mode...") if "trigger_mode" in self.config: - self.registers.set_probe("trigger_mode", self.config["trigger_mode"]) + self.fsm.r.set_probe("trigger_mode", self.config["trigger_mode"]) else: - self.registers.set_probe("trigger_mode", self.trigger_modes["SINGLE_SHOT"]) + self.fsm.r.set_probe("trigger_mode", self.fsm.trigger_modes["SINGLE_SHOT"]) # Set trigger location print_if_verbose(" -> Setting trigger location...") - self.registers.set_probe("trigger_loc", self.config["trigger_loc"]) + if "trigger_location" in self.config: + self.fsm.r.set_probe("trigger_location", self.config["trigger_location"]) + + else: + self.fsm.r.set_probe("trigger_location", self.config["sample_depth"] // 2) # Send a start request to the state machine print_if_verbose(" -> Starting capture...") - self.registers.set_probe("request_start", 1) - self.registers.set_probe("request_start", 0) + self.fsm.r.set_probe("request_start", 1) + self.fsm.r.set_probe("request_start", 0) # Poll the state machine's state, and wait for the capture to complete print_if_verbose(" -> Waiting for capture to complete...") - while self.registers.get_probe("state") != self.states["CAPTURED"]: + while self.fsm.r.get_probe("state") != self.fsm.states["CAPTURED"]: pass # Read out the entirety of the sample memory @@ -263,7 +246,7 @@ class LogicAnalyzerCore(Elaboratable): # Revolve the memory around the read_pointer, such that all the beginning # of the caputure is at the first element print_if_verbose(" -> Checking read pointer and revolving memory...") - read_pointer = self.registers.get_probe("read_pointer") + read_pointer = self.fsm.r.get_probe("read_pointer") data = raw_capture[read_pointer:] + raw_capture[:read_pointer] return LogicAnalyzerCapture(data, self.config) @@ -274,8 +257,8 @@ class LogicAnalyzerCapture: self.data = data self.config = config - def get_trigger_loc(self): - return self.config["trigger_loc"] + def get_trigger_location(self): + return self.config["trigger_location"] def get_trace(self, probe_name): # sum up the widths of all the probes below this one diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index b7a952b..9e446e0 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -36,6 +36,27 @@ class LogicAnalyzerTriggerBlock(Elaboratable): def get_max_addr(self): return self.r.get_max_addr() + def set_triggers(self, config): + # reset all triggers to zero + for p in self.probes: + self.r.set_probe(p.name + "_op", 0) + self.r.set_probe(p.name + "_arg", 0) + + # set triggers + for trigger in config["triggers"]: + components = trigger.strip().split(" ") + + # Handle triggers that don't need an argument + if len(components) == 2: + name, op = components + self.r.set_probe(name + "_op", self.triggers[0].operations[op]) + + # Handle triggers that do need an argument + elif len(components) == 3: + name, op, arg = components + self.r.set_probe(name + "_op", self.triggers[0].operations[op]) + self.r.set_probe(name + "_arg", int(arg)) + def elaborate(self, platform): m = Module() From 89f1dcde1c8f9e40a2729919884850e0abf1dae6 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 5 Jan 2024 23:01:57 -0800 Subject: [PATCH 15/89] convert diagrams to .drawio.svg format --- doc/assets/block_memory_architecture.png | Bin 668736 -> 0 bytes doc/assets/bus_architecture.drawio.svg | 445 +++++++ doc/assets/bus_architecture.png | Bin 359910 -> 0 bytes doc/assets/ethernet_packet.png | Bin 310473 -> 0 bytes doc/assets/io_core_architecture.drawio.svg | 337 +++++ doc/assets/io_core_architecture.png | Bin 239952 -> 0 bytes doc/assets/io_core_memory_map.drawio.svg | 251 ++++ .../logic_analyzer_architecture.drawio.svg | 748 +++++++++++ doc/assets/logic_analyzer_architecture.png | Bin 603208 -> 0 bytes doc/assets/manta.drawio.png | Bin 0 -> 52590 bytes doc/assets/manta_architecture.png | Bin 494609 -> 0 bytes doc/assets/memory_architecture.drawio.svg | 608 +++++++++ doc/assets/system_architecture.drawio.svg | 342 +++++ doc/assets/uart.png | Bin 447251 -> 0 bytes doc/assets/uart_packets.drawio.svg | 1148 +++++++++++++++++ doc/how_it_works.md | 6 +- doc/io_core.md | 2 +- doc/logic_analyzer_core.md | 2 +- doc/{block_memory_core.md => memory_core.md} | 2 +- mkdocs.yml | 2 +- 20 files changed, 3886 insertions(+), 7 deletions(-) delete mode 100644 doc/assets/block_memory_architecture.png create mode 100644 doc/assets/bus_architecture.drawio.svg delete mode 100644 doc/assets/bus_architecture.png delete mode 100644 doc/assets/ethernet_packet.png create mode 100644 doc/assets/io_core_architecture.drawio.svg delete mode 100644 doc/assets/io_core_architecture.png create mode 100644 doc/assets/io_core_memory_map.drawio.svg create mode 100644 doc/assets/logic_analyzer_architecture.drawio.svg delete mode 100644 doc/assets/logic_analyzer_architecture.png create mode 100644 doc/assets/manta.drawio.png delete mode 100644 doc/assets/manta_architecture.png create mode 100644 doc/assets/memory_architecture.drawio.svg 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+ bus +
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+
+ + + bus + + + + + + + + +
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+ bus +
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+ + + bus + + + + + + + +
+
+
+

+ manta +

+
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+ + + manta + + + + + + + +
+
+
+

+ FPGA Fabric +

+
+
+
+ + + FPGA Fabric + + + + + + + + +
+
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+ bus +
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+
+ + + bus + + + + + + + + +
+
+
+ bus +
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+ + + bus + + + + + + + + +
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+ rx +
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+
+ + + rx + + + + + + + + +
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+ input_0 +
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+
+ + + input_0 + + + + + + + + +
+
+
+ output_1 +
+
+
+ + + output_1 + + + + + + + +
+
+
+ rx bridge +
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+ + + rx bridge + + + + + + + +
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+
+ logic +
+ analyzer core +
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+
+ + + logic... + + + + + + + +
+
+
+ io core +
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+
+ + + io core + + + + + + + +
+
+
+ block memory core +
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+
+ + + block memo... + + + + + + + +
+
+
+ tx bridge +
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+
+ + + tx bridge + + + + + + + +
+
+
+ user logic +
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+ + + user logic + + + + + + + + +
+
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+ addr +
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+ din +
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+ probe_2 +
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+ probe_3 +
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+ probe_1 +
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Each core provides a unique method for interacting with the user’s logic, which it connects to by routing signals (called _probes_) between the user’s logic and the cores that interface with it. -![](assets/bus_architecture.png){:style="width:40%"} +![](assets/bus_architecture.drawio.svg){:style="width:40%"} These probes are presented as addressable memory, and are be controlled by reading and writing to their corresponing memory - not unlike registers on a microcontroller. Each core is allotted a section of address space at compile time, and operations addressed to a core’s address space control the behavior of the core. These cores are then daisy-chained along an internal bus, which permits a chain arbitrarily many cores to be placed on the bus. @@ -37,7 +37,7 @@ Each core has a bus input and output port, so that cores can be daisy-chained to Ethernet and UART both allow a stream of bytes to be sent between the host and FPGA, but since they're just interfaces, they don't define how these bytes are structured. As a result, Manta implements its own messaging format, with the following structure: -![](assets/uart.png){:style="width:85%"} +![](assets/uart_packets.drawio.svg){:style="width:85%"} Each of these messages is a string of ASCII characters consisting of a preamble, optional address and data fields, and an End of Line (EOL). The preamble denotes the type of operation, _R_ for a read and _W_ for a write. The address and data fields are encoded as hexadecimal digits, represented with the characters 0-9 and A-F in ASCII. As a result, four characters are needed to encode a 16-bit address or 16-bits of data. If the message specifies a write request, then it will contain a data field after the address field. Both request types will conclude with an End of Line, which consists of the two ASCII characters indicating a Carriage Return (CR) and a Line Feed (LF). diff --git a/doc/io_core.md b/doc/io_core.md index 16ff61e..ca777d1 100644 --- a/doc/io_core.md +++ b/doc/io_core.md @@ -90,7 +90,7 @@ While the IO core performs a very, very simple task, it carries a few caveats. This is done with the architecture shown below: -![](assets/io_core_architecture.png){:style="width:49%"} +![](assets/io_core_architecture.drawio.svg){:style="width:49%"} Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple. diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index edd9d50..8dcb3e8 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -139,7 +139,7 @@ At present, this class contains methods used really only for capturing data, and ## How It Works The Logic Analyzer Core's implementation on the FPGA consists of three primary components: -![](assets/logic_analyzer_architecture.png){style="width:85%"} +![](assets/logic_analyzer_architecture.drawio.svg){style="width:85%"} - The _Finite State Machine (FSM)_, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains. - The _Trigger Block_, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the $N$-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's `trig` input. diff --git a/doc/block_memory_core.md b/doc/memory_core.md similarity index 99% rename from doc/block_memory_core.md rename to doc/memory_core.md index 1d8c464..2aa4749 100644 --- a/doc/block_memory_core.md +++ b/doc/memory_core.md @@ -68,7 +68,7 @@ A Block Memory core is used in the [video_sprite](https://github.com/fischermose Each Block Memory core is actually a set of 16-bit wide BRAMs with their ports concatenated together, with any spare bits masked off. Here's a diagram: -![](assets/block_memory_architecture.png) +![](assets/memory_architecture.drawio.svg) This has one major consequence: if the core doesn't have a width that's an exact multiple of 16, synthesis engines (Vivado in particular) will throw some warnings as they optimize out the unused bits. This is expected behavior, and while the warnings are a little annoying, not having to manually deal with the unused bits simplifies the implementation immensely. No Python is needed to generate the core, and it'll configure itself just based on Verilog parameters. This turns the block memory core from a complicated conditionally-instantiated beast to a simple ~_100 line_ [Verilog file](https://github.com/fischermoseley/manta/blob/main/src/manta/block_memory.v). diff --git a/mkdocs.yml b/mkdocs.yml index bc6c8f8..f027bdc 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -61,7 +61,7 @@ nav: - Getting Started: getting_started.md - IO Core: io_core.md - Logic Analyzer Core: logic_analyzer_core.md - - Block Memory Core: block_memory_core.md + - Memory Core: memory_core.md - UART Interace: uart_interface.md - Ethernet Interface: ethernet_interface.md - For Developers: From e2daf94f3fa5ddc1c653d3b28fec005bd5b4fdeb Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 5 Jan 2024 23:43:47 -0800 Subject: [PATCH 16/89] remove unneeded diagram --- doc/assets/manta.drawio.png | Bin 52590 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 doc/assets/manta.drawio.png diff --git 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Mon Sep 17 00:00:00 2001 From: fischerm Date: Sun, 7 Jan 2024 12:09:38 -0800 Subject: [PATCH 17/89] fix bad comb assignment --- src/manta/logic_analyzer/__init__.py | 5 +++++ src/manta/logic_analyzer/trigger_block.py | 5 +---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index c55b82b..4b8f466 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -191,6 +191,11 @@ class LogicAnalyzerCore(Elaboratable): def get_top_level_ports(self): return self.probes + def get_probe(self, name): + for p in self.probes: + if p.name == name: + return p + def get_max_addr(self): return self.sample_mem.get_max_addr() diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 9e446e0..2b15530 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -67,11 +67,8 @@ class LogicAnalyzerTriggerBlock(Elaboratable): for t in self.triggers: m.submodules[t.signal.name + "_trigger"] = t + # Connect IO core registers to triggers for probe, trigger in zip(self.probes, self.triggers): - # Connect trigger input signals to top-level signals - m.d.comb += trigger.signal.eq(probe) - - # Connect IO core registers to triggers m.d.comb += trigger.arg.eq(getattr(self.r, probe.name + "_arg")) m.d.comb += trigger.op.eq(getattr(self.r, probe.name + "_op")) From 4c48035201421a4872c7bed9a77b59989db25f12 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 7 Jan 2024 12:49:20 -0800 Subject: [PATCH 18/89] track amaranth release, not main repo --- pyproject.toml | 2 +- src/manta/utils.py | 25 ++++++++++++++++++++----- test/test_logic_analyzer_hw.py | 10 +++++----- 3 files changed, 26 insertions(+), 11 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index 575c948..d8ceffc 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -7,7 +7,7 @@ authors = [ description = "An In-Situ Debugging Tool for Programmable Hardware" readme = "README.md" dependencies = [ - "amaranth[builtin-yosys]@git+https://github.com/amaranth-lang/amaranth", + "amaranth[builtin-yosys]", "PyYAML", "pyserial", "pyvcd", diff --git a/src/manta/utils.py b/src/manta/utils.py index 068501d..a680567 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -109,21 +109,36 @@ def write_register(module, addr, data): def xilinx_tools_installed(): """ - Return whether Vivado is installed, by checking if the VIVADO environment variable is set. + Return whether Vivado is installed, by checking if the VIVADO environment variable is set, + or if the binary exists on PATH. This variable should point to the binary itself, not just the folder it's located in (ie, /tools/Xilinx/Vivado/2023.1/bin/vivado, not /tools/Xilinx/Vivado/2023.1/bin) """ - return "VIVADO" in os.environ + from shutil import which + return ("VIVADO" in os.environ) or (which("vivado") is not None) def ice40_tools_installed(): """ Return whether the ice40 tools are installed, by checking if the YOSYS, NEXTPNR_ICE40, - ICEPACK, and ICEPROG environment variables are defined. + ICEPACK, and ICEPROG environment variables are defined, or if the binaries exist on PATH. # These variables should point to the binaries themselves, not just the folder it's located in # (ie, /tools/oss-cad-suite/bin/yosys, not /tools/oss-cad-suite/bin/) """ - tools = ["YOSYS", "NEXTPNR_ICE40", "ICEPACK", "ICEPROG"] - return all(tool in os.environ for tool in tools) + + # Check environment variables + env_vars = ["YOSYS", "NEXTPNR_ICE40", "ICEPACK", "ICEPROG"] + if all(var in os.environ for var in env_vars): + return True + + # Check PATH + binaries = ["yosys", "nextpnr-ice40", "icepack", "iceprog"] + from shutil import which + if all([which(b) for b in binaries]): + return True + + return False + + diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 1b6b063..49d064a 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -37,9 +37,9 @@ class LogicAnalyzerCounterTest(Elaboratable): m.submodules["manta"] = self.m uart_pins = platform.request("uart") - larry = self.m.la.probe_signals["larry"]["top_level"] - curly = self.m.la.probe_signals["curly"]["top_level"] - moe = self.m.la.probe_signals["moe"]["top_level"] + larry = self.m.la.probes[0] + curly = self.m.la.probes[1] + moe = self.m.la.probes[2] m.d.sync += larry.eq(larry + 1) m.d.sync += curly.eq(curly + 1) @@ -75,10 +75,10 @@ class LogicAnalyzerCounterTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") -def test_mem_core_xilinx(): +def test_logic_analyzer_core_xilinx(): LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB2").verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") -def test_mem_core_ice40(): +def test_logic_analyzer_core_ice40(): LogicAnalyzerCounterTest(ICEStickPlatform(), "/dev/ttyUSB1").verify() From 61d6479805eae099e7ee12ef50c6086f0cde4313 Mon Sep 17 00:00:00 2001 From: fischerm Date: Sun, 7 Jan 2024 15:13:35 -0800 Subject: [PATCH 19/89] add docstrings --- src/manta/logic_analyzer/__init__.py | 133 ++++++++++++++++++++++++--- src/manta/logic_analyzer/playback.py | 11 +++ src/manta/utils.py | 4 +- test/test_logic_analyzer_hw.py | 6 +- 4 files changed, 134 insertions(+), 20 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 4b8f466..fcb27d9 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -8,7 +8,29 @@ from .playback import LogicAnalyzerPlayback class LogicAnalyzerCore(Elaboratable): - """ """ + """A logic analzyer, implemented in the FPGA fabric. Connects to the rest of the cores + over Manta's internal bus, and may be operated from a user's machine through the Python API. + + Parameters: + ---------- + config : dict + Configuration options. This is taken from the section of Manta's configuration YAML that + describes the core. + + base_addr : int + Where to place the core in Manta's internal memory map. This determines the beginning of + the core's address space. The end of the core's address space may be obtained by calling + the get_max_addr() method. + + interface : UARTInterface or EthernetInterface + The interface used to communicate with the core. + + Attributes: + ---------- + None + + + """ def __init__(self, config, base_addr, interface): self.config = config @@ -39,15 +61,6 @@ class LogicAnalyzerCore(Elaboratable): self.config, self.trig_blk.get_max_addr() + 1, interface ) - # Top-Level Probes: - for name, width in self.config["probes"].items(): - if hasattr(self, name): - raise ValueError( - f"Unable to assign probe name '{name}' as it clashes with a reserved name in the backend. Please rename the probe." - ) - - setattr(self, name, Signal(width, name=name)) - def check_config(self, config): # Check for unrecognized options valid_options = [ @@ -196,16 +209,31 @@ class LogicAnalyzerCore(Elaboratable): if p.name == name: return p + raise ValueError(f"Probe '{name}' not found in Logic Analyzer core.") + def get_max_addr(self): return self.sample_mem.get_max_addr() def capture(self, verbose=False): + """Perform a capture, recording the state of all input probes to the FPGA's memory, and + then reading that out on the host. + + Parameters: + ---------- + verbose : bool + Whether or not to print the status of the capture to stdout as it progresses. + Defaults to False. + + Returns: + ---------- + An instance of LogicAnalyzerCapture. + """ print_if_verbose = lambda x: print(x) if verbose else None # If core is not in IDLE state, request that it return to IDLE print_if_verbose(" -> Resetting core...") state = self.fsm.r.get_probe("state") - if state != self.states["IDLE"]: + if state != self.fsm.states["IDLE"]: self.fsm.r.set_probe("request_stop", 0) self.fsm.r.set_probe("request_stop", 1) self.fsm.r.set_probe("request_stop", 0) @@ -215,7 +243,7 @@ class LogicAnalyzerCore(Elaboratable): # Set triggers print_if_verbose(" -> Setting triggers...") - self.trig_blk.set_triggers() + self.trig_blk.set_triggers(self.config) # Set trigger mode, default to single-shot if user didn't specify a mode print_if_verbose(" -> Setting trigger mode...") @@ -258,14 +286,52 @@ class LogicAnalyzerCore(Elaboratable): class LogicAnalyzerCapture: + """A container for the data collected during a capture from a LogicAnalyzerCore. Contains + methods for exporting the data as a VCD waveform file, or as a Verilog module for playing + back captured data in simulation/synthesis. + + Parameters: + ---------- + data : list[int] + The raw captured data taken by the LogicAnalyzerCore. This consists of the values of + all the input probes concatenated together at every timestep. + + config : dict + The configuration of the LogicAnalyzerCore that took this capture. + """ + def __init__(self, data, config): self.data = data self.config = config def get_trigger_location(self): + """Gets the location of the trigger in the capture. This will match the value of + "trigger_location" provided in the configuration file at the time of capture. + + Parameters: + ---------- + None + + Returns: + ---------- + The trigger location as an `int`. + """ return self.config["trigger_location"] def get_trace(self, probe_name): + """Gets the value of a single probe over the capture. + + Parameters: + ---------- + probe_name : int + The name of the probe in the LogicAnalyzer Core. This must match the name provided + in the configuration file. + + Returns: + ---------- + The value of the probe at every timestep in the capture, as a list of integers. + """ + # sum up the widths of all the probes below this one lower = 0 for name, width in self.config["probes"].items(): @@ -282,6 +348,19 @@ class LogicAnalyzerCapture: return [int(b[lower:upper], 2) for b in binary] def export_vcd(self, path): + """Export the capture to a VCD file, containing the data of all probes in the core. + + Parameters: + ---------- + path : str + The path of the output file, including the ".vcd" file extension. + + Returns: + ---------- + None + + """ + from vcd import VCDWriter from datetime import datetime @@ -310,7 +389,7 @@ class LogicAnalyzerCapture: writer.change(clock, timestamp, timestamp % 2 == 0) # set the trigger - triggered = (timestamp // 2) >= self.get_trigger_loc() + triggered = (timestamp // 2) >= self.get_trigger_location() writer.change(trigger, timestamp, triggered) # add other signals @@ -322,11 +401,35 @@ class LogicAnalyzerCapture: vcd_file.close() - def export_playback_module(self): + def get_playback_module(self): + """Gets an Amaranth module that will playback the captured data. This module is + synthesizable, so it may be used in either simulation or synthesis. + + Parameters: + ---------- + None + + Returns: + ---------- + An instance of LogicAnalyzerPlayback, which is a synthesizable Amaranth module. + """ return LogicAnalyzerPlayback(self.data, self.config) def export_playback_verilog(self, path): - lap = self.export_playback_module() + """Exports a Verilog module that will playback the captured data. This module is + synthesizable, so it may be used in either simulation or synthesis. + + Parameters: + ---------- + path : str + The path of the output file, including the ".v" file extension. + + Returns: + ---------- + None + """ + + lap = self.get_playback_module() from amaranth.back import verilog with open(path, "w") as f: diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index d5eea8e..cc392f3 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -2,6 +2,17 @@ from amaranth import * class LogicAnalyzerPlayback(Elaboratable): + """A synthesizable module that plays back data captured by a LogicAnalyzerCore. + + Parameters: + ---------- + data : list[int] + The raw captured data taken by the LogicAnalyzerCore. This consists of the values of + all the input probes concatenated together at every timestep. + + config : dict + The configuration of the LogicAnalyzerCore that took this capture. + """ def __init__(self, data, config): self.data = data self.config = config diff --git a/src/manta/utils.py b/src/manta/utils.py index a680567..bb20271 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -116,6 +116,7 @@ def xilinx_tools_installed(): (ie, /tools/Xilinx/Vivado/2023.1/bin/vivado, not /tools/Xilinx/Vivado/2023.1/bin) """ from shutil import which + return ("VIVADO" in os.environ) or (which("vivado") is not None) @@ -136,9 +137,8 @@ def ice40_tools_installed(): # Check PATH binaries = ["yosys", "nextpnr-ice40", "icepack", "iceprog"] from shutil import which + if all([which(b) for b in binaries]): return True return False - - diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 49d064a..9b456d4 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -20,7 +20,7 @@ class LogicAnalyzerCounterTest(Elaboratable): "la": { "type": "logic_analyzer", "sample_depth": 1024, - "trigger_loc": 500, + "trigger_location": 500, "probes": {"larry": 1, "curly": 3, "moe": 9}, "triggers": ["moe RISING"], }, @@ -76,9 +76,9 @@ class LogicAnalyzerCounterTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_logic_analyzer_core_xilinx(): - LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB2").verify() + LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB3").verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_logic_analyzer_core_ice40(): - LogicAnalyzerCounterTest(ICEStickPlatform(), "/dev/ttyUSB1").verify() + LogicAnalyzerCounterTest(ICEStickPlatform(), "/dev/ttyUSB2").verify() From ee4a3026af9a54bdd87543b4145323087f1b6928 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 7 Jan 2024 18:17:09 -0800 Subject: [PATCH 20/89] refactor to use common bus layout across all modules --- doc/getting_started.md | 2 +- doc/logic_analyzer_core.md | 2 +- src/manta/io_core.py | 30 ++++-------- src/manta/logic_analyzer/__init__.py | 36 ++++---------- src/manta/logic_analyzer/fsm.py | 19 ++------ src/manta/logic_analyzer/trigger_block.py | 17 ++----- src/manta/manta.py | 21 ++------ src/manta/memory_core.py | 56 +++++++--------------- src/manta/uart.py | 58 ++++++++--------------- src/manta/utils.py | 37 ++++++++++----- test/test_bridge_rx_sim.py | 22 ++++----- test/test_bridge_tx_sim.py | 12 ++--- test/test_logic_analyzer_sim.py | 18 +++---- 13 files changed, 119 insertions(+), 211 deletions(-) diff --git a/doc/getting_started.md b/doc/getting_started.md index 8da0adb..2913ef3 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -31,7 +31,7 @@ cores: my_logic_analyzer: type: logic_analyzer sample_depth: 4096 - trigger_loc: 1000 + trigger_location: 1000 probes: larry: 1 diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index 8dcb3e8..5f245c1 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -14,7 +14,7 @@ cores: my_logic_analyzer: type: logic_analyzer sample_depth: 4096 - trigger_loc: 1000 + trigger_location: 1000 probes: larry: 1 diff --git a/src/manta/io_core.py b/src/manta/io_core.py index c12096a..b1d9e5c 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -88,15 +88,8 @@ class IOCore(Elaboratable): def define_signals(self): # Bus Ports - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal() - self.valid_i = Signal() - - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal() - self.valid_o = Signal() + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) # Input Probes (and buffers) if "inputs" in self.config: @@ -187,10 +180,7 @@ class IOCore(Elaboratable): m = Module() # Shuffle bus transactions along - m.d.sync += self.addr_o.eq(self.addr_i) - m.d.sync += self.data_o.eq(self.data_i) - m.d.sync += self.rw_o.eq(self.rw_i) - m.d.sync += self.valid_o.eq(self.valid_i) + m.d.sync += self.bus_o.eq(self.bus_i) # Update buffers from probes with m.If(self.strobe): @@ -209,17 +199,17 @@ class IOCore(Elaboratable): m.d.sync += output_probe.eq(output_probe_buf) # Handle register reads and writes - with m.If((self.addr_i >= self.base_addr)): - with m.If((self.addr_o <= self.max_addr)): + with m.If((self.bus_i.addr >= self.base_addr)): + with m.If((self.bus_o.addr <= self.max_addr)): for entry in self.mmap.values(): for addr, signal in zip(entry["addrs"], entry["signals"]): - with m.If(self.rw_i): - with m.If(self.addr_i == addr): - m.d.sync += signal.eq(self.data_i) + with m.If(self.bus_i.rw): + with m.If(self.bus_i.addr == addr): + m.d.sync += signal.eq(self.bus_i.data) with m.Else(): - with m.If(self.addr_i == addr): - m.d.sync += self.data_o.eq(signal) + with m.If(self.bus_i.addr == addr): + m.d.sync += self.bus_o.data.eq(signal) return m diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index fcb27d9..a64554d 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -36,18 +36,11 @@ class LogicAnalyzerCore(Elaboratable): self.config = config self.check_config(config) - # Bus Input - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal(1) - self.valid_i = Signal(1) - - # Bus Output - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal(1) - self.valid_o = Signal(1) + # Bus Input/Output + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) + # Probes self.probes = [ Signal(width, name=name) for name, width in self.config["probes"].items() ] @@ -177,22 +170,11 @@ class LogicAnalyzerCore(Elaboratable): # Wire bus connections between internal modules m.d.comb += [ # Bus Connections - fsm.addr_i.eq(self.addr_i), - fsm.data_i.eq(self.data_i), - fsm.rw_i.eq(self.rw_i), - fsm.valid_i.eq(self.valid_i), - trig_blk.addr_i.eq(fsm.addr_o), - trig_blk.data_i.eq(fsm.data_o), - trig_blk.rw_i.eq(fsm.rw_o), - trig_blk.valid_i.eq(fsm.valid_o), - sample_mem.addr_i.eq(trig_blk.addr_o), - sample_mem.data_i.eq(trig_blk.data_o), - sample_mem.rw_i.eq(trig_blk.rw_o), - sample_mem.valid_i.eq(trig_blk.valid_o), - self.addr_o.eq(sample_mem.addr_o), - self.data_o.eq(sample_mem.data_o), - self.rw_o.eq(sample_mem.rw_o), - self.valid_o.eq(sample_mem.valid_o), + fsm.bus_i.eq(self.bus_i), + trig_blk.bus_i.eq(fsm.bus_o), + sample_mem.bus_i.eq(trig_blk.bus_o), + self.bus_o.eq(sample_mem.bus_o), + # Non-bus Connections fsm.trigger.eq(trig_blk.trig), sample_mem.user_addr.eq(fsm.r.write_pointer), diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index b2f0059..c2a72e8 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -1,11 +1,10 @@ from amaranth import * from math import ceil, log2 from ..io_core import IOCore +from ..utils import * class LogicAnalyzerFSM(Elaboratable): - """ """ - def __init__(self, config, base_addr, interface): self.config = config self.states = { @@ -37,24 +36,14 @@ class LogicAnalyzerFSM(Elaboratable): self.r = IOCore(register_config, base_addr, interface) - # Bus Input - self.addr_i = self.r.addr_i - self.data_i = self.r.data_i - self.rw_i = self.r.rw_i - self.valid_i = self.r.valid_i - - # Bus Output - self.addr_o = self.r.addr_o - self.data_o = self.r.data_o - self.rw_o = self.r.rw_o - self.valid_o = self.r.valid_o + # Bus Input/Output + self.bus_i = self.r.bus_i + self.bus_o = self.r.bus_o def get_max_addr(self): return self.r.get_max_addr() def increment_mod_sample_depth(self, m, signal): - # m.d.sync += signal.eq((signal + 1) % self.config["sample_depth"]) - with m.If(signal == self.config["sample_depth"] - 1): m.d.sync += signal.eq(0) diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 2b15530..191b5d1 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -1,10 +1,9 @@ from amaranth import * from ..io_core import IOCore +from ..utils import * class LogicAnalyzerTriggerBlock(Elaboratable): - """ """ - def __init__(self, probes, base_addr, interface): # Instantiate a bunch of trigger blocks self.probes = probes @@ -18,17 +17,9 @@ class LogicAnalyzerTriggerBlock(Elaboratable): self.r = IOCore({"outputs": outputs}, base_addr, interface) - # Bus Input - self.addr_i = self.r.addr_i - self.data_i = self.r.data_i - self.rw_i = self.r.rw_i - self.valid_i = self.r.valid_i - - # Bus Output - self.addr_o = self.r.addr_o - self.data_o = self.r.data_o - self.rw_o = self.r.rw_o - self.valid_o = self.r.valid_o + # Bus Input/Output + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) # Global trigger. High if any probe is triggered. self.trig = Signal(1) diff --git a/src/manta/manta.py b/src/manta/manta.py index 97f1b4c..eb7e91b 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -136,28 +136,15 @@ class Manta(Elaboratable): core_instances = list(self.cores.values()) first_core = core_instances[0] last_core = core_instances[-1] - m.d.comb += [ - first_core.addr_i.eq(self.interface.addr_o), - first_core.data_i.eq(self.interface.data_o), - first_core.rw_i.eq(self.interface.rw_o), - first_core.valid_i.eq(self.interface.valid_o), - self.interface.addr_i.eq(last_core.addr_o), - self.interface.data_i.eq(last_core.data_o), - self.interface.rw_i.eq(last_core.rw_o), - self.interface.valid_i.eq(last_core.valid_o), - ] + + first_core.bus_i.eq(self.interface.bus_o) + self.interface.bus_i.eq(self.interface.bus_o) # Connect output of ith core to input of (i+1)th core for i in range(len(core_instances) - 1): ith_core = core_instances[i] i_plus_oneth_core = core_instances[i + 1] - - m.d.comb += [ - i_plus_oneth_core.addr_i.eq(ith_core.addr_o), - i_plus_oneth_core.data_i.eq(ith_core.data_o), - i_plus_oneth_core.rw_i.eq(ith_core.rw_o), - i_plus_oneth_core.valid_i.eq(ith_core.valid_o), - ] + i_plus_oneth_core.bus_i.eq(ith_core.bus_o) return m diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index cf4d9ae..b08d47e 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -47,23 +47,10 @@ class ReadOnlyMemoryCore(Elaboratable): raise ValueError("Width of memory core must be positive. ") def define_signals(self): - # Bus Input - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal(1) - self.valid_i = Signal(1) - - # Bus Pipelining - self.addr_pipe = [Signal(16) for _ in range(3)] - self.data_pipe = [Signal(16) for _ in range(3)] - self.rw_pipe = [Signal(1) for _ in range(3)] - self.valid_pipe = [Signal(1) for _ in range(3)] - - # Bus Output - self.addr_o = Signal(16, reset=0) - self.data_o = Signal(16, reset=0) - self.rw_o = Signal(1, reset=0) - self.valid_o = Signal(1, reset=0) + # Bus Input/Pipelining/Output + self.bus_i = Signal(InternalBus()) + self.bus_pipe = [Signal(InternalBus()) for _ in range(3)] + self.bus_o = Signal(InternalBus()) # User Port self.user_addr = Signal(range(self.depth)) @@ -72,21 +59,12 @@ class ReadOnlyMemoryCore(Elaboratable): def pipeline_bus(self, m): # Pipelining - m.d.sync += self.addr_pipe[0].eq(self.addr_i) - m.d.sync += self.data_pipe[0].eq(self.data_i) - m.d.sync += self.rw_pipe[0].eq(self.rw_i) - m.d.sync += self.valid_pipe[0].eq(self.valid_i) + m.d.sync += self.bus_pipe[0].eq(self.bus_i) for i in range(1, 3): - m.d.sync += self.addr_pipe[i].eq(self.addr_pipe[i - 1]) - m.d.sync += self.data_pipe[i].eq(self.data_pipe[i - 1]) - m.d.sync += self.rw_pipe[i].eq(self.rw_pipe[i - 1]) - m.d.sync += self.valid_pipe[i].eq(self.valid_pipe[i - 1]) + m.d.sync += self.bus_pipe[i].eq(self.bus_pipe[i-1]) - m.d.sync += self.addr_o.eq(self.addr_pipe[2]) - m.d.sync += self.data_o.eq(self.data_pipe[2]) - m.d.sync += self.rw_o.eq(self.rw_pipe[2]) - m.d.sync += self.valid_o.eq(self.valid_pipe[2]) + m.d.sync += self.bus_o.eq(self.bus_pipe[2]) def define_mems(self): # ok there's three cases: @@ -122,21 +100,21 @@ class ReadOnlyMemoryCore(Elaboratable): # Throw BRAM operations into the front of the pipeline with m.If( - (self.valid_i) - & (~self.rw_i) - & (self.addr_i >= start_addr) - & (self.addr_i <= stop_addr) + (self.bus_i.valid) + & (~self.bus_i.rw) + & (self.bus_i.addr >= start_addr) + & (self.bus_i.addr <= stop_addr) ): - m.d.sync += read_port.addr.eq(self.addr_i - start_addr) + m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) # Pull BRAM reads from the back of the pipeline with m.If( - (self.valid_pipe[2]) - & (~self.rw_pipe[2]) - & (self.addr_pipe[2] >= start_addr) - & (self.addr_pipe[2] <= stop_addr) + (self.bus_pipe[2].valid) + & (~self.bus_pipe[2].rw) + & (self.bus_pipe[2].addr >= start_addr) + & (self.bus_pipe[2].addr <= stop_addr) ): - m.d.sync += self.data_o.eq(read_port.data) + m.d.sync += self.bus_o.data.eq(read_port.data) def handle_write_ports(self, m): # These are given to the user diff --git a/src/manta/uart.py b/src/manta/uart.py index cba6337..0f6a395 100644 --- a/src/manta/uart.py +++ b/src/manta/uart.py @@ -222,15 +222,8 @@ class UARTInterface(Elaboratable): self.rx = Signal() self.tx = Signal() - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal() - self.valid_o = Signal() - - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal() - self.valid_i = Signal() + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) def elaborate(self, platform): # fancy submoduling and such goes in here @@ -246,14 +239,9 @@ class UARTInterface(Elaboratable): uart_rx.rx.eq(self.rx), bridge_rx.data_i.eq(uart_rx.data_o), bridge_rx.valid_i.eq(uart_rx.valid_o), - self.data_o.eq(bridge_rx.data_o), - self.addr_o.eq(bridge_rx.addr_o), - self.rw_o.eq(bridge_rx.rw_o), - self.valid_o.eq(bridge_rx.valid_o), + self.bus_o.data.eq(bridge_rx.bus_o), # Internal Bus -> UART TX - bridge_tx.data_i.eq(self.data_i), - bridge_tx.rw_i.eq(self.rw_i), - bridge_tx.valid_i.eq(self.valid_i), + bridge_tx.bus_i.eq(self.bus_i), uart_tx.data_i.eq(bridge_tx.data_o), uart_tx.start_i.eq(bridge_tx.start_o), bridge_tx.done_i.eq(uart_tx.done_o), @@ -326,10 +314,7 @@ class RecieveBridge(Elaboratable): self.data_i = Signal(8) self.valid_i = Signal() - self.addr_o = Signal(16, reset=0) - self.data_o = Signal(16, reset=0) - self.rw_o = Signal(1, reset=0) - self.valid_o = Signal(1, reset=0) + self.bus_o = Signal(InternalBus()) # State Machine self.IDLE_STATE = 0 @@ -369,30 +354,27 @@ class RecieveBridge(Elaboratable): with m.If( (self.state == self.READ_STATE) & (self.byte_num == 4) & (self.is_eol) ): - m.d.comb += self.addr_o.eq( + m.d.comb += self.bus_o.addr.eq( Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) ) - m.d.comb += self.data_o.eq(0) - m.d.comb += self.valid_o.eq(1) - m.d.comb += self.rw_o.eq(0) + m.d.comb += self.bus_o.data.eq(0) + m.d.comb += self.bus_o.valid.eq(1) + m.d.comb += self.bus_o.rw.eq(0) with m.Elif( (self.state == self.WRITE_STATE) & (self.byte_num == 8) & (self.is_eol) ): - m.d.comb += self.addr_o.eq( + m.d.comb += self.bus_o.addr.eq( Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) ) - m.d.comb += self.data_o.eq( + m.d.comb += self.bus_o.data.eq( Cat(self.buffer[7], self.buffer[6], self.buffer[5], self.buffer[4]) ) - m.d.comb += self.valid_o.eq(1) - m.d.comb += self.rw_o.eq(1) + m.d.comb += self.bus_o.valid.eq(1) + m.d.comb += self.bus_o.rw.eq(1) with m.Else(): - m.d.comb += self.addr_o.eq(0) - m.d.comb += self.data_o.eq(0) - m.d.comb += self.rw_o.eq(0) - m.d.comb += self.valid_o.eq(0) + m.d.comb += self.bus_o.eq(0) def drive_fsm(self, m): with m.If(self.valid_i): @@ -500,9 +482,7 @@ class UARTTransmitter(Elaboratable): class TransmitBridge(Elaboratable): def __init__(self): # Top-Level Ports - self.data_i = Signal(16) - self.rw_i = Signal() - self.valid_i = Signal() + self.bus_i = Signal(InternalBus()) self.data_o = Signal(8, reset=0) self.start_o = Signal(1) @@ -521,9 +501,9 @@ class TransmitBridge(Elaboratable): m.d.comb += self.start_o.eq(self.busy) with m.If(~self.busy): - with m.If((self.valid_i) & (~self.rw_i)): + with m.If((self.bus_i.valid) & (~self.bus_i.rw)): m.d.sync += self.busy.eq(1) - m.d.sync += self.buffer.eq(self.data_i) + m.d.sync += self.buffer.eq(self.bus_i.data) with m.Else(): # uart_tx is transmitting a byte: @@ -535,8 +515,8 @@ class TransmitBridge(Elaboratable): m.d.sync += self.count.eq(0) # Go back to idle, or transmit next message - with m.If((self.valid_i) & (~self.rw_i)): - m.d.sync += self.buffer.eq(self.data_i) + with m.If((self.bus_i.valid) & (~self.bus_i.rw)): + m.d.sync += self.buffer.eq(self.bus_i.data) with m.Else(): m.d.sync += self.busy.eq(0) diff --git a/src/manta/utils.py b/src/manta/utils.py index bb20271..6ce9316 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,7 +1,16 @@ from amaranth.sim import Simulator +from amaranth.lib import data, enum from math import ceil import os +class InternalBus(data.StructLayout): + def __init__(self): + super().__init__({ + "addr": 16, + "data": 16, + "rw": 1, + "valid": 1 + }) def words_to_value(data): """ @@ -74,20 +83,20 @@ def verify_register(module, addr, expected_data): """ # place read transaction on the bus - yield module.addr_i.eq(addr) - yield module.data_i.eq(0) - yield module.rw_i.eq(0) - yield module.valid_i.eq(1) + yield module.bus_i.addr.eq(addr) + yield module.bus_i.data.eq(0) + yield module.bus_i.rw.eq(0) + yield module.bus_i.valid.eq(1) yield - yield module.addr_i.eq(0) - yield module.valid_i.eq(0) + yield module.bus_i.addr.eq(0) + yield module.bus_i.valid.eq(0) # wait for output to be valid - while not (yield module.valid_o): + while not (yield module.bus_o.valid): yield # compare returned value with expected - data = yield (module.data_o) + data = yield (module.bus_o.data) if data != expected_data: raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") @@ -98,12 +107,12 @@ def write_register(module, addr, data): at `addr`. """ - yield module.addr_i.eq(addr) - yield module.data_i.eq(data) - yield module.rw_i.eq(1) - yield module.valid_i.eq(1) + yield module.bus_i.addr.eq(addr) + yield module.bus_i.data.eq(data) + yield module.bus_i.rw.eq(1) + yield module.bus_i.valid.eq(1) yield - yield module.valid_i.eq(0) + yield module.bus_i.valid.eq(0) yield @@ -142,3 +151,5 @@ def ice40_tools_installed(): return True return False + + diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py index 89c3d4d..1e7415c 100644 --- a/test/test_bridge_rx_sim.py +++ b/test/test_bridge_rx_sim.py @@ -17,15 +17,15 @@ def verify_read_decoding(bytes, addr): for i, byte in enumerate(bytes): yield bridge_rx.data_i.eq(byte) - if (yield bridge_rx.valid_o) and (i > 0): + if (yield bridge_rx.bus_o.valid) and (i > 0): valid_asserted = True - if (yield bridge_rx.addr_o) != addr: + if (yield bridge_rx.bus_o.addr) != addr: raise ValueError("wrong addr!") - if (yield bridge_rx.rw_o) != 0: + if (yield bridge_rx.bus_o.rw) != 0: raise ValueError("wrong rw!") - if (yield bridge_rx.data_o) != 0: + if (yield bridge_rx.bus_o.data) != 0: raise ValueError("wrong data!") yield @@ -33,7 +33,7 @@ def verify_read_decoding(bytes, addr): yield bridge_rx.valid_i.eq(0) yield bridge_rx.data_i.eq(0) - if not valid_asserted and not (yield bridge_rx.valid_o): + if not valid_asserted and not (yield bridge_rx.bus_o.valid): raise ValueError("Bridge failed to output valid message.") @@ -48,15 +48,15 @@ def verify_write_decoding(bytes, addr, data): for i, byte in enumerate(bytes): yield bridge_rx.data_i.eq(byte) - if (yield bridge_rx.valid_o) and (i > 0): + if (yield bridge_rx.bus_o.valid) and (i > 0): valid_asserted = True - if (yield bridge_rx.addr_o) != addr: + if (yield bridge_rx.bus_o.addr) != addr: raise ValueError("wrong addr!") - if (yield bridge_rx.rw_o) != 1: + if (yield bridge_rx.bus_o.rw) != 1: raise ValueError("wrong rw!") - if (yield bridge_rx.data_o) != data: + if (yield bridge_rx.bus_o.data) != data: raise ValueError("wrong data!") yield @@ -64,7 +64,7 @@ def verify_write_decoding(bytes, addr, data): yield bridge_rx.valid_i.eq(0) yield bridge_rx.data_i.eq(0) - if not valid_asserted and not (yield bridge_rx.valid_o): + if not valid_asserted and not (yield bridge_rx.bus_o.valid): raise ValueError("Bridge failed to output valid message.") @@ -78,7 +78,7 @@ def verify_bad_bytes(bytes): for byte in bytes: yield bridge_rx.data_i.eq(byte) - if (yield bridge_rx.valid_o): + if (yield bridge_rx.bus_o.valid): raise ValueError("Bridge decoded invalid message.") yield diff --git a/test/test_bridge_tx_sim.py b/test/test_bridge_tx_sim.py index 9a1568d..db39fe7 100644 --- a/test/test_bridge_tx_sim.py +++ b/test/test_bridge_tx_sim.py @@ -17,16 +17,16 @@ def verify_encoding(data, bytes): """ # Place a read response on the internal bus - yield bridge_tx.data_i.eq(data) - yield bridge_tx.valid_i.eq(1) - yield bridge_tx.rw_i.eq(0) + yield bridge_tx.bus_i.data.eq(data) + yield bridge_tx.bus_i.valid.eq(1) + yield bridge_tx.bus_i.rw.eq(0) yield bridge_tx.done_i.eq(1) yield - yield bridge_tx.data_i.eq(0) - yield bridge_tx.valid_i.eq(0) - yield bridge_tx.rw_i.eq(0) + yield bridge_tx.bus_i.data.eq(0) + yield bridge_tx.bus_i.valid.eq(0) + yield bridge_tx.bus_i.rw.eq(0) yield diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index 72622ed..ebce934 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -6,7 +6,7 @@ from random import sample config = { "type": "logic_analyzer", "sample_depth": 1024, - "trigger_loc": 512, + "trigger_location": 512, "probes": {"larry": 1, "curly": 3, "moe": 9}, "triggers": ["moe RISING"], } @@ -16,19 +16,19 @@ la = LogicAnalyzerCore(config, base_addr=0, interface=None) def print_data_at_addr(addr): # place read transaction on the bus - yield la.addr_i.eq(addr) - yield la.data_i.eq(0) - yield la.rw_i.eq(0) - yield la.valid_i.eq(1) + yield la.bus_i.addr.eq(addr) + yield la.bus_i.data.eq(0) + yield la.bus_i.rw.eq(0) + yield la.bus_i.valid.eq(1) yield - yield la.addr_i.eq(0) - yield la.valid_i.eq(0) + yield la.bus_i.addr.eq(0) + yield la.bus_i.valid.eq(0) # wait for output to be valid - while not (yield la.valid_o): + while not (yield la.bus_o.valid): yield - print(f"addr: {hex(addr)} data: {hex((yield la.data_o))}") + print(f"addr: {hex(addr)} data: {hex((yield la.bus_o.data))}") def set_fsm_register(name, data): From fbaf93b110216c258864b1e90f6f52cc975da846 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 7 Jan 2024 18:54:33 -0800 Subject: [PATCH 21/89] fix typo introduced during refactor --- src/manta/logic_analyzer/trigger_block.py | 4 ++-- src/manta/utils.py | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 191b5d1..50f3496 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -18,8 +18,8 @@ class LogicAnalyzerTriggerBlock(Elaboratable): self.r = IOCore({"outputs": outputs}, base_addr, interface) # Bus Input/Output - self.bus_i = Signal(InternalBus()) - self.bus_o = Signal(InternalBus()) + self.bus_i = self.r.bus_i + self.bus_o = self.r.bus_o # Global trigger. High if any probe is triggered. self.trig = Signal(1) diff --git a/src/manta/utils.py b/src/manta/utils.py index 6ce9316..9c41948 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -4,6 +4,9 @@ from math import ceil import os class InternalBus(data.StructLayout): + """Describes the layout of Manta's internal bus, such that signals of + the appropriate dimension can be instantiated with Signal(InternalBus()). + """ def __init__(self): super().__init__({ "addr": 16, From 7a6ab45b9205844f833dc0dbceb67ca1ef41d84c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 7 Jan 2024 21:39:44 -0800 Subject: [PATCH 22/89] revert UART and InternalBus() refactor --- src/manta/io_core.py | 30 ++++++++---- src/manta/logic_analyzer/__init__.py | 36 ++++++++++---- src/manta/logic_analyzer/fsm.py | 19 ++++++-- src/manta/logic_analyzer/trigger_block.py | 17 +++++-- src/manta/manta.py | 21 ++++++-- src/manta/memory_core.py | 56 +++++++++++++++------- src/manta/uart.py | 58 +++++++++++++++-------- src/manta/utils.py | 40 +++++----------- test/test_bridge_rx_sim.py | 22 ++++----- test/test_bridge_tx_sim.py | 12 ++--- test/test_io_core_hw.py | 4 +- test/test_logic_analyzer_hw.py | 2 +- test/test_logic_analyzer_sim.py | 16 +++---- test/test_mem_core_hw.py | 4 +- 14 files changed, 213 insertions(+), 124 deletions(-) diff --git a/src/manta/io_core.py b/src/manta/io_core.py index b1d9e5c..c12096a 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -88,8 +88,15 @@ class IOCore(Elaboratable): def define_signals(self): # Bus Ports - self.bus_i = Signal(InternalBus()) - self.bus_o = Signal(InternalBus()) + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal() + self.valid_o = Signal() # Input Probes (and buffers) if "inputs" in self.config: @@ -180,7 +187,10 @@ class IOCore(Elaboratable): m = Module() # Shuffle bus transactions along - m.d.sync += self.bus_o.eq(self.bus_i) + m.d.sync += self.addr_o.eq(self.addr_i) + m.d.sync += self.data_o.eq(self.data_i) + m.d.sync += self.rw_o.eq(self.rw_i) + m.d.sync += self.valid_o.eq(self.valid_i) # Update buffers from probes with m.If(self.strobe): @@ -199,17 +209,17 @@ class IOCore(Elaboratable): m.d.sync += output_probe.eq(output_probe_buf) # Handle register reads and writes - with m.If((self.bus_i.addr >= self.base_addr)): - with m.If((self.bus_o.addr <= self.max_addr)): + with m.If((self.addr_i >= self.base_addr)): + with m.If((self.addr_o <= self.max_addr)): for entry in self.mmap.values(): for addr, signal in zip(entry["addrs"], entry["signals"]): - with m.If(self.bus_i.rw): - with m.If(self.bus_i.addr == addr): - m.d.sync += signal.eq(self.bus_i.data) + with m.If(self.rw_i): + with m.If(self.addr_i == addr): + m.d.sync += signal.eq(self.data_i) with m.Else(): - with m.If(self.bus_i.addr == addr): - m.d.sync += self.bus_o.data.eq(signal) + with m.If(self.addr_i == addr): + m.d.sync += self.data_o.eq(signal) return m diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index a64554d..fcb27d9 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -36,11 +36,18 @@ class LogicAnalyzerCore(Elaboratable): self.config = config self.check_config(config) - # Bus Input/Output - self.bus_i = Signal(InternalBus()) - self.bus_o = Signal(InternalBus()) + # Bus Input + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal(1) + self.valid_i = Signal(1) + + # Bus Output + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal(1) + self.valid_o = Signal(1) - # Probes self.probes = [ Signal(width, name=name) for name, width in self.config["probes"].items() ] @@ -170,11 +177,22 @@ class LogicAnalyzerCore(Elaboratable): # Wire bus connections between internal modules m.d.comb += [ # Bus Connections - fsm.bus_i.eq(self.bus_i), - trig_blk.bus_i.eq(fsm.bus_o), - sample_mem.bus_i.eq(trig_blk.bus_o), - self.bus_o.eq(sample_mem.bus_o), - + fsm.addr_i.eq(self.addr_i), + fsm.data_i.eq(self.data_i), + fsm.rw_i.eq(self.rw_i), + fsm.valid_i.eq(self.valid_i), + trig_blk.addr_i.eq(fsm.addr_o), + trig_blk.data_i.eq(fsm.data_o), + trig_blk.rw_i.eq(fsm.rw_o), + trig_blk.valid_i.eq(fsm.valid_o), + sample_mem.addr_i.eq(trig_blk.addr_o), + sample_mem.data_i.eq(trig_blk.data_o), + sample_mem.rw_i.eq(trig_blk.rw_o), + sample_mem.valid_i.eq(trig_blk.valid_o), + self.addr_o.eq(sample_mem.addr_o), + self.data_o.eq(sample_mem.data_o), + self.rw_o.eq(sample_mem.rw_o), + self.valid_o.eq(sample_mem.valid_o), # Non-bus Connections fsm.trigger.eq(trig_blk.trig), sample_mem.user_addr.eq(fsm.r.write_pointer), diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index c2a72e8..b2f0059 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -1,10 +1,11 @@ from amaranth import * from math import ceil, log2 from ..io_core import IOCore -from ..utils import * class LogicAnalyzerFSM(Elaboratable): + """ """ + def __init__(self, config, base_addr, interface): self.config = config self.states = { @@ -36,14 +37,24 @@ class LogicAnalyzerFSM(Elaboratable): self.r = IOCore(register_config, base_addr, interface) - # Bus Input/Output - self.bus_i = self.r.bus_i - self.bus_o = self.r.bus_o + # Bus Input + self.addr_i = self.r.addr_i + self.data_i = self.r.data_i + self.rw_i = self.r.rw_i + self.valid_i = self.r.valid_i + + # Bus Output + self.addr_o = self.r.addr_o + self.data_o = self.r.data_o + self.rw_o = self.r.rw_o + self.valid_o = self.r.valid_o def get_max_addr(self): return self.r.get_max_addr() def increment_mod_sample_depth(self, m, signal): + # m.d.sync += signal.eq((signal + 1) % self.config["sample_depth"]) + with m.If(signal == self.config["sample_depth"] - 1): m.d.sync += signal.eq(0) diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 50f3496..2b15530 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -1,9 +1,10 @@ from amaranth import * from ..io_core import IOCore -from ..utils import * class LogicAnalyzerTriggerBlock(Elaboratable): + """ """ + def __init__(self, probes, base_addr, interface): # Instantiate a bunch of trigger blocks self.probes = probes @@ -17,9 +18,17 @@ class LogicAnalyzerTriggerBlock(Elaboratable): self.r = IOCore({"outputs": outputs}, base_addr, interface) - # Bus Input/Output - self.bus_i = self.r.bus_i - self.bus_o = self.r.bus_o + # Bus Input + self.addr_i = self.r.addr_i + self.data_i = self.r.data_i + self.rw_i = self.r.rw_i + self.valid_i = self.r.valid_i + + # Bus Output + self.addr_o = self.r.addr_o + self.data_o = self.r.data_o + self.rw_o = self.r.rw_o + self.valid_o = self.r.valid_o # Global trigger. High if any probe is triggered. self.trig = Signal(1) diff --git a/src/manta/manta.py b/src/manta/manta.py index eb7e91b..97f1b4c 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -136,15 +136,28 @@ class Manta(Elaboratable): core_instances = list(self.cores.values()) first_core = core_instances[0] last_core = core_instances[-1] - - first_core.bus_i.eq(self.interface.bus_o) - self.interface.bus_i.eq(self.interface.bus_o) + m.d.comb += [ + first_core.addr_i.eq(self.interface.addr_o), + first_core.data_i.eq(self.interface.data_o), + first_core.rw_i.eq(self.interface.rw_o), + first_core.valid_i.eq(self.interface.valid_o), + self.interface.addr_i.eq(last_core.addr_o), + self.interface.data_i.eq(last_core.data_o), + self.interface.rw_i.eq(last_core.rw_o), + self.interface.valid_i.eq(last_core.valid_o), + ] # Connect output of ith core to input of (i+1)th core for i in range(len(core_instances) - 1): ith_core = core_instances[i] i_plus_oneth_core = core_instances[i + 1] - i_plus_oneth_core.bus_i.eq(ith_core.bus_o) + + m.d.comb += [ + i_plus_oneth_core.addr_i.eq(ith_core.addr_o), + i_plus_oneth_core.data_i.eq(ith_core.data_o), + i_plus_oneth_core.rw_i.eq(ith_core.rw_o), + i_plus_oneth_core.valid_i.eq(ith_core.valid_o), + ] return m diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index b08d47e..cf4d9ae 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -47,10 +47,23 @@ class ReadOnlyMemoryCore(Elaboratable): raise ValueError("Width of memory core must be positive. ") def define_signals(self): - # Bus Input/Pipelining/Output - self.bus_i = Signal(InternalBus()) - self.bus_pipe = [Signal(InternalBus()) for _ in range(3)] - self.bus_o = Signal(InternalBus()) + # Bus Input + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal(1) + self.valid_i = Signal(1) + + # Bus Pipelining + self.addr_pipe = [Signal(16) for _ in range(3)] + self.data_pipe = [Signal(16) for _ in range(3)] + self.rw_pipe = [Signal(1) for _ in range(3)] + self.valid_pipe = [Signal(1) for _ in range(3)] + + # Bus Output + self.addr_o = Signal(16, reset=0) + self.data_o = Signal(16, reset=0) + self.rw_o = Signal(1, reset=0) + self.valid_o = Signal(1, reset=0) # User Port self.user_addr = Signal(range(self.depth)) @@ -59,12 +72,21 @@ class ReadOnlyMemoryCore(Elaboratable): def pipeline_bus(self, m): # Pipelining - m.d.sync += self.bus_pipe[0].eq(self.bus_i) + m.d.sync += self.addr_pipe[0].eq(self.addr_i) + m.d.sync += self.data_pipe[0].eq(self.data_i) + m.d.sync += self.rw_pipe[0].eq(self.rw_i) + m.d.sync += self.valid_pipe[0].eq(self.valid_i) for i in range(1, 3): - m.d.sync += self.bus_pipe[i].eq(self.bus_pipe[i-1]) + m.d.sync += self.addr_pipe[i].eq(self.addr_pipe[i - 1]) + m.d.sync += self.data_pipe[i].eq(self.data_pipe[i - 1]) + m.d.sync += self.rw_pipe[i].eq(self.rw_pipe[i - 1]) + m.d.sync += self.valid_pipe[i].eq(self.valid_pipe[i - 1]) - m.d.sync += self.bus_o.eq(self.bus_pipe[2]) + m.d.sync += self.addr_o.eq(self.addr_pipe[2]) + m.d.sync += self.data_o.eq(self.data_pipe[2]) + m.d.sync += self.rw_o.eq(self.rw_pipe[2]) + m.d.sync += self.valid_o.eq(self.valid_pipe[2]) def define_mems(self): # ok there's three cases: @@ -100,21 +122,21 @@ class ReadOnlyMemoryCore(Elaboratable): # Throw BRAM operations into the front of the pipeline with m.If( - (self.bus_i.valid) - & (~self.bus_i.rw) - & (self.bus_i.addr >= start_addr) - & (self.bus_i.addr <= stop_addr) + (self.valid_i) + & (~self.rw_i) + & (self.addr_i >= start_addr) + & (self.addr_i <= stop_addr) ): - m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) + m.d.sync += read_port.addr.eq(self.addr_i - start_addr) # Pull BRAM reads from the back of the pipeline with m.If( - (self.bus_pipe[2].valid) - & (~self.bus_pipe[2].rw) - & (self.bus_pipe[2].addr >= start_addr) - & (self.bus_pipe[2].addr <= stop_addr) + (self.valid_pipe[2]) + & (~self.rw_pipe[2]) + & (self.addr_pipe[2] >= start_addr) + & (self.addr_pipe[2] <= stop_addr) ): - m.d.sync += self.bus_o.data.eq(read_port.data) + m.d.sync += self.data_o.eq(read_port.data) def handle_write_ports(self, m): # These are given to the user diff --git a/src/manta/uart.py b/src/manta/uart.py index 0f6a395..cba6337 100644 --- a/src/manta/uart.py +++ b/src/manta/uart.py @@ -222,8 +222,15 @@ class UARTInterface(Elaboratable): self.rx = Signal() self.tx = Signal() - self.bus_i = Signal(InternalBus()) - self.bus_o = Signal(InternalBus()) + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal() + self.valid_o = Signal() + + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() def elaborate(self, platform): # fancy submoduling and such goes in here @@ -239,9 +246,14 @@ class UARTInterface(Elaboratable): uart_rx.rx.eq(self.rx), bridge_rx.data_i.eq(uart_rx.data_o), bridge_rx.valid_i.eq(uart_rx.valid_o), - self.bus_o.data.eq(bridge_rx.bus_o), + self.data_o.eq(bridge_rx.data_o), + self.addr_o.eq(bridge_rx.addr_o), + self.rw_o.eq(bridge_rx.rw_o), + self.valid_o.eq(bridge_rx.valid_o), # Internal Bus -> UART TX - bridge_tx.bus_i.eq(self.bus_i), + bridge_tx.data_i.eq(self.data_i), + bridge_tx.rw_i.eq(self.rw_i), + bridge_tx.valid_i.eq(self.valid_i), uart_tx.data_i.eq(bridge_tx.data_o), uart_tx.start_i.eq(bridge_tx.start_o), bridge_tx.done_i.eq(uart_tx.done_o), @@ -314,7 +326,10 @@ class RecieveBridge(Elaboratable): self.data_i = Signal(8) self.valid_i = Signal() - self.bus_o = Signal(InternalBus()) + self.addr_o = Signal(16, reset=0) + self.data_o = Signal(16, reset=0) + self.rw_o = Signal(1, reset=0) + self.valid_o = Signal(1, reset=0) # State Machine self.IDLE_STATE = 0 @@ -354,27 +369,30 @@ class RecieveBridge(Elaboratable): with m.If( (self.state == self.READ_STATE) & (self.byte_num == 4) & (self.is_eol) ): - m.d.comb += self.bus_o.addr.eq( + m.d.comb += self.addr_o.eq( Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) ) - m.d.comb += self.bus_o.data.eq(0) - m.d.comb += self.bus_o.valid.eq(1) - m.d.comb += self.bus_o.rw.eq(0) + m.d.comb += self.data_o.eq(0) + m.d.comb += self.valid_o.eq(1) + m.d.comb += self.rw_o.eq(0) with m.Elif( (self.state == self.WRITE_STATE) & (self.byte_num == 8) & (self.is_eol) ): - m.d.comb += self.bus_o.addr.eq( + m.d.comb += self.addr_o.eq( Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) ) - m.d.comb += self.bus_o.data.eq( + m.d.comb += self.data_o.eq( Cat(self.buffer[7], self.buffer[6], self.buffer[5], self.buffer[4]) ) - m.d.comb += self.bus_o.valid.eq(1) - m.d.comb += self.bus_o.rw.eq(1) + m.d.comb += self.valid_o.eq(1) + m.d.comb += self.rw_o.eq(1) with m.Else(): - m.d.comb += self.bus_o.eq(0) + m.d.comb += self.addr_o.eq(0) + m.d.comb += self.data_o.eq(0) + m.d.comb += self.rw_o.eq(0) + m.d.comb += self.valid_o.eq(0) def drive_fsm(self, m): with m.If(self.valid_i): @@ -482,7 +500,9 @@ class UARTTransmitter(Elaboratable): class TransmitBridge(Elaboratable): def __init__(self): # Top-Level Ports - self.bus_i = Signal(InternalBus()) + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() self.data_o = Signal(8, reset=0) self.start_o = Signal(1) @@ -501,9 +521,9 @@ class TransmitBridge(Elaboratable): m.d.comb += self.start_o.eq(self.busy) with m.If(~self.busy): - with m.If((self.bus_i.valid) & (~self.bus_i.rw)): + with m.If((self.valid_i) & (~self.rw_i)): m.d.sync += self.busy.eq(1) - m.d.sync += self.buffer.eq(self.bus_i.data) + m.d.sync += self.buffer.eq(self.data_i) with m.Else(): # uart_tx is transmitting a byte: @@ -515,8 +535,8 @@ class TransmitBridge(Elaboratable): m.d.sync += self.count.eq(0) # Go back to idle, or transmit next message - with m.If((self.bus_i.valid) & (~self.bus_i.rw)): - m.d.sync += self.buffer.eq(self.bus_i.data) + with m.If((self.valid_i) & (~self.rw_i)): + m.d.sync += self.buffer.eq(self.data_i) with m.Else(): m.d.sync += self.busy.eq(0) diff --git a/src/manta/utils.py b/src/manta/utils.py index 9c41948..bb20271 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,19 +1,7 @@ from amaranth.sim import Simulator -from amaranth.lib import data, enum from math import ceil import os -class InternalBus(data.StructLayout): - """Describes the layout of Manta's internal bus, such that signals of - the appropriate dimension can be instantiated with Signal(InternalBus()). - """ - def __init__(self): - super().__init__({ - "addr": 16, - "data": 16, - "rw": 1, - "valid": 1 - }) def words_to_value(data): """ @@ -86,20 +74,20 @@ def verify_register(module, addr, expected_data): """ # place read transaction on the bus - yield module.bus_i.addr.eq(addr) - yield module.bus_i.data.eq(0) - yield module.bus_i.rw.eq(0) - yield module.bus_i.valid.eq(1) + yield module.addr_i.eq(addr) + yield module.data_i.eq(0) + yield module.rw_i.eq(0) + yield module.valid_i.eq(1) yield - yield module.bus_i.addr.eq(0) - yield module.bus_i.valid.eq(0) + yield module.addr_i.eq(0) + yield module.valid_i.eq(0) # wait for output to be valid - while not (yield module.bus_o.valid): + while not (yield module.valid_o): yield # compare returned value with expected - data = yield (module.bus_o.data) + data = yield (module.data_o) if data != expected_data: raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") @@ -110,12 +98,12 @@ def write_register(module, addr, data): at `addr`. """ - yield module.bus_i.addr.eq(addr) - yield module.bus_i.data.eq(data) - yield module.bus_i.rw.eq(1) - yield module.bus_i.valid.eq(1) + yield module.addr_i.eq(addr) + yield module.data_i.eq(data) + yield module.rw_i.eq(1) + yield module.valid_i.eq(1) yield - yield module.bus_i.valid.eq(0) + yield module.valid_i.eq(0) yield @@ -154,5 +142,3 @@ def ice40_tools_installed(): return True return False - - diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py index 1e7415c..89c3d4d 100644 --- a/test/test_bridge_rx_sim.py +++ b/test/test_bridge_rx_sim.py @@ -17,15 +17,15 @@ def verify_read_decoding(bytes, addr): for i, byte in enumerate(bytes): yield bridge_rx.data_i.eq(byte) - if (yield bridge_rx.bus_o.valid) and (i > 0): + if (yield bridge_rx.valid_o) and (i > 0): valid_asserted = True - if (yield bridge_rx.bus_o.addr) != addr: + if (yield bridge_rx.addr_o) != addr: raise ValueError("wrong addr!") - if (yield bridge_rx.bus_o.rw) != 0: + if (yield bridge_rx.rw_o) != 0: raise ValueError("wrong rw!") - if (yield bridge_rx.bus_o.data) != 0: + if (yield bridge_rx.data_o) != 0: raise ValueError("wrong data!") yield @@ -33,7 +33,7 @@ def verify_read_decoding(bytes, addr): yield bridge_rx.valid_i.eq(0) yield bridge_rx.data_i.eq(0) - if not valid_asserted and not (yield bridge_rx.bus_o.valid): + if not valid_asserted and not (yield bridge_rx.valid_o): raise ValueError("Bridge failed to output valid message.") @@ -48,15 +48,15 @@ def verify_write_decoding(bytes, addr, data): for i, byte in enumerate(bytes): yield bridge_rx.data_i.eq(byte) - if (yield bridge_rx.bus_o.valid) and (i > 0): + if (yield bridge_rx.valid_o) and (i > 0): valid_asserted = True - if (yield bridge_rx.bus_o.addr) != addr: + if (yield bridge_rx.addr_o) != addr: raise ValueError("wrong addr!") - if (yield bridge_rx.bus_o.rw) != 1: + if (yield bridge_rx.rw_o) != 1: raise ValueError("wrong rw!") - if (yield bridge_rx.bus_o.data) != data: + if (yield bridge_rx.data_o) != data: raise ValueError("wrong data!") yield @@ -64,7 +64,7 @@ def verify_write_decoding(bytes, addr, data): yield bridge_rx.valid_i.eq(0) yield bridge_rx.data_i.eq(0) - if not valid_asserted and not (yield bridge_rx.bus_o.valid): + if not valid_asserted and not (yield bridge_rx.valid_o): raise ValueError("Bridge failed to output valid message.") @@ -78,7 +78,7 @@ def verify_bad_bytes(bytes): for byte in bytes: yield bridge_rx.data_i.eq(byte) - if (yield bridge_rx.bus_o.valid): + if (yield bridge_rx.valid_o): raise ValueError("Bridge decoded invalid message.") yield diff --git a/test/test_bridge_tx_sim.py b/test/test_bridge_tx_sim.py index db39fe7..9a1568d 100644 --- a/test/test_bridge_tx_sim.py +++ b/test/test_bridge_tx_sim.py @@ -17,16 +17,16 @@ def verify_encoding(data, bytes): """ # Place a read response on the internal bus - yield bridge_tx.bus_i.data.eq(data) - yield bridge_tx.bus_i.valid.eq(1) - yield bridge_tx.bus_i.rw.eq(0) + yield bridge_tx.data_i.eq(data) + yield bridge_tx.valid_i.eq(1) + yield bridge_tx.rw_i.eq(0) yield bridge_tx.done_i.eq(1) yield - yield bridge_tx.bus_i.data.eq(0) - yield bridge_tx.bus_i.valid.eq(0) - yield bridge_tx.bus_i.rw.eq(0) + yield bridge_tx.data_i.eq(0) + yield bridge_tx.valid_i.eq(0) + yield bridge_tx.rw_i.eq(0) yield diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 25f0b2c..c463aa6 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -121,9 +121,9 @@ class IOCoreLoopbackTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_output_probe_initial_values_xilinx(): - IOCoreLoopbackTest(Nexys4DDRPlatform(), "/dev/ttyUSB2").verify() + IOCoreLoopbackTest(Nexys4DDRPlatform(), "/dev/ttyUSB1").verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_output_probe_initial_values_ice40(): - IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB1").verify() + IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB2").verify() diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 9b456d4..5bfd0ca 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -76,7 +76,7 @@ class LogicAnalyzerCounterTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_logic_analyzer_core_xilinx(): - LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB3").verify() + LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB1").verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index ebce934..e69db0c 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -16,19 +16,19 @@ la = LogicAnalyzerCore(config, base_addr=0, interface=None) def print_data_at_addr(addr): # place read transaction on the bus - yield la.bus_i.addr.eq(addr) - yield la.bus_i.data.eq(0) - yield la.bus_i.rw.eq(0) - yield la.bus_i.valid.eq(1) + yield la.addr_i.eq(addr) + yield la.data_i.eq(0) + yield la.rw_i.eq(0) + yield la.valid_i.eq(1) yield - yield la.bus_i.addr.eq(0) - yield la.bus_i.valid.eq(0) + yield la.addr_i.eq(0) + yield la.valid_i.eq(0) # wait for output to be valid - while not (yield la.bus_o.valid): + while not (yield la.valid_o): yield - print(f"addr: {hex(addr)} data: {hex((yield la.bus_o.data))}") + print(f"addr: {hex(addr)} data: {hex((yield la.data_o))}") def set_fsm_register(name, data): diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index cb3c1de..8c7af24 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -94,12 +94,12 @@ class MemoryCoreLoopbackTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_mem_core_xilinx(): - MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, "/dev/ttyUSB2").verify() + MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, "/dev/ttyUSB1").verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_mem_core_ice40(): - port = "/dev/ttyUSB1" + port = "/dev/ttyUSB2" MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 2, port).verify() MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 512, port).verify() MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 1024, port).verify() From a7625ce0a4e1b9b1d8fa56a18e8da0cdf100d099 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 7 Jan 2024 21:54:14 -0800 Subject: [PATCH 23/89] refactor uart into multiple files --- src/manta/logic_analyzer/playback.py | 1 + src/manta/uart.py | 583 --------------------------- src/manta/uart/__init__.py | 265 ++++++++++++ src/manta/uart/receive_bridge.py | 128 ++++++ src/manta/uart/receiver.py | 59 +++ src/manta/uart/transmit_bridge.py | 87 ++++ src/manta/uart/transmitter.py | 52 +++ src/manta/utils.py | 9 + test/test_bridge_rx_sim.py | 4 +- 9 files changed, 603 insertions(+), 585 deletions(-) delete mode 100644 src/manta/uart.py create mode 100644 src/manta/uart/__init__.py create mode 100644 src/manta/uart/receive_bridge.py create mode 100644 src/manta/uart/receiver.py create mode 100644 src/manta/uart/transmit_bridge.py create mode 100644 src/manta/uart/transmitter.py diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index cc392f3..a08db8a 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -13,6 +13,7 @@ class LogicAnalyzerPlayback(Elaboratable): config : dict The configuration of the LogicAnalyzerCore that took this capture. """ + def __init__(self, data, config): self.data = data self.config = config diff --git a/src/manta/uart.py b/src/manta/uart.py deleted file mode 100644 index cba6337..0000000 --- a/src/manta/uart.py +++ /dev/null @@ -1,583 +0,0 @@ -from amaranth import * -from amaranth.lib.data import ArrayLayout -from warnings import warn -from .utils import * -from serial import Serial - - -class UARTInterface(Elaboratable): - def __init__(self, config): - self.config = config - self.check_config(self.config) - - self.port = config["port"] - self.clock_freq = config["clock_freq"] - self.baudrate = config["baudrate"] - self.clocks_per_baud = int(self.clock_freq // self.baudrate) - - self.define_signals() - - # Set chunk_size, which is the max amount of bytes that the core will - # dump to the OS driver at a time. Since the FPGA will return bytes - # almost instantaneously, this prevents the OS's input buffer from - # overflowing, and dropping bytes. - self.chunk_size = 256 # in bytes - if "chunk_size" in config: - self.chunk_size = config["chunk_size"] - - def check_config(self, config): - # Warn if unrecognized options have been given - recognized_options = ["port", "clock_freq", "baudrate", "chunk_size"] - for option in config: - if option not in recognized_options: - warn( - f"Ignoring unrecognized option '{option}' in UART interface config." - ) - - # Ensure a serial port has been given - if "port" not in config: - raise ValueError("No serial port provided to UART interface.") - - # Ensure clock frequency is provided and positive - if "clock_freq" not in config: - raise ValueError("No clock frequency provided to UART interface.") - - if config["clock_freq"] <= 0: - raise ValueError("Non-positive clock frequency provided to UART interface.") - - # Check that baudrate is provided and positive - if "baudrate" not in config: - raise ValueError("No baudrate provided to UART interface.") - - if config["baudrate"] <= 0: - raise ValueError("Non-positive baudrate provided to UART interface.") - - # Confirm the actual baudrate is within 5% of the target baudrate - clock_freq = config["clock_freq"] - baudrate = config["baudrate"] - clocks_per_baud = clock_freq // baudrate - actual_baudrate = clock_freq / clocks_per_baud - error = 100 * abs(actual_baudrate - baudrate) / baudrate - - if error > 5: - raise ValueError( - "UART interface is unable to match targeted baudrate with specified clock frequency." - ) - - def get_serial_device(self): - """ - Return an open PySerial serial device if one exists, otherwise, open one. - """ - if hasattr(self, "serial_device"): - return self.serial_device - - else: - if self.port != "auto": - self.serial_device = Serial(self.port, self.baudrate, timeout=1) - return self.serial_device - - else: - # Try to autodetect which port to use based on the PID/VID of the device attached. - # This looks for the PID/VID of the FT2232, the primary chip used on the icestick - # and Digilent dev boards. However, folks will likely want to connect other things - # in the future, so in the future we'll probably want to look for other chips as - # well. - - # The FT2232 exposes two serial ports - and for whatever reason it usually has the - # 0th device used for JTAG programming, and the 1st used for UART. So we'll grab - # the 1st. - - import serial.tools.list_ports - - ports = [] - for port in serial.tools.list_ports.comports(): - if (port.vid == 0x403) and (port.pid == 0x6010): - ports.append(port) - - if len(ports) != 2: - raise ValueError( - f"Expected to see two serial ports for FT2232 device, but instead see {len(ports)}." - ) - - if ports[0].serial_number != ports[1].serial_number: - raise ValueError( - f"Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices." - ) - - if ports[0].location > ports[1].location: - chosen_port = ports[0].device - - else: - chosen_port = ports[1].device - - self.serial_device = Serial(chosen_port, self.baudrate, timeout=1) - return self.serial_device - - def get_top_level_ports(self): - return [self.rx, self.tx] - - def read(self, addrs): - """ - Read the data stored in a set of address on Manta's internal memory. Addresses - must be specified as either integers or a list of integers. - """ - - # Handle a single integer address - if isinstance(addrs, int): - return self.read([addrs])[0] - - # Make sure all list elements are integers - if not all(isinstance(a, int) for a in addrs): - raise ValueError("Read address must be an integer or list of integers.") - - # Send read requests, and get responses - ser = self.get_serial_device() - addr_chunks = split_into_chunks(addrs, self.chunk_size) - datas = [] - - for addr_chunk in addr_chunks: - # Encode addrs into read requests - bytes_out = b"".join([f"R{a:04X}\r\n".encode("ascii") for a in addr_chunk]) - ser.write(bytes_out) - - # Read responses have the same length as read requests - bytes_in = ser.read(len(bytes_out)) - - if len(bytes_in) != len(bytes_out): - raise ValueError( - f"Only got {len(bytes_in)} out of {len(bytes_out)} bytes." - ) - - # Split received bytes into individual responses and decode - responses = split_into_chunks(bytes_in, 7) - data_chunk = [self.decode_read_response(r) for r in responses] - datas += data_chunk - - return datas - - def write(self, addrs, datas): - """ - Write the provided data into the provided addresses in Manta's internal memory. - Addresses and data must be specified as either integers or a list of integers. - """ - - # Handle a single integer address and data - if isinstance(addrs, int) and isinstance(datas, int): - return self.write([addrs], [datas]) - - # Make sure address and datas are all integers - if not isinstance(addrs, list) or not isinstance(datas, list): - raise ValueError( - "Write addresses and data must be an integer or list of integers." - ) - - if not all(isinstance(a, int) for a in addrs): - raise ValueError("Write addresses must be all be integers.") - - if not all(isinstance(d, int) for d in datas): - raise ValueError("Write data must all be integers.") - - # I'm not sure if it's necessary to split outputs into chunks - # I think the output buffer doesn't really drop stuff, just the input buffer - - # Encode addrs and datas into write requests - bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, datas)]) - bytes_out = bytes_out.encode("ascii") - ser = self.get_serial_device() - ser.write(bytes_out) - - def decode_read_response(self, response_bytes): - """ - Check that read response is formatted properly, and extract the encoded data if so. - """ - - # Make sure response is not empty - if response_bytes is None: - raise ValueError("Unable to decode read response - no bytes received.") - - # Make sure response is properly encoded - response_ascii = response_bytes.decode("ascii") - - if len(response_ascii) != 7: - raise ValueError( - "Unable to decode read response - wrong number of bytes received." - ) - - if response_ascii[0] != "D": - raise ValueError("Unable to decode read response - incorrect preamble.") - - for i in range(1, 5): - if response_ascii[i] not in "0123456789ABCDEF": - raise ValueError("Unable to decode read response - invalid data byte.") - - if response_ascii[5] != "\r": - raise ValueError("Unable to decode read response - incorrect EOL.") - - if response_ascii[6] != "\n": - raise ValueError("Unable to decode read response - incorrect EOL.") - - return int(response_ascii[1:5], 16) - - def define_signals(self): - self.rx = Signal() - self.tx = Signal() - - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal() - self.valid_o = Signal() - - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal() - self.valid_i = Signal() - - def elaborate(self, platform): - # fancy submoduling and such goes in here - m = Module() - - m.submodules["uart_rx"] = uart_rx = UARTReceiver(self.clocks_per_baud) - m.submodules["bridge_rx"] = bridge_rx = RecieveBridge() - m.submodules["bridge_tx"] = bridge_tx = TransmitBridge() - m.submodules["uart_tx"] = uart_tx = UARTTransmitter(self.clocks_per_baud) - - m.d.comb += [ - # UART RX -> Internal Bus - uart_rx.rx.eq(self.rx), - bridge_rx.data_i.eq(uart_rx.data_o), - bridge_rx.valid_i.eq(uart_rx.valid_o), - self.data_o.eq(bridge_rx.data_o), - self.addr_o.eq(bridge_rx.addr_o), - self.rw_o.eq(bridge_rx.rw_o), - self.valid_o.eq(bridge_rx.valid_o), - # Internal Bus -> UART TX - bridge_tx.data_i.eq(self.data_i), - bridge_tx.rw_i.eq(self.rw_i), - bridge_tx.valid_i.eq(self.valid_i), - uart_tx.data_i.eq(bridge_tx.data_o), - uart_tx.start_i.eq(bridge_tx.start_o), - bridge_tx.done_i.eq(uart_tx.done_o), - self.tx.eq(uart_tx.tx), - ] - return m - - -class UARTReceiver(Elaboratable): - def __init__(self, clocks_per_baud): - self.clocks_per_baud = clocks_per_baud - - # Top-Level Ports - self.rx = Signal() - self.data_o = Signal(8, reset=0) - self.valid_o = Signal(1, reset=0) - - # Internal Signals - self.busy = Signal() - self.bit_index = Signal(range(10)) - self.baud_counter = Signal(range(2 * clocks_per_baud)) - - self.rx_d = Signal() - self.rx_q = Signal() - self.rx_q_prev = Signal() - - def elaborate(self, platform): - m = Module() - - # Two Flip-Flop Synchronizer - m.d.sync += [ - self.rx_d.eq(self.rx), - self.rx_q.eq(self.rx_d), - self.rx_q_prev.eq(self.rx_q), - ] - - m.d.sync += self.valid_o.eq(0) - - with m.If(~self.busy): - with m.If((~self.rx_q) & (self.rx_q_prev)): - m.d.sync += self.busy.eq(1) - m.d.sync += self.bit_index.eq(8) - m.d.sync += self.baud_counter.eq( - self.clocks_per_baud + (self.clocks_per_baud // 2) - 2 - ) - - with m.Else(): - with m.If(self.baud_counter == 0): - with m.If(self.bit_index == 0): - m.d.sync += self.valid_o.eq(1) - m.d.sync += self.busy.eq(0) - m.d.sync += self.bit_index.eq(0) - m.d.sync += self.baud_counter.eq(0) - - with m.Else(): - # m.d.sync += self.data_o.eq(Cat(self.rx_q, self.data_o[0:7])) - m.d.sync += self.data_o.eq(Cat(self.data_o[1:8], self.rx_q)) - m.d.sync += self.bit_index.eq(self.bit_index - 1) - m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) - - with m.Else(): - m.d.sync += self.baud_counter.eq(self.baud_counter - 1) - - return m - - -class RecieveBridge(Elaboratable): - def __init__(self): - # Top-Level Ports - self.data_i = Signal(8) - self.valid_i = Signal() - - self.addr_o = Signal(16, reset=0) - self.data_o = Signal(16, reset=0) - self.rw_o = Signal(1, reset=0) - self.valid_o = Signal(1, reset=0) - - # State Machine - self.IDLE_STATE = 0 - self.READ_STATE = 1 - self.WRITE_STATE = 2 - - # Internal Signals - self.buffer = Signal(ArrayLayout(4, 8), reset_less=True) - self.state = Signal(2, reset=self.IDLE_STATE) - self.byte_num = Signal(4, reset=0) - self.is_eol = Signal() - self.is_ascii_hex = Signal() - self.from_ascii_hex = Signal(8) - - def drive_ascii_signals(self, m): - # Decode 0-9 - with m.If((self.data_i >= 0x30) & (self.data_i <= 0x39)): - m.d.comb += self.is_ascii_hex.eq(1) - m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x30) - - # Decode A-F - with m.Elif((self.data_i >= 0x41) & (self.data_i <= 0x46)): - m.d.comb += self.is_ascii_hex.eq(1) - m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x41 + 10) - - with m.Else(): - m.d.comb += self.is_ascii_hex.eq(0) - m.d.comb += self.from_ascii_hex.eq(0) - - with m.If((self.data_i == ord("\r")) | (self.data_i == ord("\n"))): - m.d.comb += self.is_eol.eq(1) - - with m.Else(): - m.d.comb += self.is_eol.eq(0) - - def drive_output_bus(self, m): - with m.If( - (self.state == self.READ_STATE) & (self.byte_num == 4) & (self.is_eol) - ): - m.d.comb += self.addr_o.eq( - Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) - ) - m.d.comb += self.data_o.eq(0) - m.d.comb += self.valid_o.eq(1) - m.d.comb += self.rw_o.eq(0) - - with m.Elif( - (self.state == self.WRITE_STATE) & (self.byte_num == 8) & (self.is_eol) - ): - m.d.comb += self.addr_o.eq( - Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) - ) - m.d.comb += self.data_o.eq( - Cat(self.buffer[7], self.buffer[6], self.buffer[5], self.buffer[4]) - ) - m.d.comb += self.valid_o.eq(1) - m.d.comb += self.rw_o.eq(1) - - with m.Else(): - m.d.comb += self.addr_o.eq(0) - m.d.comb += self.data_o.eq(0) - m.d.comb += self.rw_o.eq(0) - m.d.comb += self.valid_o.eq(0) - - def drive_fsm(self, m): - with m.If(self.valid_i): - with m.If(self.state == self.IDLE_STATE): - m.d.sync += self.byte_num.eq(0) - - with m.If(self.data_i == ord("R")): - m.d.sync += self.state.eq(self.READ_STATE) - - with m.Elif(self.data_i == ord("W")): - m.d.sync += self.state.eq(self.WRITE_STATE) - - with m.If(self.state == self.READ_STATE): - # buffer bytes if we don't have enough - with m.If(self.byte_num < 4): - # if bytes aren't valid ASCII then return to IDLE state - with m.If(self.is_ascii_hex == 0): - m.d.sync += self.state.eq(self.IDLE_STATE) - - # otherwise buffer them - with m.Else(): - m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) - m.d.sync += self.byte_num.eq(self.byte_num + 1) - - with m.Else(): - m.d.sync += self.state.eq(self.IDLE_STATE) - - with m.If(self.state == self.WRITE_STATE): - # buffer bytes if we don't have enough - with m.If(self.byte_num < 8): - # if bytes aren't valid ASCII then return to IDLE state - with m.If(self.is_ascii_hex == 0): - m.d.sync += self.state.eq(self.IDLE_STATE) - - # otherwise buffer them - with m.Else(): - m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) - m.d.sync += self.byte_num.eq(self.byte_num + 1) - - with m.Else(): - m.d.sync += self.state.eq(self.IDLE_STATE) - pass - - def elaborate(self, platform): - m = Module() - - self.drive_ascii_signals(m) - self.drive_output_bus(m) - self.drive_fsm(m) - - return m - - -class UARTTransmitter(Elaboratable): - def __init__(self, clocks_per_baud): - self.clocks_per_baud = clocks_per_baud - - # Top-Level Ports - self.data_i = Signal(8) - self.start_i = Signal() - self.done_o = Signal(reset=1) - - self.tx = Signal(reset=1) - - # Internal Signals - self.baud_counter = Signal(range(clocks_per_baud)) - self.buffer = Signal(9) - self.bit_index = Signal(4) - - def elaborate(self, platform): - m = Module() - - with m.If((self.start_i) & (self.done_o)): - m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) - m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) - m.d.sync += self.bit_index.eq(0) - m.d.sync += self.done_o.eq(0) - m.d.sync += self.tx.eq(0) - - with m.Elif(~self.done_o): - m.d.sync += self.baud_counter.eq(self.baud_counter - 1) - m.d.sync += self.done_o.eq((self.baud_counter == 1) & (self.bit_index == 9)) - - # A baud period has elapsed - with m.If(self.baud_counter == 0): - m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) - - # Clock out another bit if there are any left - with m.If(self.bit_index < 9): - m.d.sync += self.tx.eq(self.buffer.bit_select(self.bit_index, 1)) - m.d.sync += self.bit_index.eq(self.bit_index + 1) - - # Byte has been sent, send out next one or go to idle - with m.Else(): - with m.If(self.start_i): - m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) - m.d.sync += self.bit_index.eq(0) - m.d.sync += self.tx.eq(0) - - with m.Else(): - m.d.sync += self.done_o.eq(1) - return m - - -class TransmitBridge(Elaboratable): - def __init__(self): - # Top-Level Ports - self.data_i = Signal(16) - self.rw_i = Signal() - self.valid_i = Signal() - - self.data_o = Signal(8, reset=0) - self.start_o = Signal(1) - self.done_i = Signal() - - # Internal Signals - self.buffer = Signal(16, reset=0) - self.count = Signal(4, reset=0) - self.busy = Signal(1, reset=0) - self.to_ascii_hex = Signal(8) - self.n = Signal(4) - - def elaborate(self, platform): - m = Module() - - m.d.comb += self.start_o.eq(self.busy) - - with m.If(~self.busy): - with m.If((self.valid_i) & (~self.rw_i)): - m.d.sync += self.busy.eq(1) - m.d.sync += self.buffer.eq(self.data_i) - - with m.Else(): - # uart_tx is transmitting a byte: - with m.If(self.done_i): - m.d.sync += self.count.eq(self.count + 1) - - # Message has been transmitted - with m.If(self.count > 5): - m.d.sync += self.count.eq(0) - - # Go back to idle, or transmit next message - with m.If((self.valid_i) & (~self.rw_i)): - m.d.sync += self.buffer.eq(self.data_i) - - with m.Else(): - m.d.sync += self.busy.eq(0) - - # define to_ascii_hex - with m.If(self.n < 10): - m.d.comb += self.to_ascii_hex.eq(self.n + 0x30) - with m.Else(): - m.d.comb += self.to_ascii_hex.eq(self.n + 0x41 - 10) - - # run the sequence - with m.If(self.count == 0): - m.d.comb += self.n.eq(0) - m.d.comb += self.data_o.eq(ord("D")) - - with m.Elif(self.count == 1): - m.d.comb += self.n.eq(self.buffer[12:16]) - m.d.comb += self.data_o.eq(self.to_ascii_hex) - - with m.Elif(self.count == 2): - m.d.comb += self.n.eq(self.buffer[8:12]) - m.d.comb += self.data_o.eq(self.to_ascii_hex) - - with m.Elif(self.count == 3): - m.d.comb += self.n.eq(self.buffer[4:8]) - m.d.comb += self.data_o.eq(self.to_ascii_hex) - - with m.Elif(self.count == 4): - m.d.comb += self.n.eq(self.buffer[0:4]) - m.d.comb += self.data_o.eq(self.to_ascii_hex) - - with m.Elif(self.count == 5): - m.d.comb += self.n.eq(0) - m.d.comb += self.data_o.eq(ord("\r")) - - with m.Elif(self.count == 6): - m.d.comb += self.n.eq(0) - m.d.comb += self.data_o.eq(ord("\n")) - - with m.Else(): - m.d.comb += self.n.eq(0) - m.d.comb += self.data_o.eq(0) - - return m diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py new file mode 100644 index 0000000..5f1556b --- /dev/null +++ b/src/manta/uart/__init__.py @@ -0,0 +1,265 @@ +from amaranth import * +from warnings import warn +from ..utils import * +from .receiver import UARTReceiver +from .receive_bridge import ReceiveBridge +from .transmitter import UARTTransmitter +from .transmit_bridge import TransmitBridge +from serial import Serial + + +class UARTInterface(Elaboratable): + def __init__(self, config): + self.config = config + self.check_config(self.config) + + self.port = config["port"] + self.clock_freq = config["clock_freq"] + self.baudrate = config["baudrate"] + self.clocks_per_baud = int(self.clock_freq // self.baudrate) + + self.define_signals() + + # Set chunk_size, which is the max amount of bytes that the core will + # dump to the OS driver at a time. Since the FPGA will return bytes + # almost instantaneously, this prevents the OS's input buffer from + # overflowing, and dropping bytes. + self.chunk_size = 256 # in bytes + if "chunk_size" in config: + self.chunk_size = config["chunk_size"] + + def check_config(self, config): + # Warn if unrecognized options have been given + recognized_options = ["port", "clock_freq", "baudrate", "chunk_size"] + for option in config: + if option not in recognized_options: + warn( + f"Ignoring unrecognized option '{option}' in UART interface config." + ) + + # Ensure a serial port has been given + if "port" not in config: + raise ValueError("No serial port provided to UART interface.") + + # Ensure clock frequency is provided and positive + if "clock_freq" not in config: + raise ValueError("No clock frequency provided to UART interface.") + + if config["clock_freq"] <= 0: + raise ValueError("Non-positive clock frequency provided to UART interface.") + + # Check that baudrate is provided and positive + if "baudrate" not in config: + raise ValueError("No baudrate provided to UART interface.") + + if config["baudrate"] <= 0: + raise ValueError("Non-positive baudrate provided to UART interface.") + + # Confirm the actual baudrate is within 5% of the target baudrate + clock_freq = config["clock_freq"] + baudrate = config["baudrate"] + clocks_per_baud = clock_freq // baudrate + actual_baudrate = clock_freq / clocks_per_baud + error = 100 * abs(actual_baudrate - baudrate) / baudrate + + if error > 5: + raise ValueError( + "UART interface is unable to match targeted baudrate with specified clock frequency." + ) + + def get_serial_device(self): + """ + Return an open PySerial serial device if one exists, otherwise, open one. + """ + if hasattr(self, "serial_device"): + return self.serial_device + + else: + if self.port != "auto": + self.serial_device = Serial(self.port, self.baudrate, timeout=1) + return self.serial_device + + else: + # Try to autodetect which port to use based on the PID/VID of the device attached. + # This looks for the PID/VID of the FT2232, the primary chip used on the icestick + # and Digilent dev boards. However, folks will likely want to connect other things + # in the future, so in the future we'll probably want to look for other chips as + # well. + + # The FT2232 exposes two serial ports - and for whatever reason it usually has the + # 0th device used for JTAG programming, and the 1st used for UART. So we'll grab + # the 1st. + + import serial.tools.list_ports + + ports = [] + for port in serial.tools.list_ports.comports(): + if (port.vid == 0x403) and (port.pid == 0x6010): + ports.append(port) + + if len(ports) != 2: + raise ValueError( + f"Expected to see two serial ports for FT2232 device, but instead see {len(ports)}." + ) + + if ports[0].serial_number != ports[1].serial_number: + raise ValueError( + f"Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices." + ) + + if ports[0].location > ports[1].location: + chosen_port = ports[0].device + + else: + chosen_port = ports[1].device + + self.serial_device = Serial(chosen_port, self.baudrate, timeout=1) + return self.serial_device + + def get_top_level_ports(self): + return [self.rx, self.tx] + + def read(self, addrs): + """ + Read the data stored in a set of address on Manta's internal memory. Addresses + must be specified as either integers or a list of integers. + """ + + # Handle a single integer address + if isinstance(addrs, int): + return self.read([addrs])[0] + + # Make sure all list elements are integers + if not all(isinstance(a, int) for a in addrs): + raise ValueError("Read address must be an integer or list of integers.") + + # Send read requests, and get responses + ser = self.get_serial_device() + addr_chunks = split_into_chunks(addrs, self.chunk_size) + datas = [] + + for addr_chunk in addr_chunks: + # Encode addrs into read requests + bytes_out = b"".join([f"R{a:04X}\r\n".encode("ascii") for a in addr_chunk]) + ser.write(bytes_out) + + # Read responses have the same length as read requests + bytes_in = ser.read(len(bytes_out)) + + if len(bytes_in) != len(bytes_out): + raise ValueError( + f"Only got {len(bytes_in)} out of {len(bytes_out)} bytes." + ) + + # Split received bytes into individual responses and decode + responses = split_into_chunks(bytes_in, 7) + data_chunk = [self.decode_read_response(r) for r in responses] + datas += data_chunk + + return datas + + def write(self, addrs, datas): + """ + Write the provided data into the provided addresses in Manta's internal memory. + Addresses and data must be specified as either integers or a list of integers. + """ + + # Handle a single integer address and data + if isinstance(addrs, int) and isinstance(datas, int): + return self.write([addrs], [datas]) + + # Make sure address and datas are all integers + if not isinstance(addrs, list) or not isinstance(datas, list): + raise ValueError( + "Write addresses and data must be an integer or list of integers." + ) + + if not all(isinstance(a, int) for a in addrs): + raise ValueError("Write addresses must be all be integers.") + + if not all(isinstance(d, int) for d in datas): + raise ValueError("Write data must all be integers.") + + # I'm not sure if it's necessary to split outputs into chunks + # I think the output buffer doesn't really drop stuff, just the input buffer + + # Encode addrs and datas into write requests + bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, datas)]) + bytes_out = bytes_out.encode("ascii") + ser = self.get_serial_device() + ser.write(bytes_out) + + def decode_read_response(self, response_bytes): + """ + Check that read response is formatted properly, and extract the encoded data if so. + """ + + # Make sure response is not empty + if response_bytes is None: + raise ValueError("Unable to decode read response - no bytes received.") + + # Make sure response is properly encoded + response_ascii = response_bytes.decode("ascii") + + if len(response_ascii) != 7: + raise ValueError( + "Unable to decode read response - wrong number of bytes received." + ) + + if response_ascii[0] != "D": + raise ValueError("Unable to decode read response - incorrect preamble.") + + for i in range(1, 5): + if response_ascii[i] not in "0123456789ABCDEF": + raise ValueError("Unable to decode read response - invalid data byte.") + + if response_ascii[5] != "\r": + raise ValueError("Unable to decode read response - incorrect EOL.") + + if response_ascii[6] != "\n": + raise ValueError("Unable to decode read response - incorrect EOL.") + + return int(response_ascii[1:5], 16) + + def define_signals(self): + self.rx = Signal() + self.tx = Signal() + + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal() + self.valid_o = Signal() + + self.addr_i = Signal(16) + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + def elaborate(self, platform): + # fancy submoduling and such goes in here + m = Module() + + m.submodules["uart_rx"] = uart_rx = UARTReceiver(self.clocks_per_baud) + m.submodules["bridge_rx"] = bridge_rx = ReceiveBridge() + m.submodules["bridge_tx"] = bridge_tx = TransmitBridge() + m.submodules["uart_tx"] = uart_tx = UARTTransmitter(self.clocks_per_baud) + + m.d.comb += [ + # UART RX -> Internal Bus + uart_rx.rx.eq(self.rx), + bridge_rx.data_i.eq(uart_rx.data_o), + bridge_rx.valid_i.eq(uart_rx.valid_o), + self.data_o.eq(bridge_rx.data_o), + self.addr_o.eq(bridge_rx.addr_o), + self.rw_o.eq(bridge_rx.rw_o), + self.valid_o.eq(bridge_rx.valid_o), + # Internal Bus -> UART TX + bridge_tx.data_i.eq(self.data_i), + bridge_tx.rw_i.eq(self.rw_i), + bridge_tx.valid_i.eq(self.valid_i), + uart_tx.data_i.eq(bridge_tx.data_o), + uart_tx.start_i.eq(bridge_tx.start_o), + bridge_tx.done_i.eq(uart_tx.done_o), + self.tx.eq(uart_tx.tx), + ] + return m diff --git a/src/manta/uart/receive_bridge.py b/src/manta/uart/receive_bridge.py new file mode 100644 index 0000000..4abbc7b --- /dev/null +++ b/src/manta/uart/receive_bridge.py @@ -0,0 +1,128 @@ +from amaranth import * +from amaranth.lib.data import ArrayLayout + + +class ReceiveBridge(Elaboratable): + def __init__(self): + # Top-Level Ports + self.data_i = Signal(8) + self.valid_i = Signal() + + self.addr_o = Signal(16, reset=0) + self.data_o = Signal(16, reset=0) + self.rw_o = Signal(1, reset=0) + self.valid_o = Signal(1, reset=0) + + # State Machine + self.IDLE_STATE = 0 + self.READ_STATE = 1 + self.WRITE_STATE = 2 + + # Internal Signals + self.buffer = Signal(ArrayLayout(4, 8), reset_less=True) + self.state = Signal(2, reset=self.IDLE_STATE) + self.byte_num = Signal(4, reset=0) + self.is_eol = Signal() + self.is_ascii_hex = Signal() + self.from_ascii_hex = Signal(8) + + def drive_ascii_signals(self, m): + # Decode 0-9 + with m.If((self.data_i >= 0x30) & (self.data_i <= 0x39)): + m.d.comb += self.is_ascii_hex.eq(1) + m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x30) + + # Decode A-F + with m.Elif((self.data_i >= 0x41) & (self.data_i <= 0x46)): + m.d.comb += self.is_ascii_hex.eq(1) + m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x41 + 10) + + with m.Else(): + m.d.comb += self.is_ascii_hex.eq(0) + m.d.comb += self.from_ascii_hex.eq(0) + + with m.If((self.data_i == ord("\r")) | (self.data_i == ord("\n"))): + m.d.comb += self.is_eol.eq(1) + + with m.Else(): + m.d.comb += self.is_eol.eq(0) + + def drive_output_bus(self, m): + with m.If( + (self.state == self.READ_STATE) & (self.byte_num == 4) & (self.is_eol) + ): + m.d.comb += self.addr_o.eq( + Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) + ) + m.d.comb += self.data_o.eq(0) + m.d.comb += self.valid_o.eq(1) + m.d.comb += self.rw_o.eq(0) + + with m.Elif( + (self.state == self.WRITE_STATE) & (self.byte_num == 8) & (self.is_eol) + ): + m.d.comb += self.addr_o.eq( + Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) + ) + m.d.comb += self.data_o.eq( + Cat(self.buffer[7], self.buffer[6], self.buffer[5], self.buffer[4]) + ) + m.d.comb += self.valid_o.eq(1) + m.d.comb += self.rw_o.eq(1) + + with m.Else(): + m.d.comb += self.addr_o.eq(0) + m.d.comb += self.data_o.eq(0) + m.d.comb += self.rw_o.eq(0) + m.d.comb += self.valid_o.eq(0) + + def drive_fsm(self, m): + with m.If(self.valid_i): + with m.If(self.state == self.IDLE_STATE): + m.d.sync += self.byte_num.eq(0) + + with m.If(self.data_i == ord("R")): + m.d.sync += self.state.eq(self.READ_STATE) + + with m.Elif(self.data_i == ord("W")): + m.d.sync += self.state.eq(self.WRITE_STATE) + + with m.If(self.state == self.READ_STATE): + # buffer bytes if we don't have enough + with m.If(self.byte_num < 4): + # if bytes aren't valid ASCII then return to IDLE state + with m.If(self.is_ascii_hex == 0): + m.d.sync += self.state.eq(self.IDLE_STATE) + + # otherwise buffer them + with m.Else(): + m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) + m.d.sync += self.byte_num.eq(self.byte_num + 1) + + with m.Else(): + m.d.sync += self.state.eq(self.IDLE_STATE) + + with m.If(self.state == self.WRITE_STATE): + # buffer bytes if we don't have enough + with m.If(self.byte_num < 8): + # if bytes aren't valid ASCII then return to IDLE state + with m.If(self.is_ascii_hex == 0): + m.d.sync += self.state.eq(self.IDLE_STATE) + + # otherwise buffer them + with m.Else(): + m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) + m.d.sync += self.byte_num.eq(self.byte_num + 1) + + with m.Else(): + m.d.sync += self.state.eq(self.IDLE_STATE) + pass + + def elaborate(self, platform): + m = Module() + + self.drive_ascii_signals(m) + self.drive_output_bus(m) + self.drive_fsm(m) + + return m diff --git a/src/manta/uart/receiver.py b/src/manta/uart/receiver.py new file mode 100644 index 0000000..70650cf --- /dev/null +++ b/src/manta/uart/receiver.py @@ -0,0 +1,59 @@ +from amaranth import * + + +class UARTReceiver(Elaboratable): + def __init__(self, clocks_per_baud): + self.clocks_per_baud = clocks_per_baud + + # Top-Level Ports + self.rx = Signal() + self.data_o = Signal(8, reset=0) + self.valid_o = Signal(1, reset=0) + + # Internal Signals + self.busy = Signal() + self.bit_index = Signal(range(10)) + self.baud_counter = Signal(range(2 * clocks_per_baud)) + + self.rx_d = Signal() + self.rx_q = Signal() + self.rx_q_prev = Signal() + + def elaborate(self, platform): + m = Module() + + # Two Flip-Flop Synchronizer + m.d.sync += [ + self.rx_d.eq(self.rx), + self.rx_q.eq(self.rx_d), + self.rx_q_prev.eq(self.rx_q), + ] + + m.d.sync += self.valid_o.eq(0) + + with m.If(~self.busy): + with m.If((~self.rx_q) & (self.rx_q_prev)): + m.d.sync += self.busy.eq(1) + m.d.sync += self.bit_index.eq(8) + m.d.sync += self.baud_counter.eq( + self.clocks_per_baud + (self.clocks_per_baud // 2) - 2 + ) + + with m.Else(): + with m.If(self.baud_counter == 0): + with m.If(self.bit_index == 0): + m.d.sync += self.valid_o.eq(1) + m.d.sync += self.busy.eq(0) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.baud_counter.eq(0) + + with m.Else(): + # m.d.sync += self.data_o.eq(Cat(self.rx_q, self.data_o[0:7])) + m.d.sync += self.data_o.eq(Cat(self.data_o[1:8], self.rx_q)) + m.d.sync += self.bit_index.eq(self.bit_index - 1) + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + + with m.Else(): + m.d.sync += self.baud_counter.eq(self.baud_counter - 1) + + return m diff --git a/src/manta/uart/transmit_bridge.py b/src/manta/uart/transmit_bridge.py new file mode 100644 index 0000000..3f1b640 --- /dev/null +++ b/src/manta/uart/transmit_bridge.py @@ -0,0 +1,87 @@ +from amaranth import * + + +class TransmitBridge(Elaboratable): + def __init__(self): + # Top-Level Ports + self.data_i = Signal(16) + self.rw_i = Signal() + self.valid_i = Signal() + + self.data_o = Signal(8, reset=0) + self.start_o = Signal(1) + self.done_i = Signal() + + # Internal Signals + self.buffer = Signal(16, reset=0) + self.count = Signal(4, reset=0) + self.busy = Signal(1, reset=0) + self.to_ascii_hex = Signal(8) + self.n = Signal(4) + + def elaborate(self, platform): + m = Module() + + m.d.comb += self.start_o.eq(self.busy) + + with m.If(~self.busy): + with m.If((self.valid_i) & (~self.rw_i)): + m.d.sync += self.busy.eq(1) + m.d.sync += self.buffer.eq(self.data_i) + + with m.Else(): + # uart_tx is transmitting a byte: + with m.If(self.done_i): + m.d.sync += self.count.eq(self.count + 1) + + # Message has been transmitted + with m.If(self.count > 5): + m.d.sync += self.count.eq(0) + + # Go back to idle, or transmit next message + with m.If((self.valid_i) & (~self.rw_i)): + m.d.sync += self.buffer.eq(self.data_i) + + with m.Else(): + m.d.sync += self.busy.eq(0) + + # define to_ascii_hex + with m.If(self.n < 10): + m.d.comb += self.to_ascii_hex.eq(self.n + 0x30) + with m.Else(): + m.d.comb += self.to_ascii_hex.eq(self.n + 0x41 - 10) + + # run the sequence + with m.If(self.count == 0): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("D")) + + with m.Elif(self.count == 1): + m.d.comb += self.n.eq(self.buffer[12:16]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 2): + m.d.comb += self.n.eq(self.buffer[8:12]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 3): + m.d.comb += self.n.eq(self.buffer[4:8]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 4): + m.d.comb += self.n.eq(self.buffer[0:4]) + m.d.comb += self.data_o.eq(self.to_ascii_hex) + + with m.Elif(self.count == 5): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("\r")) + + with m.Elif(self.count == 6): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(ord("\n")) + + with m.Else(): + m.d.comb += self.n.eq(0) + m.d.comb += self.data_o.eq(0) + + return m diff --git a/src/manta/uart/transmitter.py b/src/manta/uart/transmitter.py new file mode 100644 index 0000000..b67a1ab --- /dev/null +++ b/src/manta/uart/transmitter.py @@ -0,0 +1,52 @@ +from amaranth import * + + +class UARTTransmitter(Elaboratable): + def __init__(self, clocks_per_baud): + self.clocks_per_baud = clocks_per_baud + + # Top-Level Ports + self.data_i = Signal(8) + self.start_i = Signal() + self.done_o = Signal(reset=1) + + self.tx = Signal(reset=1) + + # Internal Signals + self.baud_counter = Signal(range(clocks_per_baud)) + self.buffer = Signal(9) + self.bit_index = Signal(4) + + def elaborate(self, platform): + m = Module() + + with m.If((self.start_i) & (self.done_o)): + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.done_o.eq(0) + m.d.sync += self.tx.eq(0) + + with m.Elif(~self.done_o): + m.d.sync += self.baud_counter.eq(self.baud_counter - 1) + m.d.sync += self.done_o.eq((self.baud_counter == 1) & (self.bit_index == 9)) + + # A baud period has elapsed + with m.If(self.baud_counter == 0): + m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + + # Clock out another bit if there are any left + with m.If(self.bit_index < 9): + m.d.sync += self.tx.eq(self.buffer.bit_select(self.bit_index, 1)) + m.d.sync += self.bit_index.eq(self.bit_index + 1) + + # Byte has been sent, send out next one or go to idle + with m.Else(): + with m.If(self.start_i): + m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) + m.d.sync += self.bit_index.eq(0) + m.d.sync += self.tx.eq(0) + + with m.Else(): + m.d.sync += self.done_o.eq(1) + return m diff --git a/src/manta/utils.py b/src/manta/utils.py index bb20271..3591165 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,8 +1,17 @@ from amaranth.sim import Simulator +from amaranth.lib import data, enum from math import ceil import os +class InternalBus(data.StructLayout): + """Describes the layout of Manta's internal bus, such that signals of + the appropriate dimension can be instantiated with Signal(InternalBus()).""" + + def __init__(self): + super().__init__({"addr": 16, "data": 16, "rw": 1, "valid": 1}) + + def words_to_value(data): """ Takes a list of integers, interprets them as 16-bit integers, and diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py index 89c3d4d..c65a184 100644 --- a/test/test_bridge_rx_sim.py +++ b/test/test_bridge_rx_sim.py @@ -1,9 +1,9 @@ from amaranth.sim import Simulator -from manta.uart import RecieveBridge +from manta.uart import ReceiveBridge from manta.utils import * -bridge_rx = RecieveBridge() +bridge_rx = ReceiveBridge() def verify_read_decoding(bytes, addr): From 487b11f1556be5e78a6b76ae019f7214d4ea8a3a Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 7 Jan 2024 22:35:15 -0800 Subject: [PATCH 24/89] complete refactor to InternalBus() --- src/manta/io_core.py | 32 +++++-------- src/manta/logic_analyzer/__init__.py | 37 ++++----------- src/manta/logic_analyzer/fsm.py | 14 ++---- src/manta/logic_analyzer/trigger_block.py | 14 ++---- src/manta/manta.py | 20 ++------ src/manta/memory_core.py | 57 +++++++---------------- src/manta/uart/__init__.py | 25 ++++------ src/manta/utils.py | 26 +++++------ test/test_logic_analyzer_sim.py | 16 +++---- 9 files changed, 77 insertions(+), 164 deletions(-) diff --git a/src/manta/io_core.py b/src/manta/io_core.py index c12096a..98ce631 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -87,16 +87,9 @@ class IOCore(Elaboratable): ) def define_signals(self): - # Bus Ports - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal() - self.valid_i = Signal() - - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal() - self.valid_o = Signal() + # Bus Input/Output + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) # Input Probes (and buffers) if "inputs" in self.config: @@ -187,10 +180,7 @@ class IOCore(Elaboratable): m = Module() # Shuffle bus transactions along - m.d.sync += self.addr_o.eq(self.addr_i) - m.d.sync += self.data_o.eq(self.data_i) - m.d.sync += self.rw_o.eq(self.rw_i) - m.d.sync += self.valid_o.eq(self.valid_i) + m.d.sync += self.bus_o.eq(self.bus_i) # Update buffers from probes with m.If(self.strobe): @@ -209,17 +199,17 @@ class IOCore(Elaboratable): m.d.sync += output_probe.eq(output_probe_buf) # Handle register reads and writes - with m.If((self.addr_i >= self.base_addr)): - with m.If((self.addr_o <= self.max_addr)): + with m.If((self.bus_i.addr >= self.base_addr)): + with m.If((self.bus_o.addr <= self.max_addr)): for entry in self.mmap.values(): for addr, signal in zip(entry["addrs"], entry["signals"]): - with m.If(self.rw_i): - with m.If(self.addr_i == addr): - m.d.sync += signal.eq(self.data_i) + with m.If(self.bus_i.rw): + with m.If(self.bus_i.addr == addr): + m.d.sync += signal.eq(self.bus_i.data) with m.Else(): - with m.If(self.addr_i == addr): - m.d.sync += self.data_o.eq(signal) + with m.If(self.bus_i.addr == addr): + m.d.sync += self.bus_o.data.eq(signal) return m diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index fcb27d9..6e38e54 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -36,17 +36,9 @@ class LogicAnalyzerCore(Elaboratable): self.config = config self.check_config(config) - # Bus Input - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal(1) - self.valid_i = Signal(1) - - # Bus Output - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal(1) - self.valid_o = Signal(1) + # Bus Input/Output + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) self.probes = [ Signal(width, name=name) for name, width in self.config["probes"].items() @@ -177,26 +169,15 @@ class LogicAnalyzerCore(Elaboratable): # Wire bus connections between internal modules m.d.comb += [ # Bus Connections - fsm.addr_i.eq(self.addr_i), - fsm.data_i.eq(self.data_i), - fsm.rw_i.eq(self.rw_i), - fsm.valid_i.eq(self.valid_i), - trig_blk.addr_i.eq(fsm.addr_o), - trig_blk.data_i.eq(fsm.data_o), - trig_blk.rw_i.eq(fsm.rw_o), - trig_blk.valid_i.eq(fsm.valid_o), - sample_mem.addr_i.eq(trig_blk.addr_o), - sample_mem.data_i.eq(trig_blk.data_o), - sample_mem.rw_i.eq(trig_blk.rw_o), - sample_mem.valid_i.eq(trig_blk.valid_o), - self.addr_o.eq(sample_mem.addr_o), - self.data_o.eq(sample_mem.data_o), - self.rw_o.eq(sample_mem.rw_o), - self.valid_o.eq(sample_mem.valid_o), + fsm.bus_i.eq(self.bus_i), + trig_blk.bus_i.eq(self.fsm.bus_o), + sample_mem.bus_i.eq(trig_blk.bus_o), + self.bus_o.eq(sample_mem.bus_o), + # Non-bus Connections fsm.trigger.eq(trig_blk.trig), sample_mem.user_addr.eq(fsm.r.write_pointer), - sample_mem.user_we.eq(fsm.write_enable), + sample_mem.user_we.eq(fsm.write_enable) ] return m diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index b2f0059..4d8583e 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -37,17 +37,9 @@ class LogicAnalyzerFSM(Elaboratable): self.r = IOCore(register_config, base_addr, interface) - # Bus Input - self.addr_i = self.r.addr_i - self.data_i = self.r.data_i - self.rw_i = self.r.rw_i - self.valid_i = self.r.valid_i - - # Bus Output - self.addr_o = self.r.addr_o - self.data_o = self.r.data_o - self.rw_o = self.r.rw_o - self.valid_o = self.r.valid_o + # Bus Input/Output + self.bus_i = self.r.bus_i + self.bus_o = self.r.bus_o def get_max_addr(self): return self.r.get_max_addr() diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 2b15530..0d0a0bd 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -18,17 +18,9 @@ class LogicAnalyzerTriggerBlock(Elaboratable): self.r = IOCore({"outputs": outputs}, base_addr, interface) - # Bus Input - self.addr_i = self.r.addr_i - self.data_i = self.r.data_i - self.rw_i = self.r.rw_i - self.valid_i = self.r.valid_i - - # Bus Output - self.addr_o = self.r.addr_o - self.data_o = self.r.data_o - self.rw_o = self.r.rw_o - self.valid_o = self.r.valid_o + # Bus Input/Output + self.bus_i = self.r.bus_i + self.bus_o = self.r.bus_o # Global trigger. High if any probe is triggered. self.trig = Signal(1) diff --git a/src/manta/manta.py b/src/manta/manta.py index 97f1b4c..63f902b 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -136,28 +136,16 @@ class Manta(Elaboratable): core_instances = list(self.cores.values()) first_core = core_instances[0] last_core = core_instances[-1] - m.d.comb += [ - first_core.addr_i.eq(self.interface.addr_o), - first_core.data_i.eq(self.interface.data_o), - first_core.rw_i.eq(self.interface.rw_o), - first_core.valid_i.eq(self.interface.valid_o), - self.interface.addr_i.eq(last_core.addr_o), - self.interface.data_i.eq(last_core.data_o), - self.interface.rw_i.eq(last_core.rw_o), - self.interface.valid_i.eq(last_core.valid_o), - ] + + m.d.comb += first_core.bus_i.eq(self.interface.bus_o) + m.d.comb += self.interface.bus_i.eq(last_core.bus_o) # Connect output of ith core to input of (i+1)th core for i in range(len(core_instances) - 1): ith_core = core_instances[i] i_plus_oneth_core = core_instances[i + 1] - m.d.comb += [ - i_plus_oneth_core.addr_i.eq(ith_core.addr_o), - i_plus_oneth_core.data_i.eq(ith_core.data_o), - i_plus_oneth_core.rw_i.eq(ith_core.rw_o), - i_plus_oneth_core.valid_i.eq(ith_core.valid_o), - ] + m.d.comb += i_plus_oneth_core.bus_i.eq(ith_core.bus_o) return m diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index cf4d9ae..e74e32d 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -47,23 +47,10 @@ class ReadOnlyMemoryCore(Elaboratable): raise ValueError("Width of memory core must be positive. ") def define_signals(self): - # Bus Input - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal(1) - self.valid_i = Signal(1) - - # Bus Pipelining - self.addr_pipe = [Signal(16) for _ in range(3)] - self.data_pipe = [Signal(16) for _ in range(3)] - self.rw_pipe = [Signal(1) for _ in range(3)] - self.valid_pipe = [Signal(1) for _ in range(3)] - - # Bus Output - self.addr_o = Signal(16, reset=0) - self.data_o = Signal(16, reset=0) - self.rw_o = Signal(1, reset=0) - self.valid_o = Signal(1, reset=0) + # Bus Input/Pipelining/Output + self.bus_i = Signal(InternalBus()) + self.bus_pipe = [Signal(InternalBus()) for _ in range(3)] + self.bus_o = Signal(InternalBus()) # User Port self.user_addr = Signal(range(self.depth)) @@ -71,22 +58,12 @@ class ReadOnlyMemoryCore(Elaboratable): self.user_we = Signal(1) def pipeline_bus(self, m): - # Pipelining - m.d.sync += self.addr_pipe[0].eq(self.addr_i) - m.d.sync += self.data_pipe[0].eq(self.data_i) - m.d.sync += self.rw_pipe[0].eq(self.rw_i) - m.d.sync += self.valid_pipe[0].eq(self.valid_i) + m.d.sync += self.bus_pipe[0].eq(self.bus_i) for i in range(1, 3): - m.d.sync += self.addr_pipe[i].eq(self.addr_pipe[i - 1]) - m.d.sync += self.data_pipe[i].eq(self.data_pipe[i - 1]) - m.d.sync += self.rw_pipe[i].eq(self.rw_pipe[i - 1]) - m.d.sync += self.valid_pipe[i].eq(self.valid_pipe[i - 1]) + m.d.sync += self.bus_pipe[i].eq(self.bus_pipe[i-1]) - m.d.sync += self.addr_o.eq(self.addr_pipe[2]) - m.d.sync += self.data_o.eq(self.data_pipe[2]) - m.d.sync += self.rw_o.eq(self.rw_pipe[2]) - m.d.sync += self.valid_o.eq(self.valid_pipe[2]) + m.d.sync += self.bus_o.eq(self.bus_pipe[2]) def define_mems(self): # ok there's three cases: @@ -122,21 +99,21 @@ class ReadOnlyMemoryCore(Elaboratable): # Throw BRAM operations into the front of the pipeline with m.If( - (self.valid_i) - & (~self.rw_i) - & (self.addr_i >= start_addr) - & (self.addr_i <= stop_addr) + (self.bus_i.valid) + & (~self.bus_i.rw) + & (self.bus_i.addr >= start_addr) + & (self.bus_i.addr <= stop_addr) ): - m.d.sync += read_port.addr.eq(self.addr_i - start_addr) + m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) # Pull BRAM reads from the back of the pipeline with m.If( - (self.valid_pipe[2]) - & (~self.rw_pipe[2]) - & (self.addr_pipe[2] >= start_addr) - & (self.addr_pipe[2] <= stop_addr) + (self.bus_pipe[2].valid) + & (~self.bus_pipe[2].rw) + & (self.bus_pipe[2].addr >= start_addr) + & (self.bus_pipe[2].addr <= stop_addr) ): - m.d.sync += self.data_o.eq(read_port.data) + m.d.sync += self.bus_o.data.eq(read_port.data) def handle_write_ports(self, m): # These are given to the user diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index 5f1556b..a6f5c19 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -225,15 +225,8 @@ class UARTInterface(Elaboratable): self.rx = Signal() self.tx = Signal() - self.addr_o = Signal(16) - self.data_o = Signal(16) - self.rw_o = Signal() - self.valid_o = Signal() - - self.addr_i = Signal(16) - self.data_i = Signal(16) - self.rw_i = Signal() - self.valid_i = Signal() + self.bus_o = Signal(InternalBus()) + self.bus_i = Signal(InternalBus()) def elaborate(self, platform): # fancy submoduling and such goes in here @@ -249,14 +242,14 @@ class UARTInterface(Elaboratable): uart_rx.rx.eq(self.rx), bridge_rx.data_i.eq(uart_rx.data_o), bridge_rx.valid_i.eq(uart_rx.valid_o), - self.data_o.eq(bridge_rx.data_o), - self.addr_o.eq(bridge_rx.addr_o), - self.rw_o.eq(bridge_rx.rw_o), - self.valid_o.eq(bridge_rx.valid_o), + self.bus_o.data.eq(bridge_rx.data_o), + self.bus_o.addr.eq(bridge_rx.addr_o), + self.bus_o.rw.eq(bridge_rx.rw_o), + self.bus_o.valid.eq(bridge_rx.valid_o), # Internal Bus -> UART TX - bridge_tx.data_i.eq(self.data_i), - bridge_tx.rw_i.eq(self.rw_i), - bridge_tx.valid_i.eq(self.valid_i), + bridge_tx.data_i.eq(self.bus_i.data), + bridge_tx.rw_i.eq(self.bus_i.rw), + bridge_tx.valid_i.eq(self.bus_i.valid), uart_tx.data_i.eq(bridge_tx.data_o), uart_tx.start_i.eq(bridge_tx.start_o), bridge_tx.done_i.eq(uart_tx.done_o), diff --git a/src/manta/utils.py b/src/manta/utils.py index 3591165..9773a57 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -83,20 +83,20 @@ def verify_register(module, addr, expected_data): """ # place read transaction on the bus - yield module.addr_i.eq(addr) - yield module.data_i.eq(0) - yield module.rw_i.eq(0) - yield module.valid_i.eq(1) + yield module.bus_i.addr.eq(addr) + yield module.bus_i.data.eq(0) + yield module.bus_i.rw.eq(0) + yield module.bus_i.valid.eq(1) yield - yield module.addr_i.eq(0) - yield module.valid_i.eq(0) + yield module.bus_i.addr.eq(0) + yield module.bus_i.valid.eq(0) # wait for output to be valid - while not (yield module.valid_o): + while not (yield module.bus_o.valid): yield # compare returned value with expected - data = yield (module.data_o) + data = yield (module.bus_o.data) if data != expected_data: raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") @@ -107,12 +107,12 @@ def write_register(module, addr, data): at `addr`. """ - yield module.addr_i.eq(addr) - yield module.data_i.eq(data) - yield module.rw_i.eq(1) - yield module.valid_i.eq(1) + yield module.bus_i.addr.eq(addr) + yield module.bus_i.data.eq(data) + yield module.bus_i.rw.eq(1) + yield module.bus_i.valid.eq(1) yield - yield module.valid_i.eq(0) + yield module.bus_i.valid.eq(0) yield diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index e69db0c..ebce934 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -16,19 +16,19 @@ la = LogicAnalyzerCore(config, base_addr=0, interface=None) def print_data_at_addr(addr): # place read transaction on the bus - yield la.addr_i.eq(addr) - yield la.data_i.eq(0) - yield la.rw_i.eq(0) - yield la.valid_i.eq(1) + yield la.bus_i.addr.eq(addr) + yield la.bus_i.data.eq(0) + yield la.bus_i.rw.eq(0) + yield la.bus_i.valid.eq(1) yield - yield la.addr_i.eq(0) - yield la.valid_i.eq(0) + yield la.bus_i.addr.eq(0) + yield la.bus_i.valid.eq(0) # wait for output to be valid - while not (yield la.valid_o): + while not (yield la.bus_o.valid): yield - print(f"addr: {hex(addr)} data: {hex((yield la.data_o))}") + print(f"addr: {hex(addr)} data: {hex((yield la.bus_o.data))}") def set_fsm_register(name, data): From c1c0330d86f4dea89951314dbd305cb08083763c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 11 Jan 2024 09:33:21 -0800 Subject: [PATCH 25/89] fix bug in USB PID/VID reporting --- src/manta/cli.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/manta/cli.py b/src/manta/cli.py index 7528cf8..961aa0d 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -66,7 +66,7 @@ def ports(): # sometimes macOS will enumerate non-serial devices as serial ports, # in which case the PID/VID/serial/location/etc are all None - pid = f"0x{port.vid:04X}" if port.pid is not None else "None" + pid = f"0x{port.pid:04X}" if port.pid is not None else "None" vid = f"0x{port.vid:04X}" if port.vid is not None else "None" print(f" -> pid: {pid}") From 4e44f7ac90bb60558bb19de4d5c9385065d0e228 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 11 Jan 2024 10:40:12 -0800 Subject: [PATCH 26/89] add version command to CLI --- src/manta/cli.py | 58 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 49 insertions(+), 9 deletions(-) diff --git a/src/manta/cli.py b/src/manta/cli.py index 961aa0d..21d9519 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -3,22 +3,59 @@ from warnings import warn from sys import argv from pkg_resources import get_distribution -version = "v" + get_distribution("manta").version logo = f""" -Manta {version} + . + .'; + ( ( + . `. `. + `.. .' ) + ; `; .'.--. + :' `.' (' + .;' : + ______:..._____ ./' + .-" "-.( +(`-.__ .-' .. .. `-. __......') + `: `-... .-' :* : :* : `-. ...-' :' + `-. `\"""' `--' `--' `""\"' .-' + `-. . .-. .--. `. .-' + `-. : .'. ( `--_____--' ) `. ; .-' + `--..`.`.` `--... ..--' .'.'.' ..--' + `---... ````''' ...---' + `------........------' -Usage: - gen [config_file] [verilog_file] Generate a verilog file specifying the Manta module from a given configuration file, and save to the provided path - capture [config_file] [la_core_name] [vcd_file] [verilog_file] Start a capture on the specified core, and save the results to a .vcd or .v file at the provided path(s) - ports List all available serial ports - help Display this help menu + +\033[34;49;1m\033[34;49;3m Manta Version {get_distribution("manta").version} \033[00m +\033[34;49;1m\033[34;49;3m An In-Situ Debugging Tool for Programmable Hardware \033[00m +\033[34;49;1m\033[34;49;3m https://github.com/fischermoseley/manta \033[00m """ -def help(): - print(logo) +usage = """ +Usage: + gen [config_file] [verilog_file] + Generate a verilog file specifying the Manta module from a given + configuration file, and save to the provided path. + capture [config_file] [la_core_name] [vcd_file] [verilog_file] + Start a capture on the specified core, and save the results to a .vcd + or .v file at the provided path(s). + + ports + List all available serial ports. + + help + Display this help menu. + + version + Display the currently installed version.""" + + +def help(): + print(usage) + +def version(): + print(logo) def wrong_args(): print('Wrong number of arguments, run "manta help" for usage.') @@ -108,6 +145,9 @@ def main(): elif argv[1] == "ports": ports() + elif argv[1] == "version": + version() + else: wrong_args() From 2b95fea496fff563d910df54903d37951afa107c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 13 Jan 2024 15:05:45 -0800 Subject: [PATCH 27/89] update docs, bump required python to 3.8 --- doc/alternatives.md | 61 ++++++++++++++++++++++++ doc/{how_it_works.md => architecture.md} | 46 +++++++++++++++++- doc/ethernet_interface.md | 1 - doc/getting_started.md | 2 +- doc/index.md | 16 ++++--- doc/installation.md | 50 +++++++++++-------- doc/io_core.md | 14 +----- doc/logic_analyzer_core.md | 37 ++++---------- doc/memory_core.md | 25 +--------- doc/repository_structure.md | 1 - doc/uart_interface.md | 2 +- mkdocs.yml | 9 ++-- pyproject.toml | 2 +- 13 files changed, 163 insertions(+), 103 deletions(-) create mode 100644 doc/alternatives.md rename doc/{how_it_works.md => architecture.md} (65%) diff --git a/doc/alternatives.md b/doc/alternatives.md new file mode 100644 index 0000000..e7dcd11 --- /dev/null +++ b/doc/alternatives.md @@ -0,0 +1,61 @@ +There's quite a few FPGA debugging tools out there, and it may happen that your needs are better met by another tool. This section aims to provide a list of alternatives, in hopes that you're able to be confident in your debugging flow. + +## Open Source Tools + +### LiteScope + +An embedded logic analyzer written in Migen, primarily for use in LiteX SoC designs. Also includes IO peek and poke, as well as UART, Ethernet, and PCIe interfaces with a host machine. Includes VCD, Sigrok, CSV, and Python data export. + +- [Source Code](https://github.com/enjoy-digital/litescope) +- [Documentation](https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC) + +### ZipCPU Debugger + +A set of embedded debugging modules written by Dan Gisselquist of ZipCPU fame. Communication between the host and FPGA is accomplished with UART, and control of the debugger is performed with a C++ API on the host. A wishbone interface is provided on the FPGA side to connect to other Wishbone-based debugging tools that can provide control of user registers, block RAM, and an embedded logic analyzer. Supports dumping of signals to a VCD file. + +- [Source Code](https://github.com/ZipCPU/dbgbus) +- [Documentation](https://zipcpu.com/topics.html), under the _How to Debug an FPGA_ section. + +## Commercial Tools + +### Xilinx Integrated Logic Analzyer + +An embedded logic analyzer for Xilinx FPGAs, provided as part of the Xilinx Vivado development suite. Communication between the host and FPGA is accomplished with JTAG, typically running over a USB cable to the device. Includes an integrated waveform viewer, and VCD and CSV export. Also supports a JTAG-to-AXI mode, which integrates well with Xilinx IP, which uses primarily AXI. Also integrates with the ChipScoPy API, which allows for Python control of the ILA on Versal devices. The ILA was previously known as ChipScope in earlier versions of Vivado. + +- [ILA Documentation](https://docs.xilinx.com/v/u/en-US/pg172-ila) +- [ILA User's Guide](https://docs.xilinx.com/r/en-US/ug936-vivado-tutorial-programming-debugging/Using-the-Vivado-Logic-Analyzer-to-Debug-Hardware) +- [ChipScoPy API](https://github.com/Xilinx/chipscopy) + + +### Xilinx Virtual IO + +A tool for reading and writing to individual registers on the FPGA, provided as part of the Xilinx Vivado development suite. Just like the ILA, communication between the host and FPGA is done over JTAG. Control over the registers is done through the Vivado GUI or through the Tcl interpreter. In the case of Versal devices, the ChipScoPy API can also control the registers. + +- [Virtual IO Documentation](https://docs.xilinx.com/v/u/en-US/pg159-vio) +- [ChipScoPy API](https://github.com/Xilinx/chipscopy) + +### Intel Signal Tap + +An embedded logic analyzer for Intel/Altera FPGAs, provided as part of the Quartus development suite. Communication between the host and FPGA is accomplished with JTAG, and a programmable interface is provided via Tcl. Signal Tap is notable for providing a significant amount of configurability in the trigger conditions, and provides a small scripting language called _Trigger Flow_ that allows users to define triggers as state machines. Signal Tap also allows for _Simulation-Aware nodes_, which allows for running simulations with data captured from the real world. At the time of writing, this feature is only available in the most recent and full-featured version of the Quartus suite, Quartus Prime Pro Edition 22.4. + +- [Documentation](https://www.intel.com/content/www/us/en/docs/programmable/683552/18-1/design-debugging-with-the-logic-analyzer-69524.html) + + +### Intel In-System Sources and Probes + +A tool for reading and writing to individual registers on the FPGA, provided for Intel/Altera FPGAs as part of the Quartus development suite. Just like Signal Tap, communication between the host and FPGA is accomplished with JTAG. + +- [Documentation](https://www.intel.com/content/www/us/en/docs/programmable/683552/18-1/design-debugging-using-in-system-sources-45607.html) + +### Lattice Reveal + +An embedded logic analyzer for Lattice FPGAs, provided as part of the Diamond development suite. Communication between the host and FPGA is accomplished with JTAG. Reveal is notable for providing a significant amount of configurability in the trigger conditions, and supports trigger conditions formed with a mix of combinational and sequential logic. Reveal also provides special support for Wishbone buses, and for controlling SERDES modules on ECP5 devices. + +- [Documentation](https://www.latticesemi.com/~/media/328D471BF2C74EB1907832FAA6FB344B.ashx) + +### Opal Kelly FrontPanel SDK + +Unlike other entries in this list, Opal Kelly's FrontPanel SDK is not marketed as a debugger (although it can be used as such). Instead, it's designed to provide a host computer with a real time interface to FGPA signals, and present them on a graphical “front panel". These front panels exist as a GUI window on the host, and contain buttons, knobs, and indicators, much like a LabVIEW virtual instrument. Communication between the host and FPGA is accomplished with either USB or PCIe. Bindings for hosts running Windows, macOS, and Linux are provided, and target C, C++, C#, Python, Java, Ruby, and MATLAB. The FrontPanel SDK differs from other debuggers in that it provides a skeleton module into which the user logic is instantiated, instead of being instantiated inside the user's logic. + +- [Documentation](https://docs.opalkelly.com/fpsdk/) +- [User's Guide](https://assets00.opalkelly.com/library/FrontPanel-UM.pdf) \ No newline at end of file diff --git a/doc/how_it_works.md b/doc/architecture.md similarity index 65% rename from doc/how_it_works.md rename to doc/architecture.md index 0311b89..be7f57b 100644 --- a/doc/how_it_works.md +++ b/doc/architecture.md @@ -2,7 +2,7 @@ The whole system looks like the following: -![](assets/architecture.drawio.svg){:style="width:80%"} +![](assets/system_architecture.drawio.svg){:style="width:80%"} Manta is operated via its Python API, which communicates with the connected FPGA over an interface API like `pySerial` or `Scapy`. These abstract away the OS device drivers, which function differently depending on the host machine's platform. The OS device drivers ultimately send out bytes to the FPGA, across either a USB or Ethernet cable. @@ -56,4 +56,46 @@ An example of some bus traffic is provided below: | 5 | FPGA → Host: RBEEF(CR)(LF) | Read 0xBEEF from 0xF00D | | 6 | Host → FPGA: W12340000(CR)(LF) | Write 0x0000 to 0x1234 | -When UART is used, these bytes are transmitted directly across the wire, but when Ethernet is used, they're packed into the packet's payload field. \ No newline at end of file +When UART is used, these bytes are transmitted directly across the wire, but when Ethernet is used, they're packed into the packet's payload field. + +# Cores + +## IO Core + +This is done with the architecture shown below: + +![](assets/io_core_architecture.drawio.svg){:style="width:49%"} + +Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple. + +Whatever the number of registers required, these are read from and written to by the host machine - but the connection to the user's logic isn't direct. The value of each probe is buffered, and only once the `strobe` register has been set to one will the buffers update. When this happens, output probes provide new values to user logic, and new values for input probes are read from user logic. This provides a convenient place to perform clock domain crossing, and also mitigates the possibility of an inconsistent system state. This is explained in more detail in Chapter 3.6 of the [original thesis](thesis.pdf). + +## Logic Analyzer +The Logic Analyzer Core's implementation on the FPGA consists of three primary components: + +![](assets/logic_analyzer_architecture.drawio.svg){style="width:85%"} + +- The _Finite State Machine (FSM)_, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains. +- The _Trigger Block_, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the $N$-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's `trig` input. +- The _Sample Memory_, which stores the states of the probes during a capture. This is implemented as a dual-port, dual-clock block memory, with the bus on one port and the probes on the other. The probe-connected port only writes to the memory, with the address and enable pins managed by the FSM. CDC is performed in the block RAM primitive itself. + + +## Memory Core + +Each Memory core is actually a set of 16-bit wide BRAMs with their ports concatenated together, with any spare bits masked off. Here's a diagram: + +![](assets/memory_architecture.drawio.svg) + + +Since each $n$-bit wide block memory is actually $ceil(n/16)$ BRAMs under the hood, addressing the BRAMs correctly from Manta's internal bus is important. BRAMs are organized such that each 16-bit slice of a $N$-bit word in the Block Memory core are placed next to each other in bus address space. For instance, a 34-bit wide block memory would exist on Manta's internal bus as: + +| Bus Address Space | BRAM Address Space | +| ----------- | -------------------- | +| BASE_ADDR + 0 | address 0, bits 0-15 | +| BASE_ADDR + 1 | address 0, bits 16-31| +| BASE_ADDR + 2 | address 0, bits 32-33| +| BASE_ADDR + 3 | address 1, bits 0-15 | +| BASE_ADDR + 4 | address 1, bits 16-31| +| BASE_ADDR + 5 | address 1, bits 32-33| + +...and so on. diff --git a/doc/ethernet_interface.md b/doc/ethernet_interface.md index 57d0c84..416c31b 100644 --- a/doc/ethernet_interface.md +++ b/doc/ethernet_interface.md @@ -11,6 +11,5 @@ Manta's bus clock must be equivalent to the PHY's reference clock if Ethernet is This MAC allows for the usage of packets with the structure shown below. The bus transaction being communicated is placed at the beginning of the packet's payload field, which IEEE 802.3 allows to vary in length from 46 to 1500 bytes. The 46-byte lower limit requires 41 bytes of zero padding to be added to the five bytes used to specify a bus transaction, and only one bus transactions is specified in each Ethernet frame. This abundance of unused space results in all packets being the same length, whether the packet contains a read request, write request, or read response. Packets containing write requests elicit no response from the FPGA, just as write requests delivered over UART produce no response. -![](assets/ethernet_packet.png) These packets are addressed directly to the host's MAC address, which is obtained during code autogeneration. These packets also use a fixed Ethertype of `0x88B5`, which is specially reserved for "public use and for prototype and vendor-specific protocol development" in IEEE 802.1. This was done to create an Ethernet II frame instead of a legacy 802.3 frame, without having to implement a higher level protocol like TCP or UDP to safely use a fixed Ethertype. This allows the MAC to use modern Ethernet II frames safely, but save FPGA resources. \ No newline at end of file diff --git a/doc/getting_started.md b/doc/getting_started.md index 2913ef3..2de3e05 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -1,7 +1,7 @@ ## Overview -To use Manta, you'll need a host machine with a FPGA board connected over UART or Ethernet. You'll then: +To use Manta, you'll need a host machine with a FPGA board connected over UART, or a FPGA board connected to the same network via Ethernet. You'll then: - _Specify a set of debug cores you wish to include in your design._ This is done by writing a configuration file, typically called `manta.yaml`. Specifying files in JSON is also supported, as long as the hierarchy in the file is equivalent. Just make sure that your YAML files end in `.yaml` or `.yml`, and that JSON files end in `.json`. - _Invoke Manta to generate Verilog from the configuration provided._ This is done by running `manta gen [config_file] [verilog_file]` at the command line, which generates a Verilog file (typically named `manta.v`) from the provided configuration file. This Verilog file contains a definition for a Verilog module named `manta`, and all its constituent modules. diff --git a/doc/index.md b/doc/index.md index b3c88f9..41bae4d 100644 --- a/doc/index.md +++ b/doc/index.md @@ -2,7 +2,13 @@ ## Manta: An In-Situ Debugging Tool for Programmable Hardware -Manta is a tool for getting information into and out of FPGAs over UART or Ethernet. It's primarily intended for debugging and experimentation, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It works by letting you configure a series of cores, which live as digital logic on the FPGA and are represented with vendor-agnostic Verilog-2001. The information and behavior of these cores are accessible to the host machine, which presents a Python API to the user. Manta includes the following cores, any number and combination of which may be used at once: +Manta is a tool for moving data between a host machine and a FPGA over UART or Ethernet. It's primarily intended for debugging and rapid prototyping of FPGA designs, but it's robust enough to be used as a simple, reliable transport layer. + +Manta works by generating a number of cores that are instantiated in the FPGA design. These allow for a variety of functions, such as reading and writing to registers and memory, or capturing data with a logic analyzer. These cores are operated by the connected host machine through either the Manta CLI, or a simple Python API. + +Manta is written in Amaranth HDL, and the generated designs may be used natively in other Amaranth designs, or exported to vendor-agnostic Verilog-2001. All dependencies are cross-platform, so Manta can be used on any machine that has at least Python 3.8 or newer installed. + +Manta's capabilities are best reflected in its cores, for which a brief description of each is provided below: ### __Logic Analyzer Core__ @@ -28,9 +34,9 @@ You may find this core useful for: * _Making dashboards_ - you'd like to get some telemetry out of your existing FPGA design and display it nicely, but you don't want to implement an interface, design a packetization scheme, and write a library. -### __Block Memory Cores__ +### __Memory Cores__ -_More details available on the [full documentation page](./block_memory_core.md)._ +_More details available on the [full documentation page](./memory_core.md)._ This core creates a two-port block memory on the FPGA, and gives one port to the host machine, and the other to your logic on the FPGA. The width and depth of this block memory is configurable, allowing large chunks of arbitrarily-sized data to be shuffled onto and off of the FPGA by the host machine, via the Python API. This lets you establish a transport layer between the host and FPGA, that treats the data as exactly how it exists on the FPGA. @@ -40,10 +46,6 @@ You may find this core useful for: * _Hand-tuning ROMs_ - you're designing a digital filter for a DSP project and would like to tune it in real-time, or you're developing a soft processor and want to upload program code without rebuilding a bitstream. - -## Dependencies -Manta is written in Python, and generates Verilog-2001 HDL. It's cross-platform, and its only strict dependency is pyYAML. However, [pySerial](https://github.com/pyserial/pyserial) is required for using UART, [scapy](https://github.com/secdev/scapy) is required for using Ethernet, and [pyvcd](https://github.com/westerndigitalcorporation/pyvcd) is required if you want to export a waveform from the Logic Analyzer core to a `.vcd` file. - ## About Manta and its source code are released under a [GPLv3 license](https://github.com/fischermoseley/manta/blob/main/LICENSE.txt), and it was originally developed as part of my [Master's Thesis at MIT](https://hdl.handle.net/1721.1/151223) in 2023, done under the supervision of [Dr. Joe Steinmeyer](https://www.jodalyst.com/). The thesis itself is copyrighted by Fischer Moseley (me!), but feel free to use the following Bibtex if you'd like to cite it: diff --git a/doc/installation.md b/doc/installation.md index 189552e..9141181 100644 --- a/doc/installation.md +++ b/doc/installation.md @@ -1,32 +1,42 @@ -## Dependencies -Manta requires the following dependencies: +Before installing, make sure to upgrade your `pip` to the latest version: -- pyYAML, which is used for parsing configuration files written in YAML. -- pySerial, used for communicating with the FPGA over UART. -- Scapy, used for communicating with FPGA over Ethernet. -- pyVCD, used for writing waveforms captured by the Logic Analyzer Core to standard Value Change Dump (VCD) files. +``` +pip install --upgrade pip +``` -All of these dependencies are technically optional. If you're comfortable writing configuration files in JSON, then you don't need pyYAML. If you're using UART exclusively in your project, then you won't need Scapy. That said, Manta will try to install (or use an existing copy of) pyYAML, pySerial, and pyVCD during its own installation to cover all use cases. - -## Installation +## Latest Version You can install the latest version of Manta directly from source with: ``` -pip install git+https://github.com/fischermoseley/manta.git +pip install --upgrade git+https://github.com/fischermoseley/manta.git ``` -!!! warning "Note for Ubuntu users:" +## Editable Development Install +If you're working on the source, you might want an editable installation with some extra dependencies used for development: - If you're on Ubuntu, you'll probably need to run this first to dodge - a bug in the current version of Python's `setuptools`: - ``` - export DEB_PYTHON_INSTALL_LAYOUT=deb_system - ``` - Do this before installing Manta. If you've already installed it, just - uninstall, run the above command, and then reinstall. +``` +git clone https://github.com/fischermoseley/manta.git +cd manta +pip install -e ".[dev]" +``` + +## Adding Manta to Path (Recommended) It's recommended to place Manta on your system path by adding `export PATH="~/.local/bin:$PATH"` to your `.bashrc` or `.zshrc`. This isn't strictly necessary, but it means that Manta (and any other executable Python modules) can be run as just `manta` on the command line, instead of `python3 -m manta`. If you're on Windows, this location will likely be different. -Feel free to install Manta within a virtual environment (venv, Conda, and so on) if you'd like! +Later Manta will be availabe on the PyPI lists, and you'll be able to just `pip install mantaray`, but that's not configured quite yet. -Later Manta will be availabe on the PyPI lists, and you'll be able to just `pip install mantaray`, but that's not configured quite yet. \ No newline at end of file +## Dependencies +Manta requires the following dependencies: + +- Amaranth HDL, which comes with it's own built-in copy of Yosys. +- pyYAML, which is used for parsing configuration files written in YAML. +- pySerial, used for communicating with the FPGA over UART. +- pyVCD, used for writing waveforms captured by the Logic Analyzer Core to standard Value Change Dump (VCD) files. + +As well as these dependencies for development, which are installed with the `[dev]` argument: + +- Pytest, for testing. +- Black, used for formatting the Python source. +- mkdocs-material, for generating the documentation site. +- amaranth_boards, for building designs for hardware-in-the-loop testing done by the CI. diff --git a/doc/io_core.md b/doc/io_core.md index ca777d1..ba86a53 100644 --- a/doc/io_core.md +++ b/doc/io_core.md @@ -78,20 +78,10 @@ True 5 ``` -## Caveats +## Limitations While the IO core performs a very, very simple task, it carries a few caveats. -- First, __it's not instantaneous__. Manta has designed to be as fast as possible, but setting and querying registers relies on passing messages between the host and FPGA, which is slow relative to FPGA clock speeds! If you're trying to set values in your design with cycle-accurate timing, this will not do that for you. However, the [Logic Analyzer's playback feature](./logic_analyzer.md#playback) might be helpful. +- First, __it's not instantaneous__. Manta has designed to be as fast as possible, but setting and querying registers relies on passing messages between the host and FPGA, which is slow relative to FPGA clock speeds! If you're trying to set values in your design with cycle-accurate timing, this will not do that for you. However, the [Logic Analyzer's playback feature](./logic_analyzer_core.md#playback) might be helpful. - Second, __the API methods are blocking__, and will wait for a response from the FPGA before resuming program execution. Depending on your application, you might want to run your IO Core operations in a seperate thread, but you can also decrease the execution time by using a faster interface between the host and FPGA. This means using a higher UART baudrate, or using Ethernet. - -## How It Works - -This is done with the architecture shown below: - -![](assets/io_core_architecture.drawio.svg){:style="width:49%"} - -Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple. - -Whatever the number of registers required, these are read from and written to by the host machine - but the connection to the user's logic isn't direct. The value of each probe is buffered, and only once the `strobe` register has been set to one will the buffers update. When this happens, output probes provide new values to user logic, and new values for input probes are read from user logic. This provides a convenient place to perform clock domain crossing, and also mitigates the possibility of an inconsistent system state. This is explained in more detail in Chapter 3.6 of the [original thesis](thesis.pdf). \ No newline at end of file diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index 5f245c1..bcf0a4b 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -101,50 +101,29 @@ manta capture [config file] [LA core] [path] [path] If the file `manta.yaml` contained the configuration above, and you wanted to export a .vcd and .mem of the captured data, you would execute: ```bash -manta capture manta.yaml my_logic_analyzer capture.vcd capture.mem +manta capture manta.yaml my_logic_analyzer capture.vcd capture.v ``` -This will reset your logic analyzer, configure it with the triggers specified in `manta.yaml`, and perform a capture. The resulting .vcd file can be opened in a waveform viewer like [GTKWave](https://gtkwave.sourceforge.net/), and the `.mem` file can be used for playback as described in the following section. - -Manta will stuff the capture data into as many files as you provide it on the command line, so if you don't want the `.mem` or `.vcd` file, just omit their paths. +This will reset your logic analyzer, configure it with the triggers specified in `manta.yaml`, and perform a capture. The resulting .vcd file can be opened in a waveform viewer like [GTKWave](https://gtkwave.sourceforge.net/). Manta will stuff the capture data into as many files as you provide it on the command line, so if you don't want the `.mem` or `.vcd` file, just omit their paths. ### Playback -The Logic Analyzer Core has the ability to capture a recording of a set of signals on the FPGA, and then 'play them back' inside a Verilog simulation. This requires generating a small Verilog module that loads a capture from a `.mem` file, which can be done by: - -``` -manta playback [config_file_path] [core_name] [verilog_file_path] -``` +Manta has the ability to generate a module that _plays back_ a set of data captured from a Logic Analyzer core. This module has a set of outputs matching the inputs of the Logic Analyzer, which when enabled, will take the exact values captured by the logic analyzer. This module is synthesizable, and can either be used in simulation or included in the FPGA design. This is handy for If the file `manta.yaml` contained the configuration above, then running: - -``` -manta playback manta.yaml my_logic_analyzer sim/playback.v +```bash +manta capture manta.yaml my_logic_analyzer capture.v ``` -Generates a Verilog wrapper at `sim/playback.v`, which can then be instantiated in the testbench in which it is needed. An example instantiation is provided at the top of the output verilog, so a simple copy-paste into the testbench is all that's necessary to use the module. This module is also fully synthesizable, so you can use it in designs that live on the FPGA too, if so you so wish. +Generates a Verilog module at `capture.v` which can then be instantiated in the testbench or FPGA design in which it is needed. An example instantiation is provided at the top of the output verilog, so a simple copy-paste into the testbench is all that's necessary to use the module. This is useful for two situations in particular: - _Input Verification._ Designs will often work in simulation, but fail in hardware. In the absence of any build errors, this usually means that the inputs being applied to the logic in simulation don't accurately represent those being applied to the logic in the real world. Playing signals back in simulation allows for easy comparison between simulated and measured input, and provides a nice way to check that the logic downstream is behaves properly. -- _Sparse Sampling_ Sometimes designs will have a small number of inputs, but a huge amount of internal state. In situations like these, it may be more effecient to sample the inputs and simulate the logic, instead of directly sampling the state. For instance, debugging a misbehaving branch predictor in a CPU can be done by recording activity on the address and data busses and playing them back in simulation - which would use less BRAM than sampling the entire pattern history table. +- _Sparse Sampling_ Sometimes designs will have a small number of inputs, but a huge amount of internal state. In situations like these, it may be more efficient to sample the inputs and simulate the logic, instead of directly sampling the state. For instance, debugging a misbehaving branch predictor in a CPU can be done by recording activity on the address and data busses and playing them back in simulation - which would use less FPGA resources than sampling the entire pattern history table. ## Python API -The Logic Analyzer core functionality is stored in the `Manta.LogicAnalyzerCore` class in [src/manta/la_core/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/la_core/__init__.py). - -At present, this class contains methods used really only for capturing data, and exporting `.vcd` and `.mem` files. It'd be super handy to expose the data from the logic analyzer core in a Pythonic way - which is why the feature is on the [roadmap](https://github.com/fischermoseley/manta/milestones)! - -## How It Works -The Logic Analyzer Core's implementation on the FPGA consists of three primary components: - -![](assets/logic_analyzer_architecture.drawio.svg){style="width:85%"} - -- The _Finite State Machine (FSM)_, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains. -- The _Trigger Block_, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the $N$-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's `trig` input. -- The _Sample Memory_, which stores the states of the probes during a capture. This is implemented as a dual-port, dual-clock block memory, with the bus on one port and the probes on the other. The probe-connected port only writes to the memory, with the address and enable pins managed by the FSM. CDC is performed in the block RAM primitive itself. -\end{itemize} - - +The Logic Analyzer core functionality is stored in the `Manta.LogicAnalyzerCore` class in [src/manta/la_core/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/la_core/__init__.py). This class contains methods for capturing data, and exporting `.vcd` and `.v` files. diff --git a/doc/memory_core.md b/doc/memory_core.md index 2aa4749..7189648 100644 --- a/doc/memory_core.md +++ b/doc/memory_core.md @@ -64,32 +64,9 @@ foo = m.my_block_memory.read(addrs) A Block Memory core is used in the [video_sprite](https://github.com/fischermoseley/manta/blob/main/examples/nexys_a7/video_sprite) example. This uses the core to store a 128x128 image sprite in 12-bit color, and outputs it to a VGA display at 1024x768. The sprite contents can be filled with an arbitrary image using the [send_image.py](https://github.com/fischermoseley/manta/blob/main/examples/nexys_a7/video_sprite/send_image.py) python script. -## Under the Hood - -Each Block Memory core is actually a set of 16-bit wide BRAMs with their ports concatenated together, with any spare bits masked off. Here's a diagram: - -![](assets/memory_architecture.drawio.svg) - -This has one major consequence: if the core doesn't have a width that's an exact multiple of 16, synthesis engines (Vivado in particular) will throw some warnings as they optimize out the unused bits. This is expected behavior, and while the warnings are a little annoying, not having to manually deal with the unused bits simplifies the implementation immensely. No Python is needed to generate the core, and it'll configure itself just based on Verilog parameters. This turns the block memory core from a complicated conditionally-instantiated beast to a simple ~_100 line_ [Verilog file](https://github.com/fischermoseley/manta/blob/main/src/manta/block_memory.v). - -### Address Assignment - -Since each $n$-bit wide block memory is actually $ceil(n/16)$ BRAMs under the hood, addressing the BRAMs correctly from Manta's internal bus is important. BRAMs are organized such that each 16-bit slice of a $N$-bit word in the Block Memory core are placed next to each other in bus address space. For instance, a 34-bit wide block memory would exist on Manta's internal bus as: - -| Bus Address Space | BRAM Address Space | -| ----------- | -------------------- | -| BASE_ADDR + 0 | address 0, bits 0-15 | -| BASE_ADDR + 1 | address 0, bits 16-31| -| BASE_ADDR + 2 | address 0, bits 32-33| -| BASE_ADDR + 3 | address 1, bits 0-15 | -| BASE_ADDR + 4 | address 1, bits 16-31| -| BASE_ADDR + 5 | address 1, bits 32-33| - -...and so on. - ### Synchronicity -Since Manta's [data bus](../system_architecture) is only 16-bits wide, it's only possible to manipulate the BRAM core in 16-bit increments. This means that if you have a BRAM that's ≤16 bits wide, you'll only need to issue a single bus transaction to read/write one entry in the BRAM. However, if you have a BRAM that's ≥16 bits wide, you'll need to issue a bus transaction to update each 16-bit slice of it. For instance, updating a single entry in a 33-bit wide BRAM would require sending 3 messages to the FPGA: one for bits 1-16, another for bits 17-32, and one for bit 33. If your application expects each BRAM entry to update instantaneously, this could be problematic. +Since Manta's [data bus](architecture.md#data-bus) is only 16-bits wide, it's only possible to manipulate the BRAM core in 16-bit increments. This means that if you have a BRAM that's ≤16 bits wide, you'll only need to issue a single bus transaction to read/write one entry in the BRAM. However, if you have a BRAM that's ≥16 bits wide, you'll need to issue a bus transaction to update each 16-bit slice of it. For instance, updating a single entry in a 33-bit wide BRAM would require sending 3 messages to the FPGA: one for bits 1-16, another for bits 17-32, and one for bit 33. If your application expects each BRAM entry to update instantaneously, this could be problematic. There's a few different ways to solve this - you could use an IO core to signal when a BRAM's contents or valid - or you could ping-pong between two BRAMs while one is being modified. The choice is yours, and Manta makes no attempt to presribe any particular approach. diff --git a/doc/repository_structure.md b/doc/repository_structure.md index 8b9e967..9652d74 100644 --- a/doc/repository_structure.md +++ b/doc/repository_structure.md @@ -6,7 +6,6 @@ - `.github/` also contains some GitHub Actions configuration for automatically running the SystemVerilog testbenches and building the examples, in addition to automatically rebuilding the site. ## Tools Used -- [Icarus Verilog](https://github.com/steveicarus/iverilog) is used for functional simulation. - The [YosysHQ](https://github.com/YosysHQ) tools and [Vivado](https://www.xilinx.com/products/design-tools/vivado.html) are used for building bitstreams. - [Wavedrom](https://wavedrom.com/) is used for for waveform diagrams, and [draw.io](https://app.diagrams.net/) for block diagrams - [GitHub Pages](https://pages.github.com/) is used to serve the documentation site, which is built with [Material for MkDocs](https://squidfunk.github.io/mkdocs-material/). diff --git a/doc/uart_interface.md b/doc/uart_interface.md index 0ad3ca8..847f52b 100644 --- a/doc/uart_interface.md +++ b/doc/uart_interface.md @@ -1,6 +1,6 @@ ## Overview -Manta needs an interface to pass data between the host machine and FPGA, and UART is a convenient option. When configured to use UART, Manta will shuffle data back and forth using generic 8N1 serial with no flow control. This happens through a series of read and write transactions, which are specified using a messaging format described [here](../how_it_works/#message-format). +Manta needs an interface to pass data between the host machine and FPGA, and UART is a convenient option. When configured to use UART, Manta will shuffle data back and forth using generic 8N1 serial with no flow control. This happens through a series of read and write transactions, which are specified using a messaging format described [here](architecture.md#message-format). ## Configuration diff --git a/mkdocs.yml b/mkdocs.yml index f027bdc..ca1d1d0 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -57,14 +57,15 @@ markdown_extensions: nav: - Home: index.md - Installation: installation.md - - Reference: - - Getting Started: getting_started.md + - Getting Started: getting_started.md + - Alternatives: alternatives.md + - Architecture: architecture.md + - Usage: - IO Core: io_core.md - Logic Analyzer Core: logic_analyzer_core.md - Memory Core: memory_core.md - - UART Interace: uart_interface.md + - UART Interface: uart_interface.md - Ethernet Interface: ethernet_interface.md - For Developers: - Repository Structure: repository_structure.md - - How It Works: how_it_works.md - Roadmap: https://github.com/fischermoseley/manta/milestones diff --git a/pyproject.toml b/pyproject.toml index d8ceffc..0b798de 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -13,7 +13,7 @@ dependencies = [ "pyvcd", ] -requires-python = ">=3.7" +requires-python = ">=3.8" [project.optional-dependencies] dev = [ From 970499d137d232090f454f6f3dac725fa5605c9f Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 13 Jan 2024 15:52:06 -0800 Subject: [PATCH 28/89] remove ANSI escape codes, they don't work in command prompt --- src/manta/cli.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/manta/cli.py b/src/manta/cli.py index 21d9519..cb79be3 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -25,9 +25,9 @@ logo = f""" `------........------' -\033[34;49;1m\033[34;49;3m Manta Version {get_distribution("manta").version} \033[00m -\033[34;49;1m\033[34;49;3m An In-Situ Debugging Tool for Programmable Hardware \033[00m -\033[34;49;1m\033[34;49;3m https://github.com/fischermoseley/manta \033[00m +Manta - An In-Situ Debugging Tool for Programmable Hardware +Version {get_distribution("manta").version} +https://github.com/fischermoseley/manta """ From 1528f569ef95864538bab9eeea8b59b68ce5df93 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 14 Jan 2024 12:51:52 -0800 Subject: [PATCH 29/89] update submodule usage, tidy logic analyzer config check --- src/manta/cli.py | 2 + src/manta/logic_analyzer/__init__.py | 159 ++++++++++++---------- src/manta/logic_analyzer/fsm.py | 5 +- src/manta/logic_analyzer/playback.py | 2 +- src/manta/logic_analyzer/trigger_block.py | 7 +- src/manta/manta.py | 2 +- src/manta/memory_core.py | 2 +- src/manta/uart/__init__.py | 8 +- test/test_io_core_hw.py | 22 +-- test/test_logic_analyzer_hw.py | 21 ++- test/test_mem_core_hw.py | 26 ++-- 11 files changed, 136 insertions(+), 120 deletions(-) diff --git a/src/manta/cli.py b/src/manta/cli.py index cb79be3..e629064 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -54,9 +54,11 @@ Usage: def help(): print(usage) + def version(): print(logo) + def wrong_args(): print('Wrong number of arguments, run "manta help" for usage.') diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 6e38e54..ffce911 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -68,98 +68,102 @@ class LogicAnalyzerCore(Elaboratable): warn(f"Ignoring unrecognized option '{option}' in Logic Analyzer.") # Check sample depth is provided and positive - if "sample_depth" not in config: + sample_depth = config.get("sample_depth") + if not sample_depth: raise ValueError("Logic Analyzer must have sample_depth specified.") - if not isinstance(config["sample_depth"], int): - raise ValueError("Logic Analyzer sample_depth must be an integer.") - - if config["sample_depth"] <= 0: - raise ValueError("Logic Analyzer sample_depth must be positive.") + if not isinstance(sample_depth, int) or sample_depth <= 0: + raise ValueError("Logic Analyzer sample_depth must be a positive integer.") # Check probes - if "probes" not in config: - raise ValueError("Logic Analyzer must have at least one probe specified.") - - if len(config["probes"]) == 0: + if "probes" not in config or len(config["probes"]) == 0: raise ValueError("Logic Analyzer must have at least one probe specified.") for name, width in config["probes"].items(): if width < 0: raise ValueError(f"Width of probe {name} must be positive.") - # Check triggers - if "triggers" not in config: - raise ValueError("Logic Analyzer must have at least one trigger specified.") - - if len(config["triggers"]) == 0: - raise ValueError("Logic Analyzer must have at least one trigger specified.") - - # Check trigger location - if "trigger_location" in config: - if not isinstance(config["trigger_location"], int): - raise ValueError("Trigger location must be an integer.") - - if config["trigger_location"] < 0: - raise ValueError("Trigger location must be positive.") - - if config["trigger_location"] > config["sample_depth"]: - raise ValueError("Trigger location cannot exceed sample depth.") - # Check trigger mode, if provided - if "trigger_mode" in config: - valid_modes = ["single_shot", "incremental", "immediate"] - if config["trigger_mode"] not in valid_modes: + trigger_mode = config.get("trigger_mode") + valid_modes = ["single_shot", "incremental", "immediate"] + if trigger_mode and trigger_mode not in valid_modes: + raise ValueError( + f"Unrecognized trigger mode {config['trigger_mode']} provided." + ) + + # Check triggers + if (trigger_mode) and (trigger_mode != "immediate"): + if ("triggers" not in config) or (config["triggers"] == 0): raise ValueError( - f"Unrecognized trigger mode {config['trigger_mode']} provided." + "Logic Analyzer must have at least one trigger specified." ) - if config["trigger_mode"] == "incremental": - if "trigger_location" in config: - warn( - "Ignoring option 'trigger_location', as 'trigger_mode' is set to immediate, and there is no trigger condition to wait for." - ) + # Check trigger location + trigger_location = config.get("trigger_location") + if trigger_location: + if not isinstance(trigger_location, int) or trigger_location < 0: + raise ValueError("Trigger location must be a positive integer.") + + if trigger_location > config["sample_depth"]: + raise ValueError("Trigger location cannot exceed sample depth.") + + if trigger_mode == "immediate": + warn( + "Ignoring option 'trigger_location', as 'trigger_mode' is set to immediate, and there is no trigger condition to wait for." + ) # Check triggers themselves - for trigger in config["triggers"]: - if not isinstance(trigger, str): - raise ValueError("Trigger must be specified with a string.") + if trigger_mode == "immediate": + if "triggers" in config: + warn( + "Ignoring triggers as 'trigger_mode' is set to immediate, and there are no triggers to specify." + ) - # Trigger conditions may be composed of either two or three components, - # depending on the operation specified. In the case of operations that - # don't need an argument (like DISABLE, RISING, FALLING, CHANGING) or - # three statements in + else: + if ("triggers" not in config) or (len(config["triggers"]) == 0): + raise ValueError("At least one trigger must be specified.") - # Check the trigger operations - components = trigger.strip().split(" ") - if len(components) == 2: - name, op = components - if op not in ["DISABLE", "RISING", "FALLING", "CHANGING"]: + for trigger in config.get("triggers"): + if not isinstance(trigger, str): + raise ValueError("Trigger must be specified with a string.") + + # Trigger conditions may be composed of either two or three components, + # depending on the operation specified. In the case of operations that + # don't need an argument (like DISABLE, RISING, FALLING, CHANGING) or + # three statements in + + # Check the trigger operations + components = trigger.strip().split(" ") + if len(components) == 2: + name, op = components + if op not in ["DISABLE", "RISING", "FALLING", "CHANGING"]: + raise ValueError( + f"Unable to interpret trigger condition '{trigger}'." + ) + + elif len(components) == 3: + name, op, arg = components + if op not in ["GT", "LT", "GEQ", "LEQ", "EQ", "NEQ"]: + raise ValueError( + f"Unable to interpret trigger condition '{trigger}'." + ) + + else: raise ValueError( f"Unable to interpret trigger condition '{trigger}'." ) - elif len(components) == 3: - name, op, arg = components - if op not in ["GT", "LT", "GEQ", "LEQ", "EQ", "NEQ"]: - raise ValueError( - f"Unable to interpret trigger condition '{trigger}'." - ) - - else: - raise ValueError(f"Unable to interpret trigger condition '{trigger}'.") - - # Check probe names - if components[0] not in config["probes"]: - raise ValueError(f"Unknown probe name '{components[0]}' specified.") + # Check probe names + if components[0] not in config["probes"]: + raise ValueError(f"Unknown probe name '{components[0]}' specified.") def elaborate(self, platform): m = Module() # Add submodules - m.submodules["fsm"] = fsm = self.fsm - m.submodules["sample_mem"] = sample_mem = self.sample_mem - m.submodules["trig_blk"] = trig_blk = self.trig_blk + m.submodules.fsm = fsm = self.fsm + m.submodules.sample_mem = sample_mem = self.sample_mem + m.submodules.trig_blk = trig_blk = self.trig_blk # Concat all the probes together, and feed to input of sample memory # (it is necessary to reverse the order such that first probe occupies @@ -173,11 +177,10 @@ class LogicAnalyzerCore(Elaboratable): trig_blk.bus_i.eq(self.fsm.bus_o), sample_mem.bus_i.eq(trig_blk.bus_o), self.bus_o.eq(sample_mem.bus_o), - # Non-bus Connections fsm.trigger.eq(trig_blk.trig), sample_mem.user_addr.eq(fsm.r.write_pointer), - sample_mem.user_we.eq(fsm.write_enable) + sample_mem.user_we.eq(fsm.write_enable), ] return m @@ -215,6 +218,7 @@ class LogicAnalyzerCore(Elaboratable): print_if_verbose(" -> Resetting core...") state = self.fsm.r.get_probe("state") if state != self.fsm.states["IDLE"]: + self.fsm.r.set_probe("request_start", 0) self.fsm.r.set_probe("request_stop", 0) self.fsm.r.set_probe("request_stop", 1) self.fsm.r.set_probe("request_stop", 0) @@ -224,12 +228,16 @@ class LogicAnalyzerCore(Elaboratable): # Set triggers print_if_verbose(" -> Setting triggers...") - self.trig_blk.set_triggers(self.config) + self.trig_blk.clear_triggers() + + if self.config["trigger_mode"] != "immediate": + self.trig_blk.set_triggers(self.config) # Set trigger mode, default to single-shot if user didn't specify a mode print_if_verbose(" -> Setting trigger mode...") if "trigger_mode" in self.config: - self.fsm.r.set_probe("trigger_mode", self.config["trigger_mode"]) + mode = self.config["trigger_mode"].upper() + self.fsm.r.set_probe("trigger_mode", self.fsm.trigger_modes[mode]) else: self.fsm.r.set_probe("trigger_mode", self.fsm.trigger_modes["SINGLE_SHOT"]) @@ -244,6 +252,7 @@ class LogicAnalyzerCore(Elaboratable): # Send a start request to the state machine print_if_verbose(" -> Starting capture...") + self.fsm.r.set_probe("request_start", 0) self.fsm.r.set_probe("request_start", 1) self.fsm.r.set_probe("request_start", 0) @@ -362,16 +371,20 @@ class LogicAnalyzerCapture: signals.append(signal) clock = writer.register_var("manta", "clk", "wire", size=1) - trigger = writer.register_var("manta", "trigger", "wire", size=1) + + # include a trigger signal such would be meaningful (ie, we didn't trigger immediately) + if self.config["trigger_mode"] != "immediate": + trigger = writer.register_var("manta", "trigger", "wire", size=1) # add the data to each probe in the vcd file for timestamp in range(0, 2 * len(self.data)): # run the clock writer.change(clock, timestamp, timestamp % 2 == 0) - # set the trigger - triggered = (timestamp // 2) >= self.get_trigger_location() - writer.change(trigger, timestamp, triggered) + # set the trigger (if there is one) + if self.config["trigger_mode"] != "immediate": + triggered = (timestamp // 2) >= self.get_trigger_location() + writer.change(trigger, timestamp, triggered) # add other signals for signal in signals: diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 4d8583e..d146818 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -56,7 +56,7 @@ class LogicAnalyzerFSM(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules["registers"] = self.r + m.submodules.registers = self.r prev_request_start = Signal(1) prev_request_stop = Signal(1) @@ -74,6 +74,7 @@ class LogicAnalyzerFSM(Elaboratable): m.d.sync += self.write_enable.eq(1) with m.If(self.r.trigger_mode == self.trigger_modes["IMMEDIATE"]): m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) with m.Else(): with m.If(self.r.trigger_location == 0): @@ -82,7 +83,7 @@ class LogicAnalyzerFSM(Elaboratable): with m.Else(): m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) - m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) + # m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) with m.Elif(self.r.state == self.states["MOVE_TO_POSITION"]): m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index a08db8a..50100e6 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -38,7 +38,7 @@ class LogicAnalyzerPlayback(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules["mem"] = self.mem + m.submodules.mem = self.mem m.d.comb += self.read_port.en.eq(1) diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 0d0a0bd..0591e2e 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -28,12 +28,13 @@ class LogicAnalyzerTriggerBlock(Elaboratable): def get_max_addr(self): return self.r.get_max_addr() - def set_triggers(self, config): - # reset all triggers to zero + def clear_triggers(self): + # reset all triggers to disabled with no argument for p in self.probes: self.r.set_probe(p.name + "_op", 0) self.r.set_probe(p.name + "_arg", 0) + def set_triggers(self, config): # set triggers for trigger in config["triggers"]: components = trigger.strip().split(" ") @@ -53,7 +54,7 @@ class LogicAnalyzerTriggerBlock(Elaboratable): m = Module() # Add IO Core as submodule - m.submodules["registers"] = self.r + m.submodules.registers = self.r # Add triggers as submodules for t in self.triggers: diff --git a/src/manta/manta.py b/src/manta/manta.py index 63f902b..a86150a 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -126,7 +126,7 @@ class Manta(Elaboratable): m = Module() # Add interface as submodule - m.submodules["interface"] = self.interface + m.submodules.interface = self.interface # Add all cores as submodules for name, instance in self.cores.items(): diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index e74e32d..db54a36 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -61,7 +61,7 @@ class ReadOnlyMemoryCore(Elaboratable): m.d.sync += self.bus_pipe[0].eq(self.bus_i) for i in range(1, 3): - m.d.sync += self.bus_pipe[i].eq(self.bus_pipe[i-1]) + m.d.sync += self.bus_pipe[i].eq(self.bus_pipe[i - 1]) m.d.sync += self.bus_o.eq(self.bus_pipe[2]) diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index a6f5c19..7540c93 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -232,10 +232,10 @@ class UARTInterface(Elaboratable): # fancy submoduling and such goes in here m = Module() - m.submodules["uart_rx"] = uart_rx = UARTReceiver(self.clocks_per_baud) - m.submodules["bridge_rx"] = bridge_rx = ReceiveBridge() - m.submodules["bridge_tx"] = bridge_tx = TransmitBridge() - m.submodules["uart_tx"] = uart_tx = UARTTransmitter(self.clocks_per_baud) + m.submodules.uart_rx = uart_rx = UARTReceiver(self.clocks_per_baud) + m.submodules.bridge_rx = bridge_rx = ReceiveBridge() + m.submodules.bridge_tx = bridge_tx = TransmitBridge() + m.submodules.uart_tx = uart_tx = UARTTransmitter(self.clocks_per_baud) m.d.comb += [ # UART RX -> Internal Bus diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index c463aa6..1e6f31c 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -13,7 +13,7 @@ class IOCoreLoopbackTest(Elaboratable): self.port = port self.config = self.platform_specific_config() - self.m = Manta(self.config) + self.manta = Manta(self.config) def platform_specific_config(self): return { @@ -41,17 +41,17 @@ class IOCoreLoopbackTest(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules["manta"] = self.m + m.submodules.manta = self.manta uart_pins = platform.request("uart") m.d.comb += [ - self.m.io_core.probe0.eq(self.m.io_core.probe4), - self.m.io_core.probe1.eq(self.m.io_core.probe5), - self.m.io_core.probe2.eq(self.m.io_core.probe6), - self.m.io_core.probe3.eq(self.m.io_core.probe7), - self.m.interface.rx.eq(uart_pins.rx.i), - uart_pins.tx.o.eq(self.m.interface.tx), + self.manta.io_core.probe0.eq(self.manta.io_core.probe4), + self.manta.io_core.probe1.eq(self.manta.io_core.probe5), + self.manta.io_core.probe2.eq(self.manta.io_core.probe6), + self.manta.io_core.probe3.eq(self.manta.io_core.probe7), + self.manta.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.manta.interface.tx), ] return m @@ -71,7 +71,7 @@ class IOCoreLoopbackTest(Elaboratable): outputs = self.config["cores"]["io_core"]["outputs"] for name, attrs in outputs.items(): - actual = self.m.io_core.get_probe(name) + actual = self.manta.io_core.get_probe(name) if isinstance(attrs, dict): if "initial_value" in attrs: @@ -100,8 +100,8 @@ class IOCoreLoopbackTest(Elaboratable): width = self.config["cores"]["io_core"]["inputs"][input] value = randint(0, 2**width - 1) - self.m.io_core.set_probe(output, value) - readback = self.m.io_core.get_probe(input) + self.manta.io_core.set_probe(output, value) + readback = self.manta.io_core.get_probe(input) if readback != value: raise ValueError( diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 5bfd0ca..12e8c41 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -12,7 +12,7 @@ class LogicAnalyzerCounterTest(Elaboratable): self.port = port self.config = self.platform_specific_config() - self.m = Manta(self.config) + self.manta = Manta(self.config) def platform_specific_config(self): return { @@ -20,9 +20,8 @@ class LogicAnalyzerCounterTest(Elaboratable): "la": { "type": "logic_analyzer", "sample_depth": 1024, - "trigger_location": 500, + "trigger_mode": "immediate", "probes": {"larry": 1, "curly": 3, "moe": 9}, - "triggers": ["moe RISING"], }, }, "uart": { @@ -34,20 +33,20 @@ class LogicAnalyzerCounterTest(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules["manta"] = self.m + m.submodules.manta = self.manta uart_pins = platform.request("uart") - larry = self.m.la.probes[0] - curly = self.m.la.probes[1] - moe = self.m.la.probes[2] + larry = self.manta.la.probes[0] + curly = self.manta.la.probes[1] + moe = self.manta.la.probes[2] m.d.sync += larry.eq(larry + 1) m.d.sync += curly.eq(curly + 1) m.d.sync += moe.eq(moe + 1) m.d.comb += [ - self.m.interface.rx.eq(uart_pins.rx.i), - uart_pins.tx.o.eq(self.m.interface.tx), + self.manta.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.manta.interface.tx), ] return m @@ -57,7 +56,7 @@ class LogicAnalyzerCounterTest(Elaboratable): def verify(self): self.build_and_program() - cap = self.m.la.capture() + cap = self.manta.la.capture() # check that VCD export works cap.export_vcd("out.vcd") @@ -66,7 +65,7 @@ class LogicAnalyzerCounterTest(Elaboratable): cap.export_playback_verilog("out.v") # verify that each signal is just a counter modulo the width of the signal - for name, width in self.m.la.config["probes"].items(): + for name, width in self.manta.la.config["probes"].items(): trace = cap.get_trace(name) for i in range(len(trace) - 1): diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 8c7af24..e9c0710 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -22,7 +22,7 @@ class MemoryCoreLoopbackTest(Elaboratable): self.port = port self.config = self.platform_specific_config() - self.m = Manta(self.config) + self.manta = Manta(self.config) def platform_specific_config(self): return { @@ -50,16 +50,16 @@ class MemoryCoreLoopbackTest(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules["manta"] = self.m + m.submodules.manta = self.manta uart_pins = platform.request("uart") m.d.comb += [ - self.m.mem_core.user_addr.eq(self.m.io_core.addr), - self.m.mem_core.user_data.eq(self.m.io_core.data), - self.m.mem_core.user_we.eq(self.m.io_core.we), - self.m.interface.rx.eq(uart_pins.rx.i), - uart_pins.tx.o.eq(self.m.interface.tx), + self.manta.mem_core.user_addr.eq(self.manta.io_core.addr), + self.manta.mem_core.user_data.eq(self.manta.io_core.data), + self.manta.mem_core.user_we.eq(self.manta.io_core.we), + self.manta.interface.rx.eq(uart_pins.rx.i), + uart_pins.tx.o.eq(self.manta.interface.tx), ] return m @@ -68,14 +68,14 @@ class MemoryCoreLoopbackTest(Elaboratable): self.platform.build(self, do_program=True) def write_user_side(self, addr, data): - self.m.io_core.set_probe("we", 0) - self.m.io_core.set_probe("addr", addr) - self.m.io_core.set_probe("data", data) - self.m.io_core.set_probe("we", 1) - self.m.io_core.set_probe("we", 0) + self.manta.io_core.set_probe("we", 0) + self.manta.io_core.set_probe("addr", addr) + self.manta.io_core.set_probe("data", data) + self.manta.io_core.set_probe("we", 1) + self.manta.io_core.set_probe("we", 0) def verify_register(self, addr, expected_data): - data = self.m.mem_core.read_from_user_addr(addr) + data = self.manta.mem_core.read_from_user_addr(addr) if data != expected_data: raise ValueError( From edd00310c4e357c4f2d0eb16fd0bbe052e37fb1d Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 14 Jan 2024 14:49:02 -0800 Subject: [PATCH 30/89] first pass at logic analyzer trigger block tests --- src/manta/logic_analyzer/__init__.py | 6 +- src/manta/logic_analyzer/trigger_block.py | 4 +- test/logic_analyzer_trig_blk_sim.py | 181 ++++++++++++++++++++++ 3 files changed, 186 insertions(+), 5 deletions(-) create mode 100644 test/logic_analyzer_trig_blk_sim.py diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index ffce911..bfbf295 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -92,10 +92,10 @@ class LogicAnalyzerCore(Elaboratable): ) # Check triggers - if (trigger_mode) and (trigger_mode != "immediate"): - if ("triggers" not in config) or (config["triggers"] == 0): + if trigger_mode and trigger_mode != "immediate": + if "triggers" not in config or config["triggers"] == 0: raise ValueError( - "Logic Analyzer must have at least one trigger specified." + "Logic Analyzer must have at least one trigger specified if not running in immediate mode." ) # Check trigger location diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 0591e2e..7dca023 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -101,10 +101,10 @@ class LogicAnalyzerTrigger(Elaboratable): m.d.comb += self.triggered.eq(0) with m.Elif(self.op == self.operations["RISING"]): - m.d.comb += self.triggered.eq((self.signal) & (~prev)) + m.d.comb += self.triggered.eq(self.signal > prev) with m.Elif(self.op == self.operations["FALLING"]): - m.d.comb += self.triggered.eq((~self.signal) & (prev)) + m.d.comb += self.triggered.eq(self.signal < prev) with m.Elif(self.op == self.operations["CHANGING"]): m.d.comb += self.triggered.eq(self.signal != prev) diff --git a/test/logic_analyzer_trig_blk_sim.py b/test/logic_analyzer_trig_blk_sim.py new file mode 100644 index 0000000..910bfa6 --- /dev/null +++ b/test/logic_analyzer_trig_blk_sim.py @@ -0,0 +1,181 @@ +from amaranth import * +from amaranth.sim import Simulator +from manta.logic_analyzer import LogicAnalyzerTriggerBlock +from manta.utils import * +from random import randint, sample + + +# Make random number of random width probes +probes = [Signal(randint(1, 32), name=str(i)) for i in range(randint(1, 32))] +trig_blk = LogicAnalyzerTriggerBlock(probes, base_addr=0, interface=None) + + +def write_trig_blk_register(name, value): + strobe_addr = trig_blk.r.base_addr + yield from write_register(trig_blk, strobe_addr, 0) + + addrs = trig_blk.r.mmap[f"{name}_buf"]["addrs"] + datas = value_to_words(value, len(addrs)) + for addr, data in zip(addrs, datas): + yield from write_register(trig_blk, addr, data) + + yield from write_register(trig_blk, strobe_addr, 1) + yield from write_register(trig_blk, strobe_addr, 0) + + +def test(): + def testbench(): + # Step through each probe and perform all functions in random order + for p in trig_blk.probes: + ops = trig_blk.triggers[0].operations + for op in sample(list(ops.keys()), len(ops)): + # Program operation register with selected register + yield from write_trig_blk_register(f"{p.name}_op", ops[op]) + + if op == "DISABLE": + # Argument can be anything, since it's not used for this operation + yield from write_trig_blk_register( + f"{p.name}_arg", randint(0, (2**p.width) - 1) + ) + yield p.eq(randint(0, (2**p.width) - 1)) + yield + + if (yield trig_blk.trig): + raise ValueError("Trigger raised when disabled!") + + if op == "RISING": + # Argument can be anything, since it's not used for this operation + yield from write_trig_blk_register( + f"{p.name}_arg", randint(0, (2**p.width) - 1) + ) + yield p.eq(0) + yield + yield p.eq(randint(1, (2**p.width) - 1)) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + + if op == "FALLING": + # Argument can be anything, since it's not used for this operation + yield from write_trig_blk_register( + f"{p.name}_arg", randint(0, (2**p.width) - 1) + ) + yield p.eq(randint(1, (2**p.width) - 1)) + yield + yield p.eq(0) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + if op == "CHANGING": + # Argument can be anything, since it's not used for this operation + yield from write_trig_blk_register( + f"{p.name}_arg", randint(0, (2**p.width) - 1) + ) + yield p.eq(randint(1, (2**p.width) - 1)) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + if op == "GT": + upper = randint(1, (2**p.width) - 1) + lower = randint(0, upper - 1) + + yield from write_trig_blk_register(f"{p.name}_arg", lower) + yield p.eq(upper) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + if op == "LT": + upper = randint(1, (2**p.width) - 1) + lower = randint(0, upper - 1) + + yield from write_trig_blk_register(f"{p.name}_arg", upper) + yield p.eq(lower) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + if op == "GEQ": + upper = randint(1, (2**p.width) - 1) + lower = randint(0, upper - 1) + + # test that the case where it's equal + yield from write_trig_blk_register(f"{p.name}_arg", lower) + yield p.eq(lower) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + # test the case where it's greater than + yield p.eq(upper) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + if op == "LEQ": + upper = randint(1, (2**p.width) - 1) + lower = randint(0, upper - 1) + + # test that the case where it's equal + yield from write_trig_blk_register(f"{p.name}_arg", upper) + yield p.eq(upper) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + # test the case where it's less than + yield p.eq(lower) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + if op == "EQ": + value = randint(0, (2**p.width) - 1) + yield from write_trig_blk_register(f"{p.name}_arg", value) + yield p.eq(value) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + if op == "NEQ": + upper = randint(1, (2**p.width) - 1) + lower = randint(0, upper - 1) + + # test that the case where it's equal + yield from write_trig_blk_register(f"{p.name}_arg", upper) + yield p.eq(lower) + yield + + if not (yield trig_blk.trig): + raise ValueError(f"Trigger not raised on probe {p.name}!") + pass + + + # disable probe once complete + yield + yield from write_trig_blk_register(f"{p.name}_op", ops["DISABLE"]) + yield from write_trig_blk_register(f"{p.name}_arg", 0) + yield p.eq(0) + + simulate(trig_blk, testbench, "out.vcd") From a8b43849ecb4d50fcf7873761ef6bae019adbc3c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 15 Jan 2024 12:33:59 -0800 Subject: [PATCH 31/89] remove trig_blk test - was not adding value --- test/logic_analyzer_trig_blk_sim.py | 181 ---------------------------- 1 file changed, 181 deletions(-) delete mode 100644 test/logic_analyzer_trig_blk_sim.py diff --git a/test/logic_analyzer_trig_blk_sim.py b/test/logic_analyzer_trig_blk_sim.py deleted file mode 100644 index 910bfa6..0000000 --- a/test/logic_analyzer_trig_blk_sim.py +++ /dev/null @@ -1,181 +0,0 @@ -from amaranth import * -from amaranth.sim import Simulator -from manta.logic_analyzer import LogicAnalyzerTriggerBlock -from manta.utils import * -from random import randint, sample - - -# Make random number of random width probes -probes = [Signal(randint(1, 32), name=str(i)) for i in range(randint(1, 32))] -trig_blk = LogicAnalyzerTriggerBlock(probes, base_addr=0, interface=None) - - -def write_trig_blk_register(name, value): - strobe_addr = trig_blk.r.base_addr - yield from write_register(trig_blk, strobe_addr, 0) - - addrs = trig_blk.r.mmap[f"{name}_buf"]["addrs"] - datas = value_to_words(value, len(addrs)) - for addr, data in zip(addrs, datas): - yield from write_register(trig_blk, addr, data) - - yield from write_register(trig_blk, strobe_addr, 1) - yield from write_register(trig_blk, strobe_addr, 0) - - -def test(): - def testbench(): - # Step through each probe and perform all functions in random order - for p in trig_blk.probes: - ops = trig_blk.triggers[0].operations - for op in sample(list(ops.keys()), len(ops)): - # Program operation register with selected register - yield from write_trig_blk_register(f"{p.name}_op", ops[op]) - - if op == "DISABLE": - # Argument can be anything, since it's not used for this operation - yield from write_trig_blk_register( - f"{p.name}_arg", randint(0, (2**p.width) - 1) - ) - yield p.eq(randint(0, (2**p.width) - 1)) - yield - - if (yield trig_blk.trig): - raise ValueError("Trigger raised when disabled!") - - if op == "RISING": - # Argument can be anything, since it's not used for this operation - yield from write_trig_blk_register( - f"{p.name}_arg", randint(0, (2**p.width) - 1) - ) - yield p.eq(0) - yield - yield p.eq(randint(1, (2**p.width) - 1)) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - - if op == "FALLING": - # Argument can be anything, since it's not used for this operation - yield from write_trig_blk_register( - f"{p.name}_arg", randint(0, (2**p.width) - 1) - ) - yield p.eq(randint(1, (2**p.width) - 1)) - yield - yield p.eq(0) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - if op == "CHANGING": - # Argument can be anything, since it's not used for this operation - yield from write_trig_blk_register( - f"{p.name}_arg", randint(0, (2**p.width) - 1) - ) - yield p.eq(randint(1, (2**p.width) - 1)) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - if op == "GT": - upper = randint(1, (2**p.width) - 1) - lower = randint(0, upper - 1) - - yield from write_trig_blk_register(f"{p.name}_arg", lower) - yield p.eq(upper) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - if op == "LT": - upper = randint(1, (2**p.width) - 1) - lower = randint(0, upper - 1) - - yield from write_trig_blk_register(f"{p.name}_arg", upper) - yield p.eq(lower) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - if op == "GEQ": - upper = randint(1, (2**p.width) - 1) - lower = randint(0, upper - 1) - - # test that the case where it's equal - yield from write_trig_blk_register(f"{p.name}_arg", lower) - yield p.eq(lower) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - # test the case where it's greater than - yield p.eq(upper) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - if op == "LEQ": - upper = randint(1, (2**p.width) - 1) - lower = randint(0, upper - 1) - - # test that the case where it's equal - yield from write_trig_blk_register(f"{p.name}_arg", upper) - yield p.eq(upper) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - # test the case where it's less than - yield p.eq(lower) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - if op == "EQ": - value = randint(0, (2**p.width) - 1) - yield from write_trig_blk_register(f"{p.name}_arg", value) - yield p.eq(value) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - if op == "NEQ": - upper = randint(1, (2**p.width) - 1) - lower = randint(0, upper - 1) - - # test that the case where it's equal - yield from write_trig_blk_register(f"{p.name}_arg", upper) - yield p.eq(lower) - yield - - if not (yield trig_blk.trig): - raise ValueError(f"Trigger not raised on probe {p.name}!") - pass - - - # disable probe once complete - yield - yield from write_trig_blk_register(f"{p.name}_op", ops["DISABLE"]) - yield from write_trig_blk_register(f"{p.name}_arg", 0) - yield p.eq(0) - - simulate(trig_blk, testbench, "out.vcd") From 6e3fe8cb0e34ef88f64d9a619805d2567532dda8 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 20 Jan 2024 15:25:04 -0800 Subject: [PATCH 32/89] add initial FSM tests --- src/manta/logic_analyzer/fsm.py | 174 ++++++++++++++++++++++------ test/test_logic_analyzer_fsm_sim.py | 73 ++++++++++++ 2 files changed, 209 insertions(+), 38 deletions(-) create mode 100644 test/test_logic_analyzer_fsm_sim.py diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index d146818..7dcbceb 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -58,62 +58,160 @@ class LogicAnalyzerFSM(Elaboratable): m.submodules.registers = self.r + sample_depth = self.config["sample_depth"] + request_start = self.r.request_start + request_stop = self.r.request_stop + trigger_mode = self.r.trigger_mode + trigger_location = self.r.trigger_location + state = self.r.state + write_enable = self.write_enable + write_pointer = self.r.write_pointer + read_pointer = self.r.read_pointer + prev_request_start = Signal(1) prev_request_stop = Signal(1) - # Rising edge detection for start/stop requests - m.d.sync += prev_request_start.eq(self.r.request_start) - m.d.sync += prev_request_stop.eq(self.r.request_stop) + next_state = Signal().like(state) + next_read_pointer = Signal().like(read_pointer) + latch_read_pointer = Signal().like(read_pointer) + next_write_pointer = Signal().like(write_pointer) - with m.If(self.r.state == self.states["IDLE"]): - m.d.sync += self.r.write_pointer.eq(0) - m.d.sync += self.r.read_pointer.eq(0) - m.d.sync += self.write_enable.eq(0) + # COMBINATIONAL SHIT + with m.If(trigger_mode == self.trigger_modes["SINGLE_SHOT"]): + with m.If(state == self.states["IDLE"]): + m.d.comb += write_enable.eq(0) + m.d.comb += write_pointer.eq(0) + m.d.comb += read_pointer.eq(0) + m.d.comb += next_state.eq(self.states["IDLE"]) - with m.If((self.r.request_start) & (~prev_request_start)): - m.d.sync += self.write_enable.eq(1) - with m.If(self.r.trigger_mode == self.trigger_modes["IMMEDIATE"]): - m.d.sync += self.r.state.eq(self.states["CAPTURING"]) - m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) + # Rising edge of request_start beings the capture: + with m.If((request_start) & (~prev_request_start)): + m.d.comb += write_enable.eq(1) + # Go straight to IN_POSITION if trigger_location == 0 + with m.If(trigger_location == 0): + m.d.comb += next_state.eq(self.states["IN_POSITION"]) - with m.Else(): - with m.If(self.r.trigger_location == 0): - m.d.sync += self.r.state.eq(self.states["IN_POSITION"]) + # Otherwise go to MOVE_TO_POSITION + with m.Else(): + m.d.comb += next_state.eq(self.states["MOVE_TO_POSITION"]) + + with m.Elif(state == self.states["MOVE_TO_POSITION"]): + m.d.comb += write_enable.eq(1) + m.d.comb += write_pointer.eq(next_write_pointer) + m.d.comb += read_pointer.eq(0) + m.d.comb += next_state.eq(self.states["MOVE_TO_POSITION"]) + + with m.If(write_pointer == trigger_location - 1): + with m.If(self.trigger): + m.d.comb += next_state.eq(self.states["CAPTURING"]) with m.Else(): - m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) + m.d.comb += next_state.eq(self.states["IN_POSITION"]) - # m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) + with m.Elif(state == self.states["IN_POSITION"]): + m.d.comb += write_enable.eq(1) + m.d.comb += write_pointer.eq(next_write_pointer) + m.d.comb += next_state.eq(self.states["IN_POSITION"]) - with m.Elif(self.r.state == self.states["MOVE_TO_POSITION"]): - m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) - - with m.If(self.r.write_pointer == self.r.trigger_location): with m.If(self.trigger): - m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + m.d.comb += next_state.eq(self.states["CAPTURING"]) + m.d.comb += read_pointer.eq(latch_read_pointer) with m.Else(): - m.d.sync += self.r.state.eq(self.states["IN_POSITION"]) - self.increment_mod_sample_depth(m, self.r.read_pointer) + m.d.comb += read_pointer.eq(next_read_pointer) - with m.Elif(self.r.state == self.states["IN_POSITION"]): - self.increment_mod_sample_depth(m, self.r.write_pointer) + with m.Elif(state == self.states["CAPTURING"]): + m.d.comb += write_enable.eq(1) + m.d.comb += read_pointer.eq(latch_read_pointer) + m.d.comb += next_state.eq(self.states["CAPTURING"]) - with m.If(self.trigger): - m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + with m.If(next_write_pointer == read_pointer): + m.d.comb += write_enable.eq(0) + m.d.comb += next_state.eq(self.states["CAPTURED"]) - with m.Else(): - self.increment_mod_sample_depth(m, self.r.read_pointer) + with m.Else(): + m.d.comb += write_pointer.eq(next_write_pointer) - with m.Elif(self.r.state == self.states["CAPTURING"]): - with m.If(self.r.write_pointer == self.r.read_pointer): - m.d.sync += self.write_enable.eq(0) - m.d.sync += self.r.state.eq(self.states["CAPTURED"]) + with m.Elif(state == self.states["CAPTURED"]): + m.d.comb += next_state.eq(self.states["CAPTURED"]) + m.d.comb += read_pointer.eq(latch_read_pointer) + m.d.comb += write_enable.eq(0) + # m.d.comb += read_pointer.eq(read_pointer) + # m.d.comb += write_pointer.eq(write_pointer) - with m.Else(): - self.increment_mod_sample_depth(m, self.r.write_pointer) + with m.If(self.r.trigger_mode == self.trigger_modes["IMMEDIATE"]): + pass - with m.If((self.r.request_stop) & (~prev_request_stop)): - m.d.sync += self.r.state.eq(self.states["IDLE"]) + with m.If(self.r.trigger_mode == self.trigger_modes["INCREMENTAL"]): + pass + + # Regardless of trigger mode, go back to IDLE if request_stop is pulsed + with m.If((request_stop) & (~prev_request_stop)): + m.d.comb += next_state.eq(self.states["IDLE"]) + + # SEQUENTIAL SHIT + + # Rising edge detection for start/stop requests + m.d.sync += prev_request_start.eq(request_start) + m.d.sync += prev_request_stop.eq(request_stop) + + # Copy next into current + m.d.sync += state.eq(next_state) + m.d.sync += next_write_pointer.eq((write_pointer + 1) % sample_depth) + m.d.sync += next_read_pointer.eq((read_pointer + 1) % sample_depth) + m.d.sync += latch_read_pointer.eq(read_pointer) return m + + #### OLD STUFF FOR REFERENCE #### + + # with m.If(self.r.state == self.states["IDLE"]): + # m.d.sync += self.r.write_pointer.eq(0) + # m.d.sync += self.r.read_pointer.eq(0) + # m.d.sync += self.write_enable.eq(0) + + # with m.If((self.r.request_start) & (~prev_request_start)): + # m.d.sync += self.write_enable.eq(1) + # with m.If(self.r.trigger_mode == self.trigger_modes["IMMEDIATE"]): + # m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + # m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) + + # with m.Else(): + # with m.If(self.r.trigger_location == 0): + # m.d.sync += self.r.state.eq(self.states["IN_POSITION"]) + + # with m.Else(): + # m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) + + # # m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) + + # with m.Elif(self.r.state == self.states["MOVE_TO_POSITION"]): + # m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) + + # with m.If(self.r.write_pointer == self.r.trigger_location): + # with m.If(self.trigger): + # m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + + # with m.Else(): + # m.d.sync += self.r.state.eq(self.states["IN_POSITION"]) + # self.increment_mod_sample_depth(m, self.r.read_pointer) + + # with m.Elif(self.r.state == self.states["IN_POSITION"]): + # self.increment_mod_sample_depth(m, self.r.write_pointer) + + # with m.If(self.trigger): + # m.d.sync += self.r.state.eq(self.states["CAPTURING"]) + + # with m.Else(): + # self.increment_mod_sample_depth(m, self.r.read_pointer) + + # with m.Elif(self.r.state == self.states["CAPTURING"]): + # with m.If(self.r.write_pointer == self.r.read_pointer): + # m.d.sync += self.write_enable.eq(0) + # m.d.sync += self.r.state.eq(self.states["CAPTURED"]) + + # with m.Else(): + # self.increment_mod_sample_depth(m, self.r.write_pointer) + + # with m.If((self.r.request_stop) & (~prev_request_stop)): + # m.d.sync += self.r.state.eq(self.states["IDLE"]) diff --git a/test/test_logic_analyzer_fsm_sim.py b/test/test_logic_analyzer_fsm_sim.py new file mode 100644 index 0000000..2bd7f8d --- /dev/null +++ b/test/test_logic_analyzer_fsm_sim.py @@ -0,0 +1,73 @@ +from amaranth.sim import Simulator +from manta.logic_analyzer import LogicAnalyzerFSM +from manta.utils import * + +""" +what do we want this to do? + +we want to run a capture in single shot mode, immediate mode, and incremental mode + + +single-shot case: +- exactly the right number of samples are taken +- we only start taking samples once captured + +immediate case: +- exactly the right number of samples are taken +- we only start taking samples once captured + +incremental case: +- exactly the right number of samples are taken +- we only take samples when trig is asserted + +""" +config = {"sample_depth": 8} +fsm = LogicAnalyzerFSM(config, base_addr=0, interface=None) + + +def set_fsm_register(name, data): + addr = fsm.r.mmap[f"{name}_buf"]["addrs"][0] + strobe_addr = fsm.r.base_addr + + yield from write_register(fsm, strobe_addr, 0) + yield from write_register(fsm, addr, data) + yield from write_register(fsm, strobe_addr, 1) + yield from write_register(fsm, strobe_addr, 0) + + +def test_single_shot_always_trigger(): + def testbench(): + if (yield fsm.r.state != fsm.states["IDLE"]): + raise ValueError + + yield fsm.trigger.eq(1) + yield from set_fsm_register("trigger_mode", fsm.trigger_modes["SINGLE_SHOT"]) + yield from set_fsm_register("trigger_location", 4) + yield from set_fsm_register("request_start", 1) + yield from set_fsm_register("request_start", 0) + + for _ in range(100): + yield + + simulate(fsm, testbench, "single_shot_always_trigger.vcd") + + +def test_single_shot_wait_to_trigger(): + def testbench(): + if (yield fsm.r.state != fsm.states["IDLE"]): + raise ValueError + + yield from set_fsm_register("trigger_mode", fsm.trigger_modes["SINGLE_SHOT"]) + yield from set_fsm_register("trigger_location", 4) + yield from set_fsm_register("request_start", 1) + yield from set_fsm_register("request_start", 0) + + for _ in range(8): + yield + + yield fsm.trigger.eq(1) + + for _ in range(100): + yield + + simulate(fsm, testbench, "single_shot_wait_to_trigger.vcd") From ab0909d06bbf2efce6a5629b3037c1ecd5630fa5 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 20 Jan 2024 21:59:42 -0800 Subject: [PATCH 33/89] refactor logic analyzer to use enums, add incremental + immediate trigger modes --- src/manta/logic_analyzer/__init__.py | 12 +- src/manta/logic_analyzer/fsm.py | 288 ++++++++++++++------------- test/test_logic_analyzer_fsm_sim.py | 263 +++++++++++++++++++++--- 3 files changed, 389 insertions(+), 174 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index bfbf295..e78f634 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -2,7 +2,7 @@ from amaranth import * from warnings import warn from ..utils import * from .trigger_block import LogicAnalyzerTriggerBlock -from .fsm import LogicAnalyzerFSM +from .fsm import LogicAnalyzerFSM, States, TriggerModes from .sample_mem import LogicAnalyzerSampleMemory from .playback import LogicAnalyzerPlayback @@ -217,13 +217,13 @@ class LogicAnalyzerCore(Elaboratable): # If core is not in IDLE state, request that it return to IDLE print_if_verbose(" -> Resetting core...") state = self.fsm.r.get_probe("state") - if state != self.fsm.states["IDLE"]: + if state != States.IDLE: self.fsm.r.set_probe("request_start", 0) self.fsm.r.set_probe("request_stop", 0) self.fsm.r.set_probe("request_stop", 1) self.fsm.r.set_probe("request_stop", 0) - if self.fsm.r.get_probe("state") != self.fsm.states["IDLE"]: + if self.fsm.r.get_probe("state") != States.IDLE: raise ValueError("Logic analyzer did not reset to IDLE state.") # Set triggers @@ -237,10 +237,10 @@ class LogicAnalyzerCore(Elaboratable): print_if_verbose(" -> Setting trigger mode...") if "trigger_mode" in self.config: mode = self.config["trigger_mode"].upper() - self.fsm.r.set_probe("trigger_mode", self.fsm.trigger_modes[mode]) + self.fsm.r.set_probe("trigger_mode", TriggerModes[mode]) else: - self.fsm.r.set_probe("trigger_mode", self.fsm.trigger_modes["SINGLE_SHOT"]) + self.fsm.r.set_probe("trigger_mode", TriggerModes.SINGLE_SHOT) # Set trigger location print_if_verbose(" -> Setting trigger location...") @@ -258,7 +258,7 @@ class LogicAnalyzerCore(Elaboratable): # Poll the state machine's state, and wait for the capture to complete print_if_verbose(" -> Waiting for capture to complete...") - while self.fsm.r.get_probe("state") != self.fsm.states["CAPTURED"]: + while self.fsm.r.get_probe("state") != States.CAPTURED: pass # Read out the entirety of the sample memory diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 7dcbceb..38d384d 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -1,23 +1,28 @@ from amaranth import * +from amaranth.lib.enum import IntEnum from math import ceil, log2 from ..io_core import IOCore +class States(IntEnum): + IDLE = 0 + MOVE_TO_POSITION = 1 + IN_POSITION = 2 + CAPTURING = 3 + CAPTURED = 4 + + +class TriggerModes(IntEnum): + SINGLE_SHOT = 0 + INCREMENTAL = 1 + IMMEDIATE = 2 + + class LogicAnalyzerFSM(Elaboratable): """ """ def __init__(self, config, base_addr, interface): self.config = config - self.states = { - "IDLE": 0, - "MOVE_TO_POSITION": 1, - "IN_POSITION": 2, - "CAPTURING": 3, - "CAPTURED": 4, - } - - self.trigger_modes = {"SINGLE_SHOT": 0, "INCREMENTAL": 1, "IMMEDIATE": 2} - self.trigger = Signal(1) self.write_enable = Signal(1) @@ -74,83 +79,11 @@ class LogicAnalyzerFSM(Elaboratable): next_state = Signal().like(state) next_read_pointer = Signal().like(read_pointer) latch_read_pointer = Signal().like(read_pointer) + latch_write_pointer = Signal().like(write_pointer) + latch_write_enable = Signal().like(write_enable) next_write_pointer = Signal().like(write_pointer) - # COMBINATIONAL SHIT - with m.If(trigger_mode == self.trigger_modes["SINGLE_SHOT"]): - with m.If(state == self.states["IDLE"]): - m.d.comb += write_enable.eq(0) - m.d.comb += write_pointer.eq(0) - m.d.comb += read_pointer.eq(0) - m.d.comb += next_state.eq(self.states["IDLE"]) - - # Rising edge of request_start beings the capture: - with m.If((request_start) & (~prev_request_start)): - m.d.comb += write_enable.eq(1) - # Go straight to IN_POSITION if trigger_location == 0 - with m.If(trigger_location == 0): - m.d.comb += next_state.eq(self.states["IN_POSITION"]) - - # Otherwise go to MOVE_TO_POSITION - with m.Else(): - m.d.comb += next_state.eq(self.states["MOVE_TO_POSITION"]) - - with m.Elif(state == self.states["MOVE_TO_POSITION"]): - m.d.comb += write_enable.eq(1) - m.d.comb += write_pointer.eq(next_write_pointer) - m.d.comb += read_pointer.eq(0) - m.d.comb += next_state.eq(self.states["MOVE_TO_POSITION"]) - - with m.If(write_pointer == trigger_location - 1): - with m.If(self.trigger): - m.d.comb += next_state.eq(self.states["CAPTURING"]) - - with m.Else(): - m.d.comb += next_state.eq(self.states["IN_POSITION"]) - - with m.Elif(state == self.states["IN_POSITION"]): - m.d.comb += write_enable.eq(1) - m.d.comb += write_pointer.eq(next_write_pointer) - m.d.comb += next_state.eq(self.states["IN_POSITION"]) - - with m.If(self.trigger): - m.d.comb += next_state.eq(self.states["CAPTURING"]) - m.d.comb += read_pointer.eq(latch_read_pointer) - - with m.Else(): - m.d.comb += read_pointer.eq(next_read_pointer) - - with m.Elif(state == self.states["CAPTURING"]): - m.d.comb += write_enable.eq(1) - m.d.comb += read_pointer.eq(latch_read_pointer) - m.d.comb += next_state.eq(self.states["CAPTURING"]) - - with m.If(next_write_pointer == read_pointer): - m.d.comb += write_enable.eq(0) - m.d.comb += next_state.eq(self.states["CAPTURED"]) - - with m.Else(): - m.d.comb += write_pointer.eq(next_write_pointer) - - with m.Elif(state == self.states["CAPTURED"]): - m.d.comb += next_state.eq(self.states["CAPTURED"]) - m.d.comb += read_pointer.eq(latch_read_pointer) - m.d.comb += write_enable.eq(0) - # m.d.comb += read_pointer.eq(read_pointer) - # m.d.comb += write_pointer.eq(write_pointer) - - with m.If(self.r.trigger_mode == self.trigger_modes["IMMEDIATE"]): - pass - - with m.If(self.r.trigger_mode == self.trigger_modes["INCREMENTAL"]): - pass - - # Regardless of trigger mode, go back to IDLE if request_stop is pulsed - with m.If((request_stop) & (~prev_request_stop)): - m.d.comb += next_state.eq(self.states["IDLE"]) - - # SEQUENTIAL SHIT - + # --- Sequential Logic --- # Rising edge detection for start/stop requests m.d.sync += prev_request_start.eq(request_start) m.d.sync += prev_request_stop.eq(request_stop) @@ -160,58 +93,137 @@ class LogicAnalyzerFSM(Elaboratable): m.d.sync += next_write_pointer.eq((write_pointer + 1) % sample_depth) m.d.sync += next_read_pointer.eq((read_pointer + 1) % sample_depth) m.d.sync += latch_read_pointer.eq(read_pointer) + m.d.sync += latch_write_pointer.eq(write_pointer) + m.d.sync += latch_write_enable.eq(write_enable) + + # --- Combinational Logic --- + + # --- Single Shot Trigger Mode --- + with m.If(trigger_mode == TriggerModes.SINGLE_SHOT): + with m.If(state == States.IDLE): + m.d.comb += write_enable.eq(0) + m.d.comb += write_pointer.eq(0) + m.d.comb += read_pointer.eq(0) + m.d.comb += next_state.eq(States.IDLE) + + # Rising edge of request_start beings the capture: + with m.If((request_start) & (~prev_request_start)): + m.d.comb += write_enable.eq(1) + # Go straight to IN_POSITION if trigger_location == 0 + with m.If(trigger_location == 0): + m.d.comb += next_state.eq(States.IN_POSITION) + + # Otherwise go to MOVE_TO_POSITION + with m.Else(): + m.d.comb += next_state.eq(States.MOVE_TO_POSITION) + + with m.Elif(state == States.MOVE_TO_POSITION): + m.d.comb += write_enable.eq(1) + m.d.comb += write_pointer.eq(next_write_pointer) + m.d.comb += read_pointer.eq(0) + m.d.comb += next_state.eq(States.MOVE_TO_POSITION) + + with m.If(write_pointer == trigger_location - 1): + with m.If(self.trigger): + m.d.comb += next_state.eq(States.CAPTURING) + + with m.Else(): + m.d.comb += next_state.eq(States.IN_POSITION) + + with m.Elif(state == States.IN_POSITION): + m.d.comb += write_enable.eq(1) + m.d.comb += write_pointer.eq(next_write_pointer) + m.d.comb += next_state.eq(States.IN_POSITION) + + with m.If(self.trigger): + m.d.comb += next_state.eq(States.CAPTURING) + m.d.comb += read_pointer.eq(latch_read_pointer) + + with m.Else(): + m.d.comb += read_pointer.eq(next_read_pointer) + + with m.Elif(state == States.CAPTURING): + m.d.comb += write_enable.eq(1) + m.d.comb += read_pointer.eq(latch_read_pointer) + m.d.comb += next_state.eq(States.CAPTURING) + + with m.If(next_write_pointer == read_pointer): + m.d.comb += write_enable.eq(0) + m.d.comb += write_pointer.eq(latch_write_pointer) + m.d.comb += next_state.eq(States.CAPTURED) + + with m.Else(): + m.d.comb += write_pointer.eq(next_write_pointer) + + with m.Elif(state == States.CAPTURED): + m.d.comb += next_state.eq(States.CAPTURED) + m.d.comb += read_pointer.eq(latch_read_pointer) + m.d.comb += write_pointer.eq(latch_write_pointer) + m.d.comb += write_enable.eq(0) + + # --- Immediate Trigger Mode --- + with m.If(self.r.trigger_mode == TriggerModes.IMMEDIATE): + m.d.comb += read_pointer.eq(0) + with m.If(self.r.state == States.IDLE): + m.d.comb += write_enable.eq(0) + m.d.comb += write_pointer.eq(0) + m.d.comb += next_state.eq(States.IDLE) + + # Rising edge of request_start beings the capture: + with m.If((request_start) & (~prev_request_start)): + m.d.comb += write_enable.eq(1) + m.d.comb += next_state.eq(States.CAPTURING) + + with m.Elif(state == States.CAPTURING): + m.d.comb += write_enable.eq(1) + m.d.comb += next_state.eq(States.CAPTURING) + m.d.comb += write_pointer.eq(next_write_pointer) + + with m.If(next_write_pointer == read_pointer): + m.d.comb += write_enable.eq(0) + m.d.comb += write_pointer.eq(latch_write_pointer) + m.d.comb += next_state.eq(States.CAPTURED) + + with m.Elif(state == States.CAPTURED): + m.d.comb += write_enable.eq(0) + m.d.comb += write_pointer.eq(latch_write_pointer) + m.d.comb += next_state.eq(States.CAPTURED) + + # --- Incremental Trigger Mode --- + with m.If(self.r.trigger_mode == TriggerModes.INCREMENTAL): + with m.If(state == States.IDLE): + m.d.comb += write_enable.eq(0) + m.d.comb += write_pointer.eq(0) + m.d.comb += read_pointer.eq(0) + m.d.comb += next_state.eq(States.IDLE) + + # Rising edge of request_start beings the capture: + with m.If((request_start) & (~prev_request_start)): + m.d.comb += write_enable.eq(self.trigger) + m.d.comb += next_state.eq(States.CAPTURING) + + with m.Elif(state == States.CAPTURING): + m.d.comb += read_pointer.eq(0) + m.d.comb += next_state.eq(States.CAPTURING) + m.d.comb += write_enable.eq(self.trigger) + + with m.If(latch_write_enable): + m.d.comb += write_pointer.eq(next_write_pointer) + with m.Else(): + m.d.comb += write_pointer.eq(latch_write_pointer) + + with m.If((self.trigger) & (next_write_pointer == read_pointer)): + m.d.comb += write_pointer.eq(latch_write_pointer) + m.d.comb += next_state.eq(States.CAPTURED) + + with m.Elif(state == States.CAPTURED): + m.d.comb += next_state.eq(States.CAPTURED) + m.d.comb += read_pointer.eq(latch_read_pointer) + m.d.comb += write_pointer.eq(latch_write_pointer) + m.d.comb += write_enable.eq(0) + + # Regardless of trigger mode, go back to IDLE if request_stop is pulsed + with m.If((request_stop) & (~prev_request_stop)): + m.d.comb += next_state.eq(States.IDLE) return m - - #### OLD STUFF FOR REFERENCE #### - - # with m.If(self.r.state == self.states["IDLE"]): - # m.d.sync += self.r.write_pointer.eq(0) - # m.d.sync += self.r.read_pointer.eq(0) - # m.d.sync += self.write_enable.eq(0) - - # with m.If((self.r.request_start) & (~prev_request_start)): - # m.d.sync += self.write_enable.eq(1) - # with m.If(self.r.trigger_mode == self.trigger_modes["IMMEDIATE"]): - # m.d.sync += self.r.state.eq(self.states["CAPTURING"]) - # m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) - - # with m.Else(): - # with m.If(self.r.trigger_location == 0): - # m.d.sync += self.r.state.eq(self.states["IN_POSITION"]) - - # with m.Else(): - # m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) - - # # m.d.sync += self.r.state.eq(self.states["MOVE_TO_POSITION"]) - - # with m.Elif(self.r.state == self.states["MOVE_TO_POSITION"]): - # m.d.sync += self.r.write_pointer.eq(self.r.write_pointer + 1) - - # with m.If(self.r.write_pointer == self.r.trigger_location): - # with m.If(self.trigger): - # m.d.sync += self.r.state.eq(self.states["CAPTURING"]) - - # with m.Else(): - # m.d.sync += self.r.state.eq(self.states["IN_POSITION"]) - # self.increment_mod_sample_depth(m, self.r.read_pointer) - - # with m.Elif(self.r.state == self.states["IN_POSITION"]): - # self.increment_mod_sample_depth(m, self.r.write_pointer) - - # with m.If(self.trigger): - # m.d.sync += self.r.state.eq(self.states["CAPTURING"]) - - # with m.Else(): - # self.increment_mod_sample_depth(m, self.r.read_pointer) - - # with m.Elif(self.r.state == self.states["CAPTURING"]): - # with m.If(self.r.write_pointer == self.r.read_pointer): - # m.d.sync += self.write_enable.eq(0) - # m.d.sync += self.r.state.eq(self.states["CAPTURED"]) - - # with m.Else(): - # self.increment_mod_sample_depth(m, self.r.write_pointer) - - # with m.If((self.r.request_stop) & (~prev_request_stop)): - # m.d.sync += self.r.state.eq(self.states["IDLE"]) diff --git a/test/test_logic_analyzer_fsm_sim.py b/test/test_logic_analyzer_fsm_sim.py index 2bd7f8d..24d8215 100644 --- a/test/test_logic_analyzer_fsm_sim.py +++ b/test/test_logic_analyzer_fsm_sim.py @@ -1,5 +1,5 @@ from amaranth.sim import Simulator -from manta.logic_analyzer import LogicAnalyzerFSM +from manta.logic_analyzer import * from manta.utils import * """ @@ -25,49 +25,252 @@ config = {"sample_depth": 8} fsm = LogicAnalyzerFSM(config, base_addr=0, interface=None) -def set_fsm_register(name, data): - addr = fsm.r.mmap[f"{name}_buf"]["addrs"][0] - strobe_addr = fsm.r.base_addr - - yield from write_register(fsm, strobe_addr, 0) - yield from write_register(fsm, addr, data) - yield from write_register(fsm, strobe_addr, 1) - yield from write_register(fsm, strobe_addr, 0) - - -def test_single_shot_always_trigger(): +def test_signals_reset_correctly(): def testbench(): - if (yield fsm.r.state != fsm.states["IDLE"]): + # Make sure pointers and write enable reset to zero + for sig in [fsm.r.write_pointer, fsm.r.read_pointer, fsm.write_enable]: + if (yield sig) != 0: + raise ValueError + + # Make sure state resets to IDLE + if (yield fsm.r.state != States.IDLE): raise ValueError - yield fsm.trigger.eq(1) - yield from set_fsm_register("trigger_mode", fsm.trigger_modes["SINGLE_SHOT"]) - yield from set_fsm_register("trigger_location", 4) - yield from set_fsm_register("request_start", 1) - yield from set_fsm_register("request_start", 0) + simulate(fsm, testbench) - for _ in range(100): + +def test_single_shot_no_wait_for_trigger(): + def testbench(): + # Configure and start FSM + yield fsm.trigger.eq(1) + yield fsm.r.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.r.trigger_location.eq(4) + yield fsm.r.request_start.eq(1) + + # Wait until write_enable is asserted + while not (yield fsm.write_enable): yield - simulate(fsm, testbench, "single_shot_always_trigger.vcd") + # Wait 8 clock cycles for capture to complete + for i in range(8): + # Make sure that read_pointer does not increase + if (yield fsm.r.read_pointer) != 0: + raise ValueError + # Make sure that write_pointer increases by one each cycle + if (yield fsm.r.write_pointer) != i: + raise ValueError -def test_single_shot_wait_to_trigger(): - def testbench(): - if (yield fsm.r.state != fsm.states["IDLE"]): + yield + + # Wait one clock cycle (to let BRAM contents cycle in) + yield + + # Check that write_pointer points to the end of memory + if (yield fsm.r.write_pointer) != 7: raise ValueError - yield from set_fsm_register("trigger_mode", fsm.trigger_modes["SINGLE_SHOT"]) - yield from set_fsm_register("trigger_location", 4) - yield from set_fsm_register("request_start", 1) - yield from set_fsm_register("request_start", 0) + # Check that state is CAPTURED + if (yield fsm.r.state) != States.CAPTURED: + raise ValueError + + simulate(fsm, testbench, "single_shot_no_wait_for_trigger.vcd") + + +def test_single_shot_wait_for_trigger(): + def testbench(): + # Configure and start FSM + yield fsm.r.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.r.trigger_location.eq(4) + yield fsm.r.request_start.eq(1) + yield + + # Check that write_enable is asserted on the same edge as request_start + if not (yield fsm.write_enable): + raise ValueError + + # Wait 4 clock cycles to get to IN_POSITION + for i in range(4): + rp = yield fsm.r.read_pointer + wp = yield fsm.r.write_pointer + + # Make sure that read_pointer does not increase + if rp != 0: + raise ValueError + + # Make sure that write_pointer increases by one each cycle + if wp != i: + raise ValueError + + yield + + # Wait a few cycles before triggering: + for _ in range(10): + if (rp + 3) % fsm.config["sample_depth"] != wp: + raise ValueError + + yield + + # Provide the trigger, and check that the capture completes 4 cycles later + yield fsm.trigger.eq(1) + yield + + rp_start = yield fsm.r.read_pointer + for i in range(4): + rp = yield fsm.r.read_pointer + wp = yield fsm.r.write_pointer + + if rp != rp_start: + raise ValueError + + if (rp_start + 4 + i) % fsm.config["sample_depth"] != wp: + raise ValueError + + yield + + # Wait one clock cycle (to let BRAM contents cycle in) + yield + + # Check that write_pointer points to the end of memory + rp = yield fsm.r.read_pointer + wp = yield fsm.r.write_pointer + if (wp + 1) % fsm.config["sample_depth"] != rp: + raise ValueError + + # Check that state is CAPTURED + if (yield fsm.r.state) != States.CAPTURED: + raise ValueError + + simulate(fsm, testbench, "single_shot_wait_for_trigger.vcd") + + +def test_immediate(): + def testbench(): + # Configure and start FSM + yield fsm.r.trigger_mode.eq(TriggerModes.IMMEDIATE) + yield fsm.r.request_start.eq(1) + yield + + # Check that write_enable is asserted on the same edge as request_start + if not (yield fsm.write_enable): + raise ValueError + + for i in range(fsm.config["sample_depth"]): + rp = yield fsm.r.read_pointer + wp = yield fsm.r.write_pointer + + if rp != 0: + raise ValueError + + if wp != i: + raise ValueError + + yield + + # Wait one clock cycle (to let BRAM contents cycle in) + yield + + # Check that write_pointer points to the end of memory + rp = yield fsm.r.read_pointer + wp = yield fsm.r.write_pointer + if rp != 0: + raise ValueError + if wp != 7: + raise ValueError + + # Check that state is CAPTURED + if (yield fsm.r.state) != States.CAPTURED: + raise ValueError + + simulate(fsm, testbench, "immediate.vcd") + + +def test_incremental(): + def testbench(): + # Configure and start FSM + yield fsm.r.trigger_mode.eq(TriggerModes.INCREMENTAL) + yield fsm.r.request_start.eq(1) + yield + + # Check that write_enable is asserted on the same edge as request_start + # if not (yield fsm.write_enable): + # raise ValueError + + for _ in range(10): + for _ in range(3): + yield + + yield fsm.trigger.eq(1) + yield + yield fsm.trigger.eq(0) + yield + + # # Check that state is CAPTURED + # if (yield fsm.r.state) != States.CAPTURED: + # raise ValueError + + simulate(fsm, testbench, "incremental.vcd") + + +def test_single_shot_write_enable(): + def testbench(): + # Configure FSM + yield fsm.r.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.r.trigger_location.eq(4) + yield + + # Make sure write is not enabled before starting the FSM + if (yield fsm.write_enable): + raise ValueError + + # Start the FSM, ensure write enable is asserted throughout the capture + yield fsm.r.request_start.eq(1) + yield + + for _ in range(fsm.config["sample_depth"]): + if not (yield fsm.write_enable): + raise ValueError - for _ in range(8): yield yield fsm.trigger.eq(1) + yield + + for _ in range(4): + if not (yield fsm.write_enable): + raise ValueError - for _ in range(100): yield - simulate(fsm, testbench, "single_shot_wait_to_trigger.vcd") + # Make sure write_enable is deasserted after + if (yield fsm.write_enable): + raise ValueError + + simulate(fsm, testbench, "single_shot_write_enable.vcd") + + +def test_immediate_write_enable(): + def testbench(): + # Configure FSM + yield fsm.r.trigger_mode.eq(TriggerModes.IMMEDIATE) + yield + + # Make sure write is not enabled before starting the FSM + if (yield fsm.write_enable): + raise ValueError + + # Start the FSM, ensure write enable is asserted throughout the capture + yield fsm.r.request_start.eq(1) + yield + + for _ in range(fsm.config["sample_depth"]): + if not (yield fsm.write_enable): + raise ValueError + + yield + + # Make sure write_enable is deasserted after + if (yield fsm.write_enable): + raise ValueError + + simulate(fsm, testbench, "immediate_write_enable.vcd") From b8de6339aae97898436cd06b085559028840b1a2 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 21 Jan 2024 00:23:07 -0800 Subject: [PATCH 34/89] adjust some ergonomics found while playtesting --- doc/getting_started.md | 21 ++------------ doc/logic_analyzer_core.md | 2 +- src/manta/cli.py | 41 +++++++++++++++++++--------- src/manta/io_core.py | 1 - src/manta/logic_analyzer/__init__.py | 17 +++++++++--- src/manta/manta.py | 3 +- src/manta/memory_core.py | 1 - src/manta/uart/__init__.py | 1 - src/manta/utils.py | 16 +++++++++-- 9 files changed, 60 insertions(+), 43 deletions(-) diff --git a/doc/getting_started.md b/doc/getting_started.md index 2de3e05..e6b3141 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -58,34 +58,19 @@ This Manta instance has an IO Core and a Logic Analyzer, each containing a numbe ## Example Instantiation -The Verilog file generated by `manta gen` contains some information at the top of the file. This includes an example instantiation for the `manta` module that's been configured, which you can copy paste into your source code. Here's what that looks like for the configuration above: - -```c -/* -This module was generated with Manta v0.0.5 on 11 Sep 2023 at 17:52:28 by fischerm - -If this breaks or if you've got spicy formal verification memes, contact fischerm [at] mit.edu - -Provided under a GNU GPLv3 license. Go wild. - -Here's an example instantiation of the Manta module you configured, feel free to copy-paste -this into your source! +Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design. This is done by running `manta inst` with the path to the configuration file describing the Manta core you'd like to instantiate. For example, the following snippet is generated for the configuration above: +```verilog manta manta_inst ( .clk(clk), - + .rst(rst) .rx(rx), .tx(tx), - .probe_0_in(probe_0_in), .probe_1_in(probe_1_in), .probe_2_out(probe_2_out), .probe_3_out(probe_3_out), - - .larry(larry), .curly(curly), .moe(moe)); - -*/ ``` \ No newline at end of file diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index bcf0a4b..50debe6 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -116,7 +116,7 @@ If the file `manta.yaml` contained the configuration above, then running: manta capture manta.yaml my_logic_analyzer capture.v ``` -Generates a Verilog module at `capture.v` which can then be instantiated in the testbench or FPGA design in which it is needed. An example instantiation is provided at the top of the output verilog, so a simple copy-paste into the testbench is all that's necessary to use the module. +Generates a Verilog module at `capture.v` which can then be instantiated in the testbench or FPGA design in which it is needed. This is useful for two situations in particular: diff --git a/src/manta/cli.py b/src/manta/cli.py index e629064..610ec13 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -1,5 +1,5 @@ from .manta import Manta -from warnings import warn +from .utils import * from sys import argv from pkg_resources import get_distribution @@ -37,6 +37,10 @@ Usage: Generate a verilog file specifying the Manta module from a given configuration file, and save to the provided path. + inst [config_file] + Generate a copy-pasteable Verilog snippet to instantiate Manta + in your design. + capture [config_file] [la_core_name] [vcd_file] [verilog_file] Start a capture on the specified core, and save the results to a .vcd or .v file at the provided path(s). @@ -61,6 +65,7 @@ def version(): def wrong_args(): print('Wrong number of arguments, run "manta help" for usage.') + exit(1) def gen(config_path, output_path): @@ -79,9 +84,23 @@ def gen(config_path, output_path): ) +def inst(config_path): + m = Manta(config_path) + ports = m.get_top_level_ports() + hdl = ",\n ".join([f".{p.name}({p.name})" for p in ports]) + + foo = """ +manta manta_inst( + .clk(clk), + .rst(rst), + """ + + print(foo + hdl + ");\n") + + def capture(config_path, logic_analyzer_name, export_paths): m = Manta(config_path) - la = getattr(s, logic_analyzer_name) + la = getattr(m, logic_analyzer_name) cap = la.capture() for path in export_paths: @@ -129,20 +148,16 @@ def main(): wrong_args() gen(argv[2], argv[3]) + elif argv[1] == "inst": + if len(argv) != 3: + wrong_args() + + inst(argv[2]) + elif argv[1] == "capture": if len(argv) < 5: wrong_args() - capture(argv[2], argv[3], argv[4]) - - elif argv[1] == "playback": - if len(argv) != 5: - wrong_args() - playback(argv[2], argv[3], argv[4]) - - elif argv[1] == "mmap": - if len(argv) != 3: - wrong_args() - mmap(argv[2]) + capture(argv[2], argv[3], argv[4:]) elif argv[1] == "ports": ports() diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 98ce631..08e7633 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -1,5 +1,4 @@ from amaranth import * -from warnings import warn from .utils import * from math import ceil diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index e78f634..fd8dece 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -1,5 +1,4 @@ from amaranth import * -from warnings import warn from ..utils import * from .trigger_block import LogicAnalyzerTriggerBlock from .fsm import LogicAnalyzerFSM, States, TriggerModes @@ -306,7 +305,11 @@ class LogicAnalyzerCapture: ---------- The trigger location as an `int`. """ - return self.config["trigger_location"] + if "trigger_location" in self.config: + return self.config["trigger_location"] + + else: + return self.config["sample_depth"] // 2 def get_trace(self, probe_name): """Gets the value of a single probe over the capture. @@ -373,7 +376,10 @@ class LogicAnalyzerCapture: clock = writer.register_var("manta", "clk", "wire", size=1) # include a trigger signal such would be meaningful (ie, we didn't trigger immediately) - if self.config["trigger_mode"] != "immediate": + if ( + "trigger_mode" not in self.config + or self.config["trigger_mode"] == "single_shot" + ): trigger = writer.register_var("manta", "trigger", "wire", size=1) # add the data to each probe in the vcd file @@ -382,7 +388,10 @@ class LogicAnalyzerCapture: writer.change(clock, timestamp, timestamp % 2 == 0) # set the trigger (if there is one) - if self.config["trigger_mode"] != "immediate": + if ( + "trigger_mode" not in self.config + or self.config["trigger_mode"] == "single_shot" + ): triggered = (timestamp // 2) >= self.get_trigger_location() writer.change(trigger, timestamp, triggered) diff --git a/src/manta/manta.py b/src/manta/manta.py index a86150a..8e9e997 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -1,5 +1,4 @@ from amaranth import * -from warnings import warn from .uart import UARTInterface # from .ethernet import EthernetInterface @@ -70,7 +69,7 @@ class Manta(Elaboratable): return EthernetInterface(self.config["ethernet"]) else: - raise ValueError("Unrecognized interface specified.") + raise ValueError("No recognized interface specified.") def get_cores(self): """ """ diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index db54a36..17bfd33 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -1,5 +1,4 @@ from amaranth import * -from warnings import warn from .utils import * from math import ceil diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index 7540c93..4cfbeef 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -1,5 +1,4 @@ from amaranth import * -from warnings import warn from ..utils import * from .receiver import UARTReceiver from .receive_bridge import ReceiveBridge diff --git a/src/manta/utils.py b/src/manta/utils.py index 9773a57..98ae766 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -5,13 +5,25 @@ import os class InternalBus(data.StructLayout): - """Describes the layout of Manta's internal bus, such that signals of - the appropriate dimension can be instantiated with Signal(InternalBus()).""" + """ + Describes the layout of Manta's internal bus, such that signals of + the appropriate dimension can be instantiated with Signal(InternalBus()). + """ def __init__(self): super().__init__({"addr": 16, "data": 16, "rw": 1, "valid": 1}) +def warn(message): + """ + Prints a warning to the user's terminal. Originally the warn() method + from the builtin warnings module was used for this, but I don't think the + way it outputs on the command line is the most helpful for the users. + (They don't care about the stacktrace or the filename/line number, for example.) + """ + print("Warning: " + message) + + def words_to_value(data): """ Takes a list of integers, interprets them as 16-bit integers, and From d075c04e2a6f1abb97244c7790ba06a882eadaf3 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 21 Jan 2024 00:47:14 -0800 Subject: [PATCH 35/89] update makefile to not require python scripts on PATH --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index c22f0d1..229247e 100644 --- a/Makefile +++ b/Makefile @@ -1,9 +1,9 @@ .PHONY: test format clean serve_docs test: - pytest + python3 -m pytest format: - black . + python3 -m black . clean: git clean -Xdf From c177e3b5b57e8f128fe1e28793203a3f60441b46 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 21 Jan 2024 00:50:53 -0800 Subject: [PATCH 36/89] update makefile to source venv again --- .github/workflows/run_tests.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index d87e932..3396525 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -34,4 +34,6 @@ jobs: export ICEPACK=/tools/oss-cad-suite/bin/icepack export ICEPROG=/tools/oss-cad-suite/bin/iceprog + source venv/bin/activate + make test \ No newline at end of file From ee4a79a4d42bb434c60d6d6634f4ecd885063d48 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 21 Jan 2024 23:45:14 -0800 Subject: [PATCH 37/89] refactor logic analyzer FSM to be sequential-only for better timing --- src/manta/logic_analyzer/__init__.py | 6 +- src/manta/logic_analyzer/fsm.py | 175 ++++++++------------------- test/test_logic_analyzer_fsm_sim.py | 53 ++------ 3 files changed, 69 insertions(+), 165 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index fd8dece..470843d 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -103,8 +103,8 @@ class LogicAnalyzerCore(Elaboratable): if not isinstance(trigger_location, int) or trigger_location < 0: raise ValueError("Trigger location must be a positive integer.") - if trigger_location > config["sample_depth"]: - raise ValueError("Trigger location cannot exceed sample depth.") + if trigger_location >= config["sample_depth"]: + raise ValueError("Trigger location must be less than sample depth.") if trigger_mode == "immediate": warn( @@ -229,7 +229,7 @@ class LogicAnalyzerCore(Elaboratable): print_if_verbose(" -> Setting triggers...") self.trig_blk.clear_triggers() - if self.config["trigger_mode"] != "immediate": + if self.config.get("trigger_mode") != "immediate": self.trig_blk.set_triggers(self.config) # Set trigger mode, default to single-shot if user didn't specify a mode diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 38d384d..9efe17a 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -76,154 +76,85 @@ class LogicAnalyzerFSM(Elaboratable): prev_request_start = Signal(1) prev_request_stop = Signal(1) - next_state = Signal().like(state) - next_read_pointer = Signal().like(read_pointer) - latch_read_pointer = Signal().like(read_pointer) - latch_write_pointer = Signal().like(write_pointer) - latch_write_enable = Signal().like(write_enable) next_write_pointer = Signal().like(write_pointer) - # --- Sequential Logic --- + m.d.comb += next_write_pointer.eq((write_pointer + 1) % sample_depth) + # Rising edge detection for start/stop requests m.d.sync += prev_request_start.eq(request_start) m.d.sync += prev_request_stop.eq(request_stop) - # Copy next into current - m.d.sync += state.eq(next_state) - m.d.sync += next_write_pointer.eq((write_pointer + 1) % sample_depth) - m.d.sync += next_read_pointer.eq((read_pointer + 1) % sample_depth) - m.d.sync += latch_read_pointer.eq(read_pointer) - m.d.sync += latch_write_pointer.eq(write_pointer) - m.d.sync += latch_write_enable.eq(write_enable) + with m.If(state == States.IDLE): + m.d.sync += write_pointer.eq(0) + m.d.sync += read_pointer.eq(0) + m.d.sync += write_enable.eq(0) - # --- Combinational Logic --- + with m.If((request_start) & (~prev_request_start)): + with m.If(trigger_mode == TriggerModes.IMMEDIATE): + m.d.sync += state.eq(States.CAPTURING) + m.d.sync += write_enable.eq(1) - # --- Single Shot Trigger Mode --- - with m.If(trigger_mode == TriggerModes.SINGLE_SHOT): - with m.If(state == States.IDLE): - m.d.comb += write_enable.eq(0) - m.d.comb += write_pointer.eq(0) - m.d.comb += read_pointer.eq(0) - m.d.comb += next_state.eq(States.IDLE) + with m.Elif(trigger_mode == TriggerModes.INCREMENTAL): + m.d.sync += state.eq(States.CAPTURING) + m.d.sync += write_enable.eq(1) - # Rising edge of request_start beings the capture: - with m.If((request_start) & (~prev_request_start)): - m.d.comb += write_enable.eq(1) - # Go straight to IN_POSITION if trigger_location == 0 + with m.Elif(trigger_mode == TriggerModes.SINGLE_SHOT): with m.If(trigger_location == 0): - m.d.comb += next_state.eq(States.IN_POSITION) - - # Otherwise go to MOVE_TO_POSITION - with m.Else(): - m.d.comb += next_state.eq(States.MOVE_TO_POSITION) - - with m.Elif(state == States.MOVE_TO_POSITION): - m.d.comb += write_enable.eq(1) - m.d.comb += write_pointer.eq(next_write_pointer) - m.d.comb += read_pointer.eq(0) - m.d.comb += next_state.eq(States.MOVE_TO_POSITION) - - with m.If(write_pointer == trigger_location - 1): - with m.If(self.trigger): - m.d.comb += next_state.eq(States.CAPTURING) + m.d.sync += state.eq(States.IN_POSITION) with m.Else(): - m.d.comb += next_state.eq(States.IN_POSITION) + m.d.sync += state.eq(States.MOVE_TO_POSITION) - with m.Elif(state == States.IN_POSITION): - m.d.comb += write_enable.eq(1) - m.d.comb += write_pointer.eq(next_write_pointer) - m.d.comb += next_state.eq(States.IN_POSITION) + m.d.sync += write_enable.eq(1) + with m.Elif(state == States.MOVE_TO_POSITION): + m.d.sync += write_pointer.eq(next_write_pointer) + + with m.If(write_pointer == trigger_location - 1): with m.If(self.trigger): - m.d.comb += next_state.eq(States.CAPTURING) - m.d.comb += read_pointer.eq(latch_read_pointer) + m.d.sync += state.eq(States.CAPTURING) with m.Else(): - m.d.comb += read_pointer.eq(next_read_pointer) + m.d.sync += state.eq(States.IN_POSITION) - with m.Elif(state == States.CAPTURING): - m.d.comb += write_enable.eq(1) - m.d.comb += read_pointer.eq(latch_read_pointer) - m.d.comb += next_state.eq(States.CAPTURING) + with m.Elif(state == States.IN_POSITION): + m.d.sync += write_pointer.eq(next_write_pointer) + with m.If(self.trigger): + m.d.sync += state.eq(States.CAPTURING) + + # kind of horrible, i'll get rid of this later... + with m.If(write_pointer > trigger_location): + m.d.sync += read_pointer.eq(write_pointer - trigger_location) + with m.Else(): + m.d.sync += read_pointer.eq( + write_pointer - trigger_location + sample_depth + ) + + # ok that's all for horrible + + with m.If(state == States.CAPTURING): + # Non- incremental modes + with m.If(trigger_mode != TriggerModes.INCREMENTAL): with m.If(next_write_pointer == read_pointer): - m.d.comb += write_enable.eq(0) - m.d.comb += write_pointer.eq(latch_write_pointer) - m.d.comb += next_state.eq(States.CAPTURED) + m.d.sync += write_enable.eq(0) + m.d.sync += state.eq(States.CAPTURED) with m.Else(): - m.d.comb += write_pointer.eq(next_write_pointer) + m.d.sync += write_pointer.eq(next_write_pointer) - with m.Elif(state == States.CAPTURED): - m.d.comb += next_state.eq(States.CAPTURED) - m.d.comb += read_pointer.eq(latch_read_pointer) - m.d.comb += write_pointer.eq(latch_write_pointer) - m.d.comb += write_enable.eq(0) + # Incremental mode + with m.Else(): + with m.If(self.trigger): + with m.If(next_write_pointer == read_pointer): + m.d.sync += write_enable.eq(0) + m.d.sync += state.eq(States.CAPTURED) - # --- Immediate Trigger Mode --- - with m.If(self.r.trigger_mode == TriggerModes.IMMEDIATE): - m.d.comb += read_pointer.eq(0) - with m.If(self.r.state == States.IDLE): - m.d.comb += write_enable.eq(0) - m.d.comb += write_pointer.eq(0) - m.d.comb += next_state.eq(States.IDLE) - - # Rising edge of request_start beings the capture: - with m.If((request_start) & (~prev_request_start)): - m.d.comb += write_enable.eq(1) - m.d.comb += next_state.eq(States.CAPTURING) - - with m.Elif(state == States.CAPTURING): - m.d.comb += write_enable.eq(1) - m.d.comb += next_state.eq(States.CAPTURING) - m.d.comb += write_pointer.eq(next_write_pointer) - - with m.If(next_write_pointer == read_pointer): - m.d.comb += write_enable.eq(0) - m.d.comb += write_pointer.eq(latch_write_pointer) - m.d.comb += next_state.eq(States.CAPTURED) - - with m.Elif(state == States.CAPTURED): - m.d.comb += write_enable.eq(0) - m.d.comb += write_pointer.eq(latch_write_pointer) - m.d.comb += next_state.eq(States.CAPTURED) - - # --- Incremental Trigger Mode --- - with m.If(self.r.trigger_mode == TriggerModes.INCREMENTAL): - with m.If(state == States.IDLE): - m.d.comb += write_enable.eq(0) - m.d.comb += write_pointer.eq(0) - m.d.comb += read_pointer.eq(0) - m.d.comb += next_state.eq(States.IDLE) - - # Rising edge of request_start beings the capture: - with m.If((request_start) & (~prev_request_start)): - m.d.comb += write_enable.eq(self.trigger) - m.d.comb += next_state.eq(States.CAPTURING) - - with m.Elif(state == States.CAPTURING): - m.d.comb += read_pointer.eq(0) - m.d.comb += next_state.eq(States.CAPTURING) - m.d.comb += write_enable.eq(self.trigger) - - with m.If(latch_write_enable): - m.d.comb += write_pointer.eq(next_write_pointer) - with m.Else(): - m.d.comb += write_pointer.eq(latch_write_pointer) - - with m.If((self.trigger) & (next_write_pointer == read_pointer)): - m.d.comb += write_pointer.eq(latch_write_pointer) - m.d.comb += next_state.eq(States.CAPTURED) - - with m.Elif(state == States.CAPTURED): - m.d.comb += next_state.eq(States.CAPTURED) - m.d.comb += read_pointer.eq(latch_read_pointer) - m.d.comb += write_pointer.eq(latch_write_pointer) - m.d.comb += write_enable.eq(0) + with m.Else(): + m.d.sync += write_pointer.eq(next_write_pointer) # Regardless of trigger mode, go back to IDLE if request_stop is pulsed with m.If((request_stop) & (~prev_request_stop)): - m.d.comb += next_state.eq(States.IDLE) + m.d.sync += state.eq(States.IDLE) return m diff --git a/test/test_logic_analyzer_fsm_sim.py b/test/test_logic_analyzer_fsm_sim.py index 24d8215..c2b4e70 100644 --- a/test/test_logic_analyzer_fsm_sim.py +++ b/test/test_logic_analyzer_fsm_sim.py @@ -2,25 +2,6 @@ from amaranth.sim import Simulator from manta.logic_analyzer import * from manta.utils import * -""" -what do we want this to do? - -we want to run a capture in single shot mode, immediate mode, and incremental mode - - -single-shot case: -- exactly the right number of samples are taken -- we only start taking samples once captured - -immediate case: -- exactly the right number of samples are taken -- we only start taking samples once captured - -incremental case: -- exactly the right number of samples are taken -- we only take samples when trig is asserted - -""" config = {"sample_depth": 8} fsm = LogicAnalyzerFSM(config, base_addr=0, interface=None) @@ -84,8 +65,9 @@ def test_single_shot_wait_for_trigger(): yield fsm.r.trigger_location.eq(4) yield fsm.r.request_start.eq(1) yield + yield - # Check that write_enable is asserted on the same edge as request_start + # Check that write_enable is asserted a cycle after request_start if not (yield fsm.write_enable): raise ValueError @@ -104,28 +86,15 @@ def test_single_shot_wait_for_trigger(): yield - # Wait a few cycles before triggering: + # Wait a few cycles before triggering for _ in range(10): - if (rp + 3) % fsm.config["sample_depth"] != wp: - raise ValueError - yield # Provide the trigger, and check that the capture completes 4 cycles later yield fsm.trigger.eq(1) yield - rp_start = yield fsm.r.read_pointer for i in range(4): - rp = yield fsm.r.read_pointer - wp = yield fsm.r.write_pointer - - if rp != rp_start: - raise ValueError - - if (rp_start + 4 + i) % fsm.config["sample_depth"] != wp: - raise ValueError - yield # Wait one clock cycle (to let BRAM contents cycle in) @@ -150,8 +119,9 @@ def test_immediate(): yield fsm.r.trigger_mode.eq(TriggerModes.IMMEDIATE) yield fsm.r.request_start.eq(1) yield + yield - # Check that write_enable is asserted on the same edge as request_start + # Check that write_enable is asserted a cycle after request_start if not (yield fsm.write_enable): raise ValueError @@ -191,10 +161,11 @@ def test_incremental(): yield fsm.r.trigger_mode.eq(TriggerModes.INCREMENTAL) yield fsm.r.request_start.eq(1) yield + yield # Check that write_enable is asserted on the same edge as request_start - # if not (yield fsm.write_enable): - # raise ValueError + if not (yield fsm.write_enable): + raise ValueError for _ in range(10): for _ in range(3): @@ -205,9 +176,9 @@ def test_incremental(): yield fsm.trigger.eq(0) yield - # # Check that state is CAPTURED - # if (yield fsm.r.state) != States.CAPTURED: - # raise ValueError + # Check that state is CAPTURED + if (yield fsm.r.state) != States.CAPTURED: + raise ValueError simulate(fsm, testbench, "incremental.vcd") @@ -226,6 +197,7 @@ def test_single_shot_write_enable(): # Start the FSM, ensure write enable is asserted throughout the capture yield fsm.r.request_start.eq(1) yield + yield for _ in range(fsm.config["sample_depth"]): if not (yield fsm.write_enable): @@ -262,6 +234,7 @@ def test_immediate_write_enable(): # Start the FSM, ensure write enable is asserted throughout the capture yield fsm.r.request_start.eq(1) yield + yield for _ in range(fsm.config["sample_depth"]): if not (yield fsm.write_enable): From 510bae6f38f81b4a934806e7bbe9ecf2cd26fb75 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 22 Jan 2024 00:03:54 -0800 Subject: [PATCH 38/89] add MATLAB fpga data capture to alternatives, thanks nathan --- doc/alternatives.md | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/doc/alternatives.md b/doc/alternatives.md index e7dcd11..7758656 100644 --- a/doc/alternatives.md +++ b/doc/alternatives.md @@ -58,4 +58,11 @@ An embedded logic analyzer for Lattice FPGAs, provided as part of the Diamond de Unlike other entries in this list, Opal Kelly's FrontPanel SDK is not marketed as a debugger (although it can be used as such). Instead, it's designed to provide a host computer with a real time interface to FGPA signals, and present them on a graphical “front panel". These front panels exist as a GUI window on the host, and contain buttons, knobs, and indicators, much like a LabVIEW virtual instrument. Communication between the host and FPGA is accomplished with either USB or PCIe. Bindings for hosts running Windows, macOS, and Linux are provided, and target C, C++, C#, Python, Java, Ruby, and MATLAB. The FrontPanel SDK differs from other debuggers in that it provides a skeleton module into which the user logic is instantiated, instead of being instantiated inside the user's logic. - [Documentation](https://docs.opalkelly.com/fpsdk/) -- [User's Guide](https://assets00.opalkelly.com/library/FrontPanel-UM.pdf) \ No newline at end of file +- [User's Guide](https://assets00.opalkelly.com/library/FrontPanel-UM.pdf) + + +### MATLAB FPGA Data Capture + +An embedded logic analyzer for Xilinx and Altera FPGAs, provided as part of MATLAB. Communication between the host and FPGA is accomplished with JTAG, but Ethernet is supported for Xilinx FPGAs. Notably, this tool allows for data to be captured and used directly inside MATLAB, which also includes a framework for FPGA-in-the-loop testing. It also provides an AXI manager IP block that allows for reads and writes to an AXI memory map from MATLAB. This IP supports PCI Express on Xilinx FPGAs, in addition to JTAG and Ethernet. + +- [Documentation](https://www.mathworks.com/help/hdlverifier/fpga-data-capture-xilinx.html) \ No newline at end of file From a75a6a3ccf266802552bc065d8aa3cfdde196799 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 28 Jan 2024 21:54:46 -0800 Subject: [PATCH 39/89] add first pass at ethernet --- project_0/build.tcl | 65 ++++++ ethernet_test.yml => project_0/manta.yaml | 8 +- project_0/manta_test.yaml | 12 + project_0/stream.py | 68 ++++++ project_0/test.yml | 28 +++ project_0/xdc/top_level.xdc | 260 ++++++++++++++++++++++ project_1/build.tcl | 65 ++++++ project_1/liteeth_config.yml | 28 +++ project_1/manta.yaml | 15 ++ project_1/stream.py | 17 ++ project_1/xdc/top_level.xdc | 260 ++++++++++++++++++++++ src/manta/ethernet.py | 171 ++++++++++++++ src/manta/io_core.py | 10 +- src/manta/manta.py | 2 +- src/manta/utils.py | 9 +- test/test_source_bridge_sim.py | 39 ++++ 16 files changed, 1049 insertions(+), 8 deletions(-) create mode 100644 project_0/build.tcl rename ethernet_test.yml => project_0/manta.yaml (62%) create mode 100644 project_0/manta_test.yaml create mode 100644 project_0/stream.py create mode 100644 project_0/test.yml create mode 100644 project_0/xdc/top_level.xdc create mode 100644 project_1/build.tcl create mode 100644 project_1/liteeth_config.yml create mode 100644 project_1/manta.yaml create mode 100644 project_1/stream.py create mode 100644 project_1/xdc/top_level.xdc create mode 100644 src/manta/ethernet.py create mode 100644 test/test_source_bridge_sim.py diff --git a/project_0/build.tcl b/project_0/build.tcl new file mode 100644 index 0000000..d0441d6 --- /dev/null +++ b/project_0/build.tcl @@ -0,0 +1,65 @@ +#!/usr/bin/tclsh +# jay's build script +# pass -tclargs -d to generate diagnostics + +# switches + +set partNum xc7a100tcsg324-1 +set outputDir output_files +set verbose 0 + +if { $argc > 0 } { + if { $argc == 1 && [string compare [ lindex $argv 0 ] "-d"] == 0 } { + set verbose 1 + } else { + puts "usage: $argv0 \[-d\]" + exit 1 + } +} + +file mkdir $outputDir +set files [glob -nocomplain "$outputDir/*"] +if {[llength $files] != 0} { + file delete -force {*}[glob -directory $outputDir *]; +} + +read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ] +read_xdc ./xdc/top_level.xdc + +set_part $partNum + +# synth +synth_design -top top_level -part $partNum -verbose +report_utilization -file $outputDir/post_synth_util.rpt +if { $verbose } { + report_timing_summary -file $outputDir/post_synth_timing_summary.rpt + report_timing -file $outputDir/post_synth_timing.rpt +} + +# place +opt_design +place_design +phys_opt_design +report_utilization -file $outputDir/post_place_util.rpt + +if { $verbose } { + report_clock_utilization -file $outputDir/clock_util.rpt + report_timing_summary -file $outputDir/post_place_timing_summary.rpt + report_timing -file $outputDir/post_place_timing.rpt +} + +# route design and generate bitstream + +route_design -directive Explore +write_bitstream -force $outputDir/final.bit + +if { $verbose } { + report_route_status -file $outputDir/post_route_status.rpt + report_timing_summary -file $outputDir/post_route_timing_summary.rpt + report_timing -file $outputDir/post_route_timing.rpt + report_power -file $outputDir/post_route_power.rpt + report_drc -file $outputDir/post_imp_drc.rpt + write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true + # unfortunately, does nothing + show_schematic [ get_cells ] +} \ No newline at end of file diff --git a/ethernet_test.yml b/project_0/manta.yaml similarity index 62% rename from ethernet_test.yml rename to project_0/manta.yaml index 9ca6abf..4fd772f 100644 --- a/ethernet_test.yml +++ b/project_0/manta.yaml @@ -7,13 +7,17 @@ cores: dhcp_done: 1 dhcp_ip_address: 32 dhcp_timeout: 1 + led: 16 outputs: dhcp_start: 1 ip_address: 32 - + udp_port: 16 + udp0_ip_address: 32 + udp0_sink_data: 32 + udp0_sink_valid: 1 uart: port: "/dev/ttyUSB1" baudrate: 115200 - clock_freq: 12000000 + clock_freq: 50000000 diff --git a/project_0/manta_test.yaml b/project_0/manta_test.yaml new file mode 100644 index 0000000..a7a83c4 --- /dev/null +++ b/project_0/manta_test.yaml @@ -0,0 +1,12 @@ +--- +cores: + io_core: + type: io + + inputs: + foobar: 1 + + +ethernet: + desired_fpga_ip: "192.168.0.110" + host_ip: "192.168.0.100" diff --git a/project_0/stream.py b/project_0/stream.py new file mode 100644 index 0000000..038d43e --- /dev/null +++ b/project_0/stream.py @@ -0,0 +1,68 @@ +from manta import Manta +import socket +import time + + +def configure(ip_address, udp_port): + m = Manta("manta.yaml") + + # Compute IP address + octets = [bin(int(o))[2:].zfill(8) for o in ip_address.split(".")] + ip_binary = int("".join(octets), 2) + + # Set IP address + m.io_core.set_probe("ip_address", ip_binary) + m.io_core.set_probe("dhcp_start", 1) + m.io_core.set_probe("dhcp_start", 0) + while m.io_core.get_probe("dhcp_done") != 1: + pass + print(m.io_core.get_probe("dhcp_ip_address")) + + # Set UDP port + m.io_core.set_probe("udp_port", udp_port) + + +def leds_test(ip_address, udp_port): + m = Manta("manta.yaml") + sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + for i in range(0xFF): + sock.sendto(int(i).to_bytes(1, byteorder="big"), (ip_address, udp_port)) + led = m.io_core.get_probe("led") + print(f"i:{i} led:{led}") + time.sleep(0.2) + + +def send_variable_length_test(): + sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + for i in range(0xFF): + sock.sendto(int(i).to_bytes(i, byteorder="big"), (ip_address, udp_port)) + time.sleep(0.2) + + +def send_to_host_test(host_ip, udp_port): + m = Manta("manta.yaml") + + # Set UDP port + m.io_core.set_probe("udp_port", udp_port) + + # Compute and set destination IP address: + octets = [bin(int(o))[2:].zfill(8) for o in host_ip.split(".")] + ip_binary = int("".join(octets), 2) + m.io_core.set_probe("udp0_ip_address", ip_binary) + + # Send data + m.io_core.set_probe("udp0_sink_data", 0x21_43_65_87) + m.io_core.set_probe("udp0_sink_valid", 1) + m.io_core.set_probe("udp0_sink_valid", 0) + + +if __name__ == "__main__": + ip_address = "192.168.0.110" + udp_port = 42069 + + configure(ip_address, udp_port) + # time.sleep(0.2) + # for _ in range(64): + # send_to_host_test("192.168.0.107", 42069) + # leds_test(ip_address, udp_port) + send_variable_length_test() diff --git a/project_0/test.yml b/project_0/test.yml new file mode 100644 index 0000000..666a399 --- /dev/null +++ b/project_0/test.yml @@ -0,0 +1,28 @@ +# +# This file is part of LiteEth. +# +# Copyright (c) 2020-2022 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +# PHY -------------------------------------------------------------------------- +phy: LiteEthPHYRMII +vendor: xilinx +toolchain: vivado + +# Core ------------------------------------------------------------------------- +refclk_freq: 50e6 +clk_freq: 50e6 +core: udp +mac_address: 0x10e2d5000000 +dhcp: True +data_width: 8 + +# UDP Ports -------------------------------------------------------------------- +udp_ports: { + "udp0": { + "udp_port" : 2000, # Static Params. + "data_width" : 32, + "tx_fifo_depth" : 64, + "rx_fifo_depth" : 64, + }, +} diff --git a/project_0/xdc/top_level.xdc b/project_0/xdc/top_level.xdc new file mode 100644 index 0000000..7a77074 --- /dev/null +++ b/project_0/xdc/top_level.xdc @@ -0,0 +1,260 @@ +## R1.0 2019-08-27 +## Updated by jodalyst in 2020-2022 +## all inputs/outputs changed to lowercase; arrays start with zero. +## system clock renamed to clk_100mhz +## ja, jb, jc, jd renamed to 0-7 +## xa port renamed 0-3 +## seven segments renamed to a,b,c,d,e,f,dp + +## This file is a general .xdc for the Nexys4 DDR Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; + + +##Switches + +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc +set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu +set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +# +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +# +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + diff --git a/project_1/build.tcl b/project_1/build.tcl new file mode 100644 index 0000000..d0441d6 --- /dev/null +++ b/project_1/build.tcl @@ -0,0 +1,65 @@ +#!/usr/bin/tclsh +# jay's build script +# pass -tclargs -d to generate diagnostics + +# switches + +set partNum xc7a100tcsg324-1 +set outputDir output_files +set verbose 0 + +if { $argc > 0 } { + if { $argc == 1 && [string compare [ lindex $argv 0 ] "-d"] == 0 } { + set verbose 1 + } else { + puts "usage: $argv0 \[-d\]" + exit 1 + } +} + +file mkdir $outputDir +set files [glob -nocomplain "$outputDir/*"] +if {[llength $files] != 0} { + file delete -force {*}[glob -directory $outputDir *]; +} + +read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ] +read_xdc ./xdc/top_level.xdc + +set_part $partNum + +# synth +synth_design -top top_level -part $partNum -verbose +report_utilization -file $outputDir/post_synth_util.rpt +if { $verbose } { + report_timing_summary -file $outputDir/post_synth_timing_summary.rpt + report_timing -file $outputDir/post_synth_timing.rpt +} + +# place +opt_design +place_design +phys_opt_design +report_utilization -file $outputDir/post_place_util.rpt + +if { $verbose } { + report_clock_utilization -file $outputDir/clock_util.rpt + report_timing_summary -file $outputDir/post_place_timing_summary.rpt + report_timing -file $outputDir/post_place_timing.rpt +} + +# route design and generate bitstream + +route_design -directive Explore +write_bitstream -force $outputDir/final.bit + +if { $verbose } { + report_route_status -file $outputDir/post_route_status.rpt + report_timing_summary -file $outputDir/post_route_timing_summary.rpt + report_timing -file $outputDir/post_route_timing.rpt + report_power -file $outputDir/post_route_power.rpt + report_drc -file $outputDir/post_imp_drc.rpt + write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true + # unfortunately, does nothing + show_schematic [ get_cells ] +} \ No newline at end of file diff --git a/project_1/liteeth_config.yml b/project_1/liteeth_config.yml new file mode 100644 index 0000000..666a399 --- /dev/null +++ b/project_1/liteeth_config.yml @@ -0,0 +1,28 @@ +# +# This file is part of LiteEth. +# +# Copyright (c) 2020-2022 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +# PHY -------------------------------------------------------------------------- +phy: LiteEthPHYRMII +vendor: xilinx +toolchain: vivado + +# Core ------------------------------------------------------------------------- +refclk_freq: 50e6 +clk_freq: 50e6 +core: udp +mac_address: 0x10e2d5000000 +dhcp: True +data_width: 8 + +# UDP Ports -------------------------------------------------------------------- +udp_ports: { + "udp0": { + "udp_port" : 2000, # Static Params. + "data_width" : 32, + "tx_fifo_depth" : 64, + "rx_fifo_depth" : 64, + }, +} diff --git a/project_1/manta.yaml b/project_1/manta.yaml new file mode 100644 index 0000000..1e9cc7a --- /dev/null +++ b/project_1/manta.yaml @@ -0,0 +1,15 @@ +--- +cores: + io_core: + type: io + + inputs: + sw: 16 + + outputs: + led: 16 + +ethernet: + desired_fpga_ip: "192.168.0.110" + host_ip: "192.168.0.107" + udp_port: 42069 diff --git a/project_1/stream.py b/project_1/stream.py new file mode 100644 index 0000000..5a3c542 --- /dev/null +++ b/project_1/stream.py @@ -0,0 +1,17 @@ +from manta import Manta +import socket +import time + +if __name__ == "__main__": + ip_address = "192.168.0.110" + udp_port = 42069 + + sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + + for i in range(256): + data = [0, 0] + data = [int(d).to_bytes(4, byteorder="big") for d in data] + data = b"".join(data) + print(data) + sock.sendto(data, (ip_address, udp_port)) + # time.sleep(0.2) diff --git a/project_1/xdc/top_level.xdc b/project_1/xdc/top_level.xdc new file mode 100644 index 0000000..7a77074 --- /dev/null +++ b/project_1/xdc/top_level.xdc @@ -0,0 +1,260 @@ +## R1.0 2019-08-27 +## Updated by jodalyst in 2020-2022 +## all inputs/outputs changed to lowercase; arrays start with zero. +## system clock renamed to clk_100mhz +## ja, jb, jc, jd renamed to 0-7 +## xa port renamed 0-3 +## seven segments renamed to a,b,c,d,e,f,dp + +## This file is a general .xdc for the Nexys4 DDR Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; + + +##Switches + +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc +set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu +set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +# +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +# +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + diff --git a/src/manta/ethernet.py b/src/manta/ethernet.py new file mode 100644 index 0000000..ae348b5 --- /dev/null +++ b/src/manta/ethernet.py @@ -0,0 +1,171 @@ +from amaranth import * +from manta.utils import * + + +class EthernetInterface(Elaboratable): + def __init__(self, config): + self.desired_fpga_ip = config["desired_fpga_ip"] + self.host_ip = config["host_ip"] + self.udp_port = config["udp_port"] + + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) + + self.rmii_clocks_ref_clk = Signal() + self.rmii_crs_dv = Signal() + self.rmii_mdc = Signal() + self.rmii_mdio = Signal() + self.rmii_rst_n = Signal() + self.rmii_rx_data = Signal(2) + self.rmii_tx_data = Signal(2) + self.rmii_tx_en = Signal() + + self.dhcp_start = Signal() + self.dhcp_timer = Signal(range(int(100e6))) + + self.source_data = Signal(32) + self.source_last = Signal() + self.source_ready = Signal() + self.source_valid = Signal() + + self.sink_data = Signal(32) + self.sink_last = Signal() + self.sink_ready = Signal() + self.sink_valid = Signal() + + def get_top_level_ports(self): + ports = [ + self.rmii_clocks_ref_clk, + self.rmii_crs_dv, + self.rmii_mdc, + self.rmii_mdio, + self.rmii_rst_n, + self.rmii_rx_data, + self.rmii_tx_data, + self.rmii_tx_en, + ] + return ports + + def binarize_ip_addr(self, ip_addr): + octets = [bin(int(o))[2:].zfill(8) for o in ip_addr.split(".")] + return int("".join(octets), 2) + + def elaborate(self, platform): + m = Module() + + with m.If(self.dhcp_timer < 15): + m.d.sync += self.dhcp_timer.eq(self.dhcp_timer + 1) + + m.d.sync += self.dhcp_start.eq(self.dhcp_timer == 14) + + m.submodules.liteeth = Instance( + "liteeth_core", + ("i", "sys_clock", ClockSignal()), + ("i", "sys_reset", ResetSignal()), + # PHY connection + ("i", "rmii_clocks_ref_clk", self.rmii_clocks_ref_clk), + ("i", "rmii_crs_dv", self.rmii_crs_dv), + ("o", "rmii_mdc", self.rmii_mdc), + ("io", "rmii_mdio", self.rmii_mdio), + ("o", "rmii_rst_n", self.rmii_rst_n), + ("i", "rmii_rx_data", self.rmii_rx_data), + ("o", "rmii_tx_data", self.rmii_tx_data), + ("o", "rmii_tx_en", self.rmii_tx_en), + # DHCP + # ("o", "dhcp_done", 1), + # ("o", "dhcp_ip_address", 1), + ("i", "dhcp_start", self.dhcp_start), + # ("o", "dhcp_timeout", 1), + ("i", "ip_address", self.binarize_ip_addr(self.desired_fpga_ip)), + # UDP Port + ("i", "udp0_udp_port", self.udp_port), + # UDP from host + ("o", "udp0_source_data", self.source_data), + # ("o", "udp0_source_error", 1), + ("o", "udp0_source_last", self.source_last), + ("i", "udp0_source_ready", self.source_ready), + ("o", "udp0_source_valid", self.source_valid), + # UDP back to host + ("i", "udp0_ip_address", self.binarize_ip_addr(self.host_ip)), + ("i", "udp0_sink_data", self.sink_data), + ("i", "udp0_sink_last", self.sink_last), + ("o", "udp0_sink_ready", self.sink_ready), + ("i", "udp0_sink_valid", self.sink_valid), + ) + + m.submodules.source_bridge = source_bridge = UDPSourceBridge() + m.submodules.sink_bridge = sink_bridge = UDPSinkBridge() + + m.d.comb += source_bridge.data_i.eq(self.source_data) + m.d.comb += source_bridge.last_i.eq(self.source_last) + m.d.comb += self.source_ready.eq(source_bridge.ready_o) + m.d.comb += source_bridge.valid_i.eq(self.source_valid) + + m.d.comb += self.sink_data.eq(sink_bridge.data_o) + m.d.comb += self.sink_last.eq(sink_bridge.last_o) + m.d.comb += sink_bridge.ready_i.eq(self.sink_ready) + m.d.comb += self.sink_valid.eq(sink_bridge.valid_o) + + m.d.comb += sink_bridge.bus_i.eq(self.bus_i) + m.d.comb += self.bus_o.eq(source_bridge.bus_o) + + return m + + +class UDPSourceBridge(Elaboratable): + def __init__(self): + self.bus_o = Signal(InternalBus()) + + self.data_i = Signal(32) + self.last_i = Signal() + self.ready_o = Signal() + self.valid_i = Signal() + + def elaborate(self, platform): + m = Module() + + state = Signal() # can either be 0, for read/write, or 1, for data + rw_buf = Signal().like(self.bus_o.rw) + + # Can always take more data + m.d.sync += self.ready_o.eq(1) + + m.d.sync += self.bus_o.eq(0) + with m.If(self.valid_i): + m.d.sync += state.eq(~state) + + with m.If(state == 0): + m.d.sync += rw_buf.eq(self.data_i) + + with m.Else(): + m.d.sync += self.bus_o.addr.eq(self.data_i[:16]) + m.d.sync += self.bus_o.data.eq(self.data_i[16:]) + m.d.sync += self.bus_o.rw.eq(rw_buf) + m.d.sync += self.bus_o.valid.eq(1) + # m.d.sync += self.bus_o.last.eq(self.last_i) + + return m + + +class UDPSinkBridge(Elaboratable): + def __init__(self): + self.bus_i = Signal(InternalBus()) + + self.data_o = Signal(32) + self.last_o = Signal() + self.ready_i = Signal() + self.valid_o = Signal() + + def elaborate(self, platform): + m = Module() + + m.d.sync += self.data_o.eq(0) + m.d.sync += self.last_o.eq(0) + m.d.sync += self.valid_o.eq(0) + + with m.If(self.bus_i.valid): + m.d.sync += self.data_o.eq(self.bus_i.data) + # m.d.sync += self.last_o.eq(self.bus_i.last) + m.d.sync += self.valid_o.eq(1) + + return m diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 08e7633..40009df 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -214,11 +214,13 @@ class IOCore(Elaboratable): def get_top_level_ports(self): ports = [] - for name in self.config["inputs"].keys(): - ports.append(getattr(self, name)) + if "inputs" in self.config: + for name in self.config["inputs"].keys(): + ports.append(getattr(self, name)) - for name in self.config["outputs"].keys(): - ports.append(getattr(self, name)) + if "outputs" in self.config: + for name in self.config["outputs"].keys(): + ports.append(getattr(self, name)) return ports diff --git a/src/manta/manta.py b/src/manta/manta.py index 8e9e997..c503fd2 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -1,7 +1,7 @@ from amaranth import * from .uart import UARTInterface -# from .ethernet import EthernetInterface +from .ethernet import EthernetInterface from .io_core import IOCore from .memory_core import ReadOnlyMemoryCore from .logic_analyzer import LogicAnalyzerCore diff --git a/src/manta/utils.py b/src/manta/utils.py index 98ae766..7aa3625 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -11,7 +11,14 @@ class InternalBus(data.StructLayout): """ def __init__(self): - super().__init__({"addr": 16, "data": 16, "rw": 1, "valid": 1}) + super().__init__( + { + "addr": 16, + "data": 16, + "rw": 1, + "valid": 1, + } + ) def warn(message): diff --git a/test/test_source_bridge_sim.py b/test/test_source_bridge_sim.py new file mode 100644 index 0000000..031dec8 --- /dev/null +++ b/test/test_source_bridge_sim.py @@ -0,0 +1,39 @@ +from amaranth.sim import Simulator +from manta.ethernet import UDPSourceBridge +from manta.utils import * + + +source_bridge = UDPSourceBridge() + + +def test_normie_ops(): + def testbench(): + yield source_bridge.data_i.eq(0) + yield source_bridge.last_i.eq(0) + yield source_bridge.valid_i.eq(0) + yield + yield + + yield source_bridge.data_i.eq(0x0000_0001) + yield source_bridge.valid_i.eq(1) + yield + yield source_bridge.data_i.eq(0x1234_5678) + yield + yield source_bridge.valid_i.eq(0) + yield + yield + + yield source_bridge.valid_i.eq(1) + yield source_bridge.data_i.eq(0x0000_0001) + yield + yield source_bridge.data_i.eq(0x90AB_CDEF) + yield + yield source_bridge.data_i.eq(0x0000_0000) + yield + yield source_bridge.data_i.eq(0x1234_5678) + yield + yield source_bridge.valid_i.eq(0) + yield + yield + + simulate(source_bridge, testbench, "source_bridge.vcd") From a5afad69927f281dd5903ed09e4dd55f88c79ac4 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 4 Feb 2024 14:29:39 -0800 Subject: [PATCH 40/89] io core with ethernet working! --- .gitignore | 12 +++++- project_0/stream.py | 2 +- project_1/manta.yaml | 16 ++++++- project_1/stream.py | 49 +++++++++++++++------ project_1/test.py | 5 +++ src/manta/ethernet.py | 87 +++++++++++++++++++++++++++++++++++--- src/manta/uart/__init__.py | 5 ++- src/manta/utils.py | 1 + 8 files changed, 151 insertions(+), 26 deletions(-) create mode 100644 project_1/test.py diff --git a/.gitignore b/.gitignore index e85d6af..5dc2efa 100644 --- a/.gitignore +++ b/.gitignore @@ -13,4 +13,14 @@ build/ *.v *.sv *.vcd -*.out \ No newline at end of file +*.out + +# Vivado files from the occasional debugging sesh +*.log +*.jou +*.rpt +*.bin +*.bit +*.out +*.xdc +.Xil/* \ No newline at end of file diff --git a/project_0/stream.py b/project_0/stream.py index 038d43e..82a17c8 100644 --- a/project_0/stream.py +++ b/project_0/stream.py @@ -65,4 +65,4 @@ if __name__ == "__main__": # for _ in range(64): # send_to_host_test("192.168.0.107", 42069) # leds_test(ip_address, udp_port) - send_variable_length_test() + # send_variable_length_test() diff --git a/project_1/manta.yaml b/project_1/manta.yaml index 1e9cc7a..23f7b6d 100644 --- a/project_1/manta.yaml +++ b/project_1/manta.yaml @@ -10,6 +10,18 @@ cores: led: 16 ethernet: - desired_fpga_ip: "192.168.0.110" - host_ip: "192.168.0.107" + phy: LiteEthPHYRMII + vendor: xilinx + toolchain: vivado + + refclk_freq: 50e6 + clk_freq: 50e6 + + fpga_ip_addr: "192.168.0.110" + host_ip_addr: "192.168.0.100" udp_port: 42069 + + core: udp # we handle this + mac_address: # this should be optional + dhcp: # should be optional, default to true? + data_width: 32 # using DHCP will force this to 32, but for ease of use we should design for that even for static IP devices diff --git a/project_1/stream.py b/project_1/stream.py index 5a3c542..ae56e49 100644 --- a/project_1/stream.py +++ b/project_1/stream.py @@ -1,17 +1,40 @@ -from manta import Manta import socket -import time - -if __name__ == "__main__": - ip_address = "192.168.0.110" - udp_port = 42069 +def write(addrs, datas): + bytes_out = b"" + for addr, data in zip(addrs, datas): + bytes_out += int(1).to_bytes(4, byteorder="little") + bytes_out += int(addr).to_bytes(2, byteorder="little") + bytes_out += int(data).to_bytes(2, byteorder="little") sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + sock.sendto(bytes_out, (fpga_ip_addr, udp_port)) - for i in range(256): - data = [0, 0] - data = [int(d).to_bytes(4, byteorder="big") for d in data] - data = b"".join(data) - print(data) - sock.sendto(data, (ip_address, udp_port)) - # time.sleep(0.2) +def read(addrs): + bytes_out = b"" + for addr in addrs: + bytes_out += int(0).to_bytes(4, byteorder="little") + bytes_out += int(addr).to_bytes(2, byteorder="little") + bytes_out += int(0).to_bytes(2, byteorder="little") + + sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + sock.bind((host_ip_addr, udp_port)) + sock.sendto(bytes_out, (fpga_ip_addr, udp_port)) + data, addr = sock.recvfrom(1024) + + return int.from_bytes(data, "little") + +if __name__ == "__main__": + host_ip_addr = "192.168.0.100" + fpga_ip_addr = "192.168.0.110" + udp_port = 42069 + + for i in range(2**16): + write([0x0000],[0x0000]) + write([0x0000],[0x0001]) + write([0x0000],[0x0000]) + write([0x0002],[i]) + # print(read([0x0002])) + # write([0x0002],[0b0101_0101_0101_0101]) + # write([0x0000],[0x0000]) + # write([0x0000],[0x0001]) + # write([0x0000],[0x0000]) diff --git a/project_1/test.py b/project_1/test.py new file mode 100644 index 0000000..3a725ad --- /dev/null +++ b/project_1/test.py @@ -0,0 +1,5 @@ +from manta import Manta +m = Manta("manta.yaml") + +print(bin(m.io_core.get_probe("sw"))) +m.io_core.set_probe("led", 4) \ No newline at end of file diff --git a/src/manta/ethernet.py b/src/manta/ethernet.py index ae348b5..9f174fd 100644 --- a/src/manta/ethernet.py +++ b/src/manta/ethernet.py @@ -1,11 +1,12 @@ from amaranth import * from manta.utils import * +import socket class EthernetInterface(Elaboratable): def __init__(self, config): - self.desired_fpga_ip = config["desired_fpga_ip"] - self.host_ip = config["host_ip"] + self.fpga_ip_addr = config["fpga_ip_addr"] + self.host_ip_addr = config["host_ip_addr"] self.udp_port = config["udp_port"] self.bus_i = Signal(InternalBus()) @@ -76,7 +77,7 @@ class EthernetInterface(Elaboratable): # ("o", "dhcp_ip_address", 1), ("i", "dhcp_start", self.dhcp_start), # ("o", "dhcp_timeout", 1), - ("i", "ip_address", self.binarize_ip_addr(self.desired_fpga_ip)), + ("i", "ip_address", self.binarize_ip_addr(self.fpga_ip_addr)), # UDP Port ("i", "udp0_udp_port", self.udp_port), # UDP from host @@ -86,7 +87,7 @@ class EthernetInterface(Elaboratable): ("i", "udp0_source_ready", self.source_ready), ("o", "udp0_source_valid", self.source_valid), # UDP back to host - ("i", "udp0_ip_address", self.binarize_ip_addr(self.host_ip)), + ("i", "udp0_ip_address", self.binarize_ip_addr(self.host_ip_addr)), ("i", "udp0_sink_data", self.sink_data), ("i", "udp0_sink_last", self.sink_last), ("o", "udp0_sink_ready", self.sink_ready), @@ -111,6 +112,78 @@ class EthernetInterface(Elaboratable): return m + def read(self, addrs): + """ + Read the data stored in a set of address on Manta's internal memory. Addresses + must be specified as either integers or a list of integers. + """ + + # Handle a single integer address + if isinstance(addrs, int): + return self.read([addrs])[0] + + # Make sure all list elements are integers + if not all(isinstance(a, int) for a in addrs): + raise ValueError("Read address must be an integer or list of integers.") + + # Send read requests, and get responses + sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + sock.bind((self.host_ip_addr, self.udp_port)) + chunk_size = 128 + addr_chunks = split_into_chunks(addrs, chunk_size) + datas = [] + + for addr_chunk in addr_chunks: + bytes_out = b"" + for addr in addr_chunk: + bytes_out += int(0).to_bytes(4, byteorder="little") + bytes_out += int(addr).to_bytes(2, byteorder="little") + bytes_out += int(0).to_bytes(2, byteorder="little") + + sock.sendto(bytes_out, (self.fpga_ip_addr, self.udp_port)) + data, addr = sock.recvfrom(4 * chunk_size) + + # Split into groups of four bytes + datas += [int.from_bytes(d, "little") for d in split_into_chunks(data, 4)] + + return datas + + def write(self, addrs, datas): + """ + Write the provided data into the provided addresses in Manta's internal memory. + Addresses and data must be specified as either integers or a list of integers. + """ + + # Handle a single integer address and data + if isinstance(addrs, int) and isinstance(datas, int): + return self.write([addrs], [datas]) + + # Make sure address and datas are all integers + if not isinstance(addrs, list) or not isinstance(datas, list): + raise ValueError( + "Write addresses and data must be an integer or list of integers." + ) + + if not all(isinstance(a, int) for a in addrs): + raise ValueError("Write addresses must be all be integers.") + + if not all(isinstance(d, int) for d in datas): + raise ValueError("Write data must all be integers.") + + # Since the FPGA doesn't issue any responses to write requests, we + # the host's input buffer isn't written to, and we don't need to + # send the data as chunks as the to avoid overflowing the input buffer. + + # Encode addrs and datas into write requests + bytes_out = b"" + for addr, data in zip(addrs, datas): + bytes_out += int(1).to_bytes(4, byteorder="little") + bytes_out += int(addr).to_bytes(2, byteorder="little") + bytes_out += int(data).to_bytes(2, byteorder="little") + + sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + sock.sendto(bytes_out, (self.fpga_ip_addr, self.udp_port)) + class UDPSourceBridge(Elaboratable): def __init__(self): @@ -142,7 +215,7 @@ class UDPSourceBridge(Elaboratable): m.d.sync += self.bus_o.data.eq(self.data_i[16:]) m.d.sync += self.bus_o.rw.eq(rw_buf) m.d.sync += self.bus_o.valid.eq(1) - # m.d.sync += self.bus_o.last.eq(self.last_i) + m.d.sync += self.bus_o.last.eq(self.last_i) return m @@ -163,9 +236,9 @@ class UDPSinkBridge(Elaboratable): m.d.sync += self.last_o.eq(0) m.d.sync += self.valid_o.eq(0) - with m.If(self.bus_i.valid): + with m.If( (self.bus_i.valid) & (~self.bus_i.rw)): m.d.sync += self.data_o.eq(self.bus_i.data) - # m.d.sync += self.last_o.eq(self.bus_i.last) + m.d.sync += self.last_o.eq(self.bus_i.last) m.d.sync += self.valid_o.eq(1) return m diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index 4cfbeef..a735897 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -179,8 +179,9 @@ class UARTInterface(Elaboratable): if not all(isinstance(d, int) for d in datas): raise ValueError("Write data must all be integers.") - # I'm not sure if it's necessary to split outputs into chunks - # I think the output buffer doesn't really drop stuff, just the input buffer + # Since the FPGA doesn't issue any responses to write requests, we + # the host's input buffer isn't written to, and we don't need to + # send the data as chunks as the to avoid overflowing the input buffer. # Encode addrs and datas into write requests bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, datas)]) diff --git a/src/manta/utils.py b/src/manta/utils.py index 7aa3625..1e63bcb 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -17,6 +17,7 @@ class InternalBus(data.StructLayout): "data": 16, "rw": 1, "valid": 1, + "last": 1, } ) From 24ee956d6cda395f138357d61fad971c60669ff9 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 9 Feb 2024 18:58:02 -0800 Subject: [PATCH 41/89] add liteeth wrapper --- project_0/build.tcl | 65 -- project_0/manta.yaml | 23 - project_0/manta_test.yaml | 12 - project_0/stream.py | 68 -- project_0/test.yml | 28 - project_0/xdc/top_level.xdc | 260 -------- project_1/build.tcl | 65 -- project_1/liteeth_config.yml | 28 - project_1/manta.yaml | 27 - project_1/stream.py | 40 -- project_1/test.py | 5 - project_1/xdc/top_level.xdc | 260 -------- pyproject.toml | 1 + src/manta/cli.py | 11 +- .../{ethernet.py => ethernet/__init__.py} | 101 ++- src/manta/ethernet/liteeth_gen.py | 611 ++++++++++++++++++ src/manta/ethernet/sink_bridge.py | 26 + src/manta/ethernet/source_bridge.py | 37 ++ src/manta/manta.py | 22 + 19 files changed, 741 insertions(+), 949 deletions(-) delete mode 100644 project_0/build.tcl delete mode 100644 project_0/manta.yaml delete mode 100644 project_0/manta_test.yaml delete mode 100644 project_0/stream.py delete mode 100644 project_0/test.yml delete mode 100644 project_0/xdc/top_level.xdc delete mode 100644 project_1/build.tcl delete mode 100644 project_1/liteeth_config.yml delete mode 100644 project_1/manta.yaml delete mode 100644 project_1/stream.py delete mode 100644 project_1/test.py delete mode 100644 project_1/xdc/top_level.xdc rename src/manta/{ethernet.py => ethernet/__init__.py} (79%) create mode 100755 src/manta/ethernet/liteeth_gen.py create mode 100644 src/manta/ethernet/sink_bridge.py create mode 100644 src/manta/ethernet/source_bridge.py diff --git a/project_0/build.tcl b/project_0/build.tcl deleted file mode 100644 index d0441d6..0000000 --- a/project_0/build.tcl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/tclsh -# jay's build script -# pass -tclargs -d to generate diagnostics - -# switches - -set partNum xc7a100tcsg324-1 -set outputDir output_files -set verbose 0 - -if { $argc > 0 } { - if { $argc == 1 && [string compare [ lindex $argv 0 ] "-d"] == 0 } { - set verbose 1 - } else { - puts "usage: $argv0 \[-d\]" - exit 1 - } -} - -file mkdir $outputDir -set files [glob -nocomplain "$outputDir/*"] -if {[llength $files] != 0} { - file delete -force {*}[glob -directory $outputDir *]; -} - -read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ] -read_xdc ./xdc/top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -if { $verbose } { - report_timing_summary -file $outputDir/post_synth_timing_summary.rpt - report_timing -file $outputDir/post_synth_timing.rpt -} - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -if { $verbose } { - report_clock_utilization -file $outputDir/clock_util.rpt - report_timing_summary -file $outputDir/post_place_timing_summary.rpt - report_timing -file $outputDir/post_place_timing.rpt -} - -# route design and generate bitstream - -route_design -directive Explore -write_bitstream -force $outputDir/final.bit - -if { $verbose } { - report_route_status -file $outputDir/post_route_status.rpt - report_timing_summary -file $outputDir/post_route_timing_summary.rpt - report_timing -file $outputDir/post_route_timing.rpt - report_power -file $outputDir/post_route_power.rpt - report_drc -file $outputDir/post_imp_drc.rpt - write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true - # unfortunately, does nothing - show_schematic [ get_cells ] -} \ No newline at end of file diff --git a/project_0/manta.yaml b/project_0/manta.yaml deleted file mode 100644 index 4fd772f..0000000 --- a/project_0/manta.yaml +++ /dev/null @@ -1,23 +0,0 @@ ---- -cores: - io_core: - type: io - - inputs: - dhcp_done: 1 - dhcp_ip_address: 32 - dhcp_timeout: 1 - led: 16 - - outputs: - dhcp_start: 1 - ip_address: 32 - udp_port: 16 - udp0_ip_address: 32 - udp0_sink_data: 32 - udp0_sink_valid: 1 - -uart: - port: "/dev/ttyUSB1" - baudrate: 115200 - clock_freq: 50000000 diff --git a/project_0/manta_test.yaml b/project_0/manta_test.yaml deleted file mode 100644 index a7a83c4..0000000 --- a/project_0/manta_test.yaml +++ /dev/null @@ -1,12 +0,0 @@ ---- -cores: - io_core: - type: io - - inputs: - foobar: 1 - - -ethernet: - desired_fpga_ip: "192.168.0.110" - host_ip: "192.168.0.100" diff --git a/project_0/stream.py b/project_0/stream.py deleted file mode 100644 index 82a17c8..0000000 --- a/project_0/stream.py +++ /dev/null @@ -1,68 +0,0 @@ -from manta import Manta -import socket -import time - - -def configure(ip_address, udp_port): - m = Manta("manta.yaml") - - # Compute IP address - octets = [bin(int(o))[2:].zfill(8) for o in ip_address.split(".")] - ip_binary = int("".join(octets), 2) - - # Set IP address - m.io_core.set_probe("ip_address", ip_binary) - m.io_core.set_probe("dhcp_start", 1) - m.io_core.set_probe("dhcp_start", 0) - while m.io_core.get_probe("dhcp_done") != 1: - pass - print(m.io_core.get_probe("dhcp_ip_address")) - - # Set UDP port - m.io_core.set_probe("udp_port", udp_port) - - -def leds_test(ip_address, udp_port): - m = Manta("manta.yaml") - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - for i in range(0xFF): - sock.sendto(int(i).to_bytes(1, byteorder="big"), (ip_address, udp_port)) - led = m.io_core.get_probe("led") - print(f"i:{i} led:{led}") - time.sleep(0.2) - - -def send_variable_length_test(): - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - for i in range(0xFF): - sock.sendto(int(i).to_bytes(i, byteorder="big"), (ip_address, udp_port)) - time.sleep(0.2) - - -def send_to_host_test(host_ip, udp_port): - m = Manta("manta.yaml") - - # Set UDP port - m.io_core.set_probe("udp_port", udp_port) - - # Compute and set destination IP address: - octets = [bin(int(o))[2:].zfill(8) for o in host_ip.split(".")] - ip_binary = int("".join(octets), 2) - m.io_core.set_probe("udp0_ip_address", ip_binary) - - # Send data - m.io_core.set_probe("udp0_sink_data", 0x21_43_65_87) - m.io_core.set_probe("udp0_sink_valid", 1) - m.io_core.set_probe("udp0_sink_valid", 0) - - -if __name__ == "__main__": - ip_address = "192.168.0.110" - udp_port = 42069 - - configure(ip_address, udp_port) - # time.sleep(0.2) - # for _ in range(64): - # send_to_host_test("192.168.0.107", 42069) - # leds_test(ip_address, udp_port) - # send_variable_length_test() diff --git a/project_0/test.yml b/project_0/test.yml deleted file mode 100644 index 666a399..0000000 --- a/project_0/test.yml +++ /dev/null @@ -1,28 +0,0 @@ -# -# This file is part of LiteEth. -# -# Copyright (c) 2020-2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -# PHY -------------------------------------------------------------------------- -phy: LiteEthPHYRMII -vendor: xilinx -toolchain: vivado - -# Core ------------------------------------------------------------------------- -refclk_freq: 50e6 -clk_freq: 50e6 -core: udp -mac_address: 0x10e2d5000000 -dhcp: True -data_width: 8 - -# UDP Ports -------------------------------------------------------------------- -udp_ports: { - "udp0": { - "udp_port" : 2000, # Static Params. - "data_width" : 32, - "tx_fifo_depth" : 64, - "rx_fifo_depth" : 64, - }, -} diff --git a/project_0/xdc/top_level.xdc b/project_0/xdc/top_level.xdc deleted file mode 100644 index 7a77074..0000000 --- a/project_0/xdc/top_level.xdc +++ /dev/null @@ -1,260 +0,0 @@ -## R1.0 2019-08-27 -## Updated by jodalyst in 2020-2022 -## all inputs/outputs changed to lowercase; arrays start with zero. -## system clock renamed to clk_100mhz -## ja, jb, jc, jd renamed to 0-7 -## xa port renamed 0-3 -## seven segments renamed to a,b,c,d,e,f,dp - -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; - - -##Switches - -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv -set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - diff --git a/project_1/build.tcl b/project_1/build.tcl deleted file mode 100644 index d0441d6..0000000 --- a/project_1/build.tcl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/tclsh -# jay's build script -# pass -tclargs -d to generate diagnostics - -# switches - -set partNum xc7a100tcsg324-1 -set outputDir output_files -set verbose 0 - -if { $argc > 0 } { - if { $argc == 1 && [string compare [ lindex $argv 0 ] "-d"] == 0 } { - set verbose 1 - } else { - puts "usage: $argv0 \[-d\]" - exit 1 - } -} - -file mkdir $outputDir -set files [glob -nocomplain "$outputDir/*"] -if {[llength $files] != 0} { - file delete -force {*}[glob -directory $outputDir *]; -} - -read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ] -read_xdc ./xdc/top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -if { $verbose } { - report_timing_summary -file $outputDir/post_synth_timing_summary.rpt - report_timing -file $outputDir/post_synth_timing.rpt -} - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -if { $verbose } { - report_clock_utilization -file $outputDir/clock_util.rpt - report_timing_summary -file $outputDir/post_place_timing_summary.rpt - report_timing -file $outputDir/post_place_timing.rpt -} - -# route design and generate bitstream - -route_design -directive Explore -write_bitstream -force $outputDir/final.bit - -if { $verbose } { - report_route_status -file $outputDir/post_route_status.rpt - report_timing_summary -file $outputDir/post_route_timing_summary.rpt - report_timing -file $outputDir/post_route_timing.rpt - report_power -file $outputDir/post_route_power.rpt - report_drc -file $outputDir/post_imp_drc.rpt - write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true - # unfortunately, does nothing - show_schematic [ get_cells ] -} \ No newline at end of file diff --git a/project_1/liteeth_config.yml b/project_1/liteeth_config.yml deleted file mode 100644 index 666a399..0000000 --- a/project_1/liteeth_config.yml +++ /dev/null @@ -1,28 +0,0 @@ -# -# This file is part of LiteEth. -# -# Copyright (c) 2020-2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -# PHY -------------------------------------------------------------------------- -phy: LiteEthPHYRMII -vendor: xilinx -toolchain: vivado - -# Core ------------------------------------------------------------------------- -refclk_freq: 50e6 -clk_freq: 50e6 -core: udp -mac_address: 0x10e2d5000000 -dhcp: True -data_width: 8 - -# UDP Ports -------------------------------------------------------------------- -udp_ports: { - "udp0": { - "udp_port" : 2000, # Static Params. - "data_width" : 32, - "tx_fifo_depth" : 64, - "rx_fifo_depth" : 64, - }, -} diff --git a/project_1/manta.yaml b/project_1/manta.yaml deleted file mode 100644 index 23f7b6d..0000000 --- a/project_1/manta.yaml +++ /dev/null @@ -1,27 +0,0 @@ ---- -cores: - io_core: - type: io - - inputs: - sw: 16 - - outputs: - led: 16 - -ethernet: - phy: LiteEthPHYRMII - vendor: xilinx - toolchain: vivado - - refclk_freq: 50e6 - clk_freq: 50e6 - - fpga_ip_addr: "192.168.0.110" - host_ip_addr: "192.168.0.100" - udp_port: 42069 - - core: udp # we handle this - mac_address: # this should be optional - dhcp: # should be optional, default to true? - data_width: 32 # using DHCP will force this to 32, but for ease of use we should design for that even for static IP devices diff --git a/project_1/stream.py b/project_1/stream.py deleted file mode 100644 index ae56e49..0000000 --- a/project_1/stream.py +++ /dev/null @@ -1,40 +0,0 @@ -import socket -def write(addrs, datas): - bytes_out = b"" - for addr, data in zip(addrs, datas): - bytes_out += int(1).to_bytes(4, byteorder="little") - bytes_out += int(addr).to_bytes(2, byteorder="little") - bytes_out += int(data).to_bytes(2, byteorder="little") - - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - sock.sendto(bytes_out, (fpga_ip_addr, udp_port)) - -def read(addrs): - bytes_out = b"" - for addr in addrs: - bytes_out += int(0).to_bytes(4, byteorder="little") - bytes_out += int(addr).to_bytes(2, byteorder="little") - bytes_out += int(0).to_bytes(2, byteorder="little") - - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - sock.bind((host_ip_addr, udp_port)) - sock.sendto(bytes_out, (fpga_ip_addr, udp_port)) - data, addr = sock.recvfrom(1024) - - return int.from_bytes(data, "little") - -if __name__ == "__main__": - host_ip_addr = "192.168.0.100" - fpga_ip_addr = "192.168.0.110" - udp_port = 42069 - - for i in range(2**16): - write([0x0000],[0x0000]) - write([0x0000],[0x0001]) - write([0x0000],[0x0000]) - write([0x0002],[i]) - # print(read([0x0002])) - # write([0x0002],[0b0101_0101_0101_0101]) - # write([0x0000],[0x0000]) - # write([0x0000],[0x0001]) - # write([0x0000],[0x0000]) diff --git a/project_1/test.py b/project_1/test.py deleted file mode 100644 index 3a725ad..0000000 --- a/project_1/test.py +++ /dev/null @@ -1,5 +0,0 @@ -from manta import Manta -m = Manta("manta.yaml") - -print(bin(m.io_core.get_probe("sw"))) -m.io_core.set_probe("led", 4) \ No newline at end of file diff --git a/project_1/xdc/top_level.xdc b/project_1/xdc/top_level.xdc deleted file mode 100644 index 7a77074..0000000 --- a/project_1/xdc/top_level.xdc +++ /dev/null @@ -1,260 +0,0 @@ -## R1.0 2019-08-27 -## Updated by jodalyst in 2020-2022 -## all inputs/outputs changed to lowercase; arrays start with zero. -## system clock renamed to clk_100mhz -## ja, jb, jc, jd renamed to 0-7 -## xa port renamed 0-3 -## seven segments renamed to a,b,c,d,e,f,dp - -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; - - -##Switches - -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv -set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - diff --git a/pyproject.toml b/pyproject.toml index 0b798de..b794d15 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -10,6 +10,7 @@ dependencies = [ "amaranth[builtin-yosys]", "PyYAML", "pyserial", + "liteeth@git+https://github.com/enjoy-digital/liteeth@2023.12", "pyvcd", ] diff --git a/src/manta/cli.py b/src/manta/cli.py index 610ec13..0d64bd5 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -71,17 +71,8 @@ def wrong_args(): def gen(config_path, output_path): m = Manta(config_path) - from amaranth.back import verilog - with open(output_path, "w") as f: - f.write( - verilog.convert( - m, - name="manta", - ports=m.get_top_level_ports(), - strip_internal_attrs=True, - ) - ) + f.write(m.generate_verilog()) def inst(config_path): diff --git a/src/manta/ethernet.py b/src/manta/ethernet/__init__.py similarity index 79% rename from src/manta/ethernet.py rename to src/manta/ethernet/__init__.py index 9f174fd..4b16ee8 100644 --- a/src/manta/ethernet.py +++ b/src/manta/ethernet/__init__.py @@ -1,10 +1,14 @@ from amaranth import * -from manta.utils import * +from ..utils import * +from .source_bridge import UDPSourceBridge +from .sink_bridge import UDPSinkBridge +from random import randint import socket class EthernetInterface(Elaboratable): def __init__(self, config): + self.config = config self.fpga_ip_addr = config["fpga_ip_addr"] self.host_ip_addr = config["host_ip_addr"] self.udp_port = config["udp_port"] @@ -54,10 +58,10 @@ class EthernetInterface(Elaboratable): def elaborate(self, platform): m = Module() - with m.If(self.dhcp_timer < 15): + with m.If(self.dhcp_timer < int(50e6)): m.d.sync += self.dhcp_timer.eq(self.dhcp_timer + 1) - m.d.sync += self.dhcp_start.eq(self.dhcp_timer == 14) + m.d.sync += self.dhcp_start.eq(self.dhcp_timer == (int(50e6) - 2)) m.submodules.liteeth = Instance( "liteeth_core", @@ -129,7 +133,7 @@ class EthernetInterface(Elaboratable): # Send read requests, and get responses sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) sock.bind((self.host_ip_addr, self.udp_port)) - chunk_size = 128 + chunk_size = 64 # 128 addr_chunks = split_into_chunks(addrs, chunk_size) datas = [] @@ -146,6 +150,9 @@ class EthernetInterface(Elaboratable): # Split into groups of four bytes datas += [int.from_bytes(d, "little") for d in split_into_chunks(data, 4)] + if len(datas) != len(addrs): + raise ValueError("Got less data than expected from FPGA.") + return datas def write(self, addrs, datas): @@ -184,61 +191,39 @@ class EthernetInterface(Elaboratable): sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) sock.sendto(bytes_out, (self.fpga_ip_addr, self.udp_port)) + def generate_liteeth_core(self): + # Randomly assign a MAC address if one is not specified in the configuration. + # This will choose a MAC address in the Locally Administered, Administratively Assigned group. + # For more information, see: + # https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses -class UDPSourceBridge(Elaboratable): - def __init__(self): - self.bus_o = Signal(InternalBus()) + if "mac_address" not in self.config: + mac_address = list(f"{randint(0, (2**48) - 1):012x}") + mac_address[1] = "2" + mac_address = int("".join(mac_address), 16) - self.data_i = Signal(32) - self.last_i = Signal() - self.ready_o = Signal() - self.valid_i = Signal() + else: + mac_address = self.config["mac_address"] - def elaborate(self, platform): - m = Module() + liteeth_config = { + "phy": self.config["phy"], + "vendor": self.config["vendor"], + "toolchain": self.config["toolchain"], + "refclk_freq": self.config["refclk_freq"], + "clk_freq": self.config["clk_freq"], + "mac_address": mac_address, + "dhcp": True, + "data_width": 32, + "udp_ports": { + "udp0": { + "udp_port": self.udp_port, + "data_width": 32, + "tx_fifo_depth": 64, + "rx_fifo_depth": 64, + } + }, + } - state = Signal() # can either be 0, for read/write, or 1, for data - rw_buf = Signal().like(self.bus_o.rw) - - # Can always take more data - m.d.sync += self.ready_o.eq(1) - - m.d.sync += self.bus_o.eq(0) - with m.If(self.valid_i): - m.d.sync += state.eq(~state) - - with m.If(state == 0): - m.d.sync += rw_buf.eq(self.data_i) - - with m.Else(): - m.d.sync += self.bus_o.addr.eq(self.data_i[:16]) - m.d.sync += self.bus_o.data.eq(self.data_i[16:]) - m.d.sync += self.bus_o.rw.eq(rw_buf) - m.d.sync += self.bus_o.valid.eq(1) - m.d.sync += self.bus_o.last.eq(self.last_i) - - return m - - -class UDPSinkBridge(Elaboratable): - def __init__(self): - self.bus_i = Signal(InternalBus()) - - self.data_o = Signal(32) - self.last_o = Signal() - self.ready_i = Signal() - self.valid_o = Signal() - - def elaborate(self, platform): - m = Module() - - m.d.sync += self.data_o.eq(0) - m.d.sync += self.last_o.eq(0) - m.d.sync += self.valid_o.eq(0) - - with m.If( (self.bus_i.valid) & (~self.bus_i.rw)): - m.d.sync += self.data_o.eq(self.bus_i.data) - m.d.sync += self.last_o.eq(self.bus_i.last) - m.d.sync += self.valid_o.eq(1) - - return m + # Generate the core + from .liteeth_gen import main + return main(liteeth_config) diff --git a/src/manta/ethernet/liteeth_gen.py b/src/manta/ethernet/liteeth_gen.py new file mode 100755 index 0000000..e07481e --- /dev/null +++ b/src/manta/ethernet/liteeth_gen.py @@ -0,0 +1,611 @@ +# LiteEth Core Generator +# Modified from https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py + +# Unless otherwise noted, LiteEth is Copyright 2012-2022 / EnjoyDigital + +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: + +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. + +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# Other authors retain ownership of their contributions. If a submission can +# reasonably be considered independently copyrightable, it's yours and we +# encourage you to claim it with appropriate copyright notices. This submission +# then falls under the "otherwise noted" category. All submissions are strongly +# encouraged to use the two-clause BSD license reproduced above. + +# Copyright (c) 2015-2023 Florent Kermarrec +# Copyright (c) 2020 Xiretza +# Copyright (c) 2020 Stefan Schrijvers +# Copyright (c) 2022 Victor Suarez Rovere +# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. +# SPDX-License-Identifier: BSD-2-Clause + +from migen import * + +from litex.gen import * + +from litex.build.generic_platform import * +from litex.build.xilinx.platform import XilinxPlatform +from litex.build.lattice.platform import LatticePlatform + +from litex.soc.interconnect import wishbone +from litex.soc.interconnect import axi +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.integration.soc import SoCRegion + +from liteeth.common import * + +from liteeth import phy as liteeth_phys +from liteeth.mac import LiteEthMAC +from liteeth.core import LiteEthUDPIPCore +from liteeth.core.dhcp import LiteEthDHCP + +from liteeth.frontend.stream import LiteEthUDPStreamer +from liteeth.frontend.etherbone import LiteEthEtherbone + +from tempfile import TemporaryDirectory + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst + ("sys_clock", 0, Pins(1)), + ("sys_reset", 1, Pins(1)), + # IP/MAC Address. + ("mac_address", 0, Pins(48)), + ("ip_address", 0, Pins(32)), + # Interrupt + ("interrupt", 0, Pins(1)), + # DHCP. + ( + "dhcp", + 0, + Subsignal("start", Pins(1)), + Subsignal("done", Pins(1)), + Subsignal("timeout", Pins(1)), + Subsignal("ip_address", Pins(32)), + ), + # MII PHY Pads + ( + "mii_clocks", + 0, + Subsignal("tx", Pins(1)), + Subsignal("rx", Pins(1)), + ), + ( + "mii", + 0, + Subsignal("rst_n", Pins(1)), + Subsignal("mdio", Pins(1)), + Subsignal("mdc", Pins(1)), + Subsignal("rx_dv", Pins(1)), + Subsignal("rx_er", Pins(1)), + Subsignal("rx_data", Pins(4)), + Subsignal("tx_en", Pins(1)), + Subsignal("tx_data", Pins(4)), + Subsignal("col", Pins(1)), + Subsignal("crs", Pins(1)), + ), + # RMII PHY Pads + ("rmii_clocks", 0, Subsignal("ref_clk", Pins(1))), + ( + "rmii", + 0, + Subsignal("rst_n", Pins(1)), + Subsignal("rx_data", Pins(2)), + Subsignal("crs_dv", Pins(1)), + Subsignal("tx_en", Pins(1)), + Subsignal("tx_data", Pins(2)), + Subsignal("mdc", Pins(1)), + Subsignal("mdio", Pins(1)), + ), + # GMII PHY Pads + ( + "gmii_clocks", + 0, + Subsignal("tx", Pins(1)), + Subsignal("gtx", Pins(1)), + Subsignal("rx", Pins(1)), + ), + ( + "gmii", + 0, + Subsignal("rst_n", Pins(1)), + Subsignal("int_n", Pins(1)), + Subsignal("mdio", Pins(1)), + Subsignal("mdc", Pins(1)), + Subsignal("rx_dv", Pins(1)), + Subsignal("rx_er", Pins(1)), + Subsignal("rx_data", Pins(8)), + Subsignal("tx_en", Pins(1)), + Subsignal("tx_er", Pins(1)), + Subsignal("tx_data", Pins(8)), + Subsignal("col", Pins(1)), + Subsignal("crs", Pins(1)), + ), + # RGMII PHY Pads + ("rgmii_clocks", 0, Subsignal("tx", Pins(1)), Subsignal("rx", Pins(1))), + ( + "rgmii", + 0, + Subsignal("rst_n", Pins(1)), + Subsignal("int_n", Pins(1)), + Subsignal("mdio", Pins(1)), + Subsignal("mdc", Pins(1)), + Subsignal("rx_ctl", Pins(1)), + Subsignal("rx_data", Pins(4)), + Subsignal("tx_ctl", Pins(1)), + Subsignal("tx_data", Pins(4)), + ), + # SGMII PHY Pads + ( + "sgmii", + 0, + Subsignal("refclk", Pins(1)), + Subsignal("rst", Pins(1)), + Subsignal("txp", Pins(1)), + Subsignal("txn", Pins(1)), + Subsignal("rxp", Pins(1)), + Subsignal("rxn", Pins(1)), + Subsignal("link_up", Pins(1)), + ), +] + + +def get_udp_port_ios(name, data_width, dynamic_params=False): + return [ + ( + f"{name}", + 0, + # Parameters. + *( + [ + Subsignal("udp_port", Pins(16)), + Subsignal("ip_address", Pins(32)), + ] + if dynamic_params + else [] + ), + # Sink. + Subsignal("sink_valid", Pins(1)), + Subsignal("sink_last", Pins(1)), + Subsignal("sink_ready", Pins(1)), + Subsignal("sink_data", Pins(data_width)), + # Source. + Subsignal("source_valid", Pins(1)), + Subsignal("source_last", Pins(1)), + Subsignal("source_ready", Pins(1)), + Subsignal("source_data", Pins(data_width)), + Subsignal("source_error", Pins(1)), + ), + ] + + +def get_udp_raw_port_ios(name, data_width): + return [ + ( + f"{name}", + 0, + # Sink. + Subsignal("sink_ip_address", Pins(32)), + Subsignal("sink_src_port", Pins(16)), + Subsignal("sink_dst_port", Pins(16)), + Subsignal("sink_valid", Pins(1)), + Subsignal("sink_length", Pins(16)), + Subsignal("sink_last", Pins(1)), + Subsignal("sink_ready", Pins(1)), + Subsignal("sink_data", Pins(data_width)), + Subsignal("sink_last_be", Pins(data_width // 8)), + # Source. + Subsignal("source_ip_address", Pins(32)), + Subsignal("source_src_port", Pins(16)), + Subsignal("source_dst_port", Pins(16)), + Subsignal("source_valid", Pins(1)), + Subsignal("source_length", Pins(16)), + Subsignal("source_last", Pins(1)), + Subsignal("source_ready", Pins(1)), + Subsignal("source_data", Pins(data_width)), + Subsignal("source_last_be", Pins(data_width // 8)), + Subsignal("source_error", Pins(1)), + ), + ] + + +# PHY Core ----------------------------------------------------------------------------------------- +class PHYCore(SoCMini): + SoCMini.csr_map = { + "ctrl": 0, + "ethphy": 1, + "ethmac": 2, + } + + def __init__(self, platform, core_config): + for deprecated in ("csr_map", "mem_map"): + if deprecated in core_config: + raise RuntimeWarning( + "Config option {!r} is now a sub-option of 'soc'".format(deprecated) + ) + + # SoC parameters --------------------------------------------------------------------------- + soc_args = {} + if "soc" in core_config: + soc_config = core_config["soc"] + + for arg in soc_config: + if arg in ("csr_map", "interrupt_map", "mem_map"): + getattr(self, arg).update(soc_config[arg]) + else: + soc_args[arg] = soc_config[arg] + + # SoCMini ---------------------------------------------------------------------------------- + SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args) + + # CRG -------------------------------------------------------------------------------------- + self.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset")) + + # PHY -------------------------------------------------------------------------------------- + phy = core_config["phy"] + # MII. + if phy in [liteeth_phys.LiteEthPHYMII]: + ethphy = phy( + clock_pads=platform.request("mii_clocks"), pads=platform.request("mii") + ) + # RMII. + elif phy in [liteeth_phys.LiteEthPHYRMII]: + ethphy = phy( + refclk_cd=None, + clock_pads=platform.request("rmii_clocks"), + pads=platform.request("rmii"), + ) + # GMII. + elif phy in [liteeth_phys.LiteEthPHYGMII]: + ethphy = phy( + clock_pads=platform.request("gmii_clocks"), + pads=platform.request("gmii"), + ) + # GMII / MII. + elif phy in [liteeth_phys.LiteEthPHYGMIIMII]: + ethphy = phy( + clock_pads=platform.request("gmii_clocks"), + pads=platform.request("gmii"), + clk_freq=self.clk_freq, + ) + # RGMII. + elif phy in [ + liteeth_phys.LiteEthS7PHYRGMII, + liteeth_phys.LiteEthECP5PHYRGMII, + ]: + ethphy = phy( + clock_pads=platform.request("rgmii_clocks"), + pads=platform.request("rgmii"), + tx_delay=core_config.get("phy_tx_delay", 2e-9), + rx_delay=core_config.get("phy_rx_delay", 2e-9), + with_hw_init_reset=False, + ) # FIXME: required since sys_clk = eth_rx_clk. + # SGMII. + elif phy in [ + liteeth_phys.A7_1000BASEX, + liteeth_phys.A7_2500BASEX, + liteeth_phys.K7_1000BASEX, + liteeth_phys.K7_2500BASEX, + liteeth_phys.KU_1000BASEX, + liteeth_phys.KU_2500BASEX, + liteeth_phys.USP_GTH_1000BASEX, + liteeth_phys.USP_GTH_2500BASEX, + liteeth_phys.USP_GTY_1000BASEX, + liteeth_phys.USP_GTY_2500BASEX, + ]: + ethphy_pads = platform.request("sgmii") + # Artix7. + if phy in [liteeth_phys.A7_1000BASEX, liteeth_phys.A7_2500BASEX]: + refclk_freq = core_config.get("refclk_freq", 0) + assert refclk_freq in [125e6, 156.25e6] + from liteeth.phy.a7_gtp import QPLLSettings, QPLL + + qpll_settings = QPLLSettings( + refclksel=0b001, + fbdiv=4, + fbdiv_45={125e6: 5, 156.25e6: 4}[refclk_freq], + refclk_div=1, + ) + qpll = QPLL(ethphy_pads.refclk, qpll_settings) + self.submodules += qpll + ethphy = phy( + qpll_channel=qpll.channels[0], + data_pads=ethphy_pads, + sys_clk_freq=self.clk_freq, + with_csr=False, + rx_polarity=core_config.get("phy_rx_polarity", 0), + tx_polarity=core_config.get("phy_tx_polarity", 0), + ) + # Other 7-Series/Ultrascale(+). + else: + ethphy = phy( + refclk_or_clk_pads=ethphy_pads.refclk, + data_pads=ethphy_pads, + sys_clk_freq=self.clk_freq, + refclk_freq=core_config.get("refclk_freq", 200e6), + with_csr=False, + rx_polarity=core_config.get("phy_rx_polarity", 0), + tx_polarity=core_config.get("phy_tx_polarity", 0), + ) + self.comb += [ + ethphy.reset.eq(ethphy_pads.rst), + ethphy_pads.link_up.eq(ethphy.link_up), + ] + else: + raise ValueError("Unsupported PHY") + self.ethphy = ethphy + + # Timing constaints. + # Generate timing constraints to ensure the "keep" attribute is properly set on the various + # clocks. This also adds the constraints to the generated .xdc that can then be "imported" + # in the project using the core. + eth_rx_clk = getattr(ethphy, "crg", ethphy).cd_eth_rx.clk + eth_tx_clk = getattr(ethphy, "crg", ethphy).cd_eth_tx.clk + from liteeth.phy.model import LiteEthPHYModel + + if not isinstance(ethphy, LiteEthPHYModel): + self.platform.add_period_constraint(eth_rx_clk, 1e9 / phy.rx_clk_freq) + self.platform.add_period_constraint(eth_tx_clk, 1e9 / phy.tx_clk_freq) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk + ) + + +# UDP Core ----------------------------------------------------------------------------------------- +class UDPCore(PHYCore): + def add_streamer_port(self, platform, name, port_cfg): + # Use default Data-Width of 8-bit when not specified. + data_width = port_cfg.get("data_width", 8) + + # Used dynamic UDP-Port/IP-Address when not specified. + dynamic_params = port_cfg.get("ip_address", None) is None + + # FIFO Depth. + tx_fifo_depth = port_cfg.get("tx_fifo_depth", 64) + rx_fifo_depth = port_cfg.get("rx_fifo_depth", 64) + + # Create/Add IOs. + # --------------- + platform.add_extension( + get_udp_port_ios(name, data_width=data_width, dynamic_params=dynamic_params) + ) + + port_ios = platform.request(name) + + if dynamic_params: + ip_address = port_ios.ip_address + udp_port = port_ios.udp_port + else: + ip_address = port_cfg.get("ip_address") + udp_port = port_cfg.get("udp_port") + + # Create UDPStreamer. + # ------------------- + udp_streamer = LiteEthUDPStreamer( + self.core.udp, + ip_address=ip_address, + udp_port=udp_port, + data_width=data_width, + tx_fifo_depth=tx_fifo_depth, + rx_fifo_depth=rx_fifo_depth, + ) + self.submodules += udp_streamer + + # Connect IOs. + # ------------ + # Connect UDP Sink IOs to UDP Steamer. + self.comb += [ + udp_streamer.sink.valid.eq(port_ios.sink_valid), + udp_streamer.sink.last.eq(port_ios.sink_last), + port_ios.sink_ready.eq(udp_streamer.sink.ready), + udp_streamer.sink.data.eq(port_ios.sink_data), + ] + + # Connect UDP Streamer to UDP Source IOs. + self.comb += [ + port_ios.source_valid.eq(udp_streamer.source.valid), + port_ios.source_last.eq(udp_streamer.source.last), + udp_streamer.source.ready.eq(port_ios.source_ready), + port_ios.source_data.eq(udp_streamer.source.data), + port_ios.source_error.eq(udp_streamer.source.error), + ] + + def add_raw_port(self, platform, name, port_cfg): + # Use default Data-Width of 8-bit when not specified. + data_width = port_cfg.get("data_width", 8) + + # Create/Add IOs. + # --------------- + platform.add_extension( + get_udp_raw_port_ios( + name, + data_width=data_width, + ) + ) + + port_ios = platform.request(name) + + raw_port = self.core.udp.crossbar.get_port( + port_ios.sink_dst_port, dw=data_width + ) + + # Connect IOs. + # ------------ + # Connect UDP Sink IOs to UDP. + self.comb += [ + raw_port.sink.valid.eq(port_ios.sink_valid), + raw_port.sink.last.eq(port_ios.sink_last), + raw_port.sink.dst_port.eq(port_ios.sink_dst_port), + raw_port.sink.src_port.eq(port_ios.sink_src_port), + raw_port.sink.ip_address.eq(port_ios.sink_ip_address), + raw_port.sink.length.eq(port_ios.sink_length), + port_ios.sink_ready.eq(raw_port.sink.ready), + raw_port.sink.data.eq(port_ios.sink_data), + raw_port.sink.last_be.eq(port_ios.sink_last_be), + ] + + # Connect UDP to UDP Source IOs. + self.comb += [ + port_ios.source_valid.eq(raw_port.source.valid), + port_ios.source_last.eq(raw_port.source.last), + port_ios.source_dst_port.eq(raw_port.source.dst_port), + port_ios.source_src_port.eq(raw_port.source.src_port), + port_ios.source_ip_address.eq(raw_port.source.ip_address), + port_ios.source_length.eq(raw_port.source.length), + raw_port.source.ready.eq(port_ios.source_ready), + port_ios.source_data.eq(raw_port.source.data), + port_ios.source_last_be.eq(raw_port.source.last_be), + port_ios.source_error.eq(raw_port.source.error), + ] + + def __init__(self, platform, core_config): + # Config ----------------------------------------------------------------------------------- + tx_cdc_depth = core_config.get("tx_cdc_depth", 32) + tx_cdc_buffered = core_config.get("tx_cdc_buffered", False) + rx_cdc_depth = core_config.get("rx_cdc_depth", 32) + rx_cdc_buffered = core_config.get("rx_cdc_buffered", False) + + # MAC Address. + mac_address = core_config.get("mac_address", None) + # Get MAC Address from IOs when not specified. + if mac_address is None: + mac_address = platform.request("mac_address") + + # IP Address. + dhcp = core_config.get("dhcp", False) + ip_address = core_config.get("ip_address", None) + # Get IP Address from IOs when not specified. + if ip_address is None: + ip_address = platform.request("ip_address") + else: + assert not dhcp + + # PHY -------------------------------------------------------------------------------------- + PHYCore.__init__(self, platform, core_config) + + # Core ------------------------------------------------------------------------------------- + data_width = core_config.get("data_width", 8) + self.core = LiteEthUDPIPCore( + self.ethphy, + mac_address=mac_address, + ip_address=ip_address, + clk_freq=core_config["clk_freq"], + dw=data_width, + with_sys_datapath=(data_width == 32), + tx_cdc_depth=tx_cdc_depth, + tx_cdc_buffered=tx_cdc_buffered, + rx_cdc_depth=rx_cdc_depth, + rx_cdc_buffered=rx_cdc_buffered, + ) + + # DHCP ------------------------------------------------------------------------------------- + + if dhcp: + dhcp_pads = platform.request("dhcp") + dhcp_port = self.core.udp.crossbar.get_port(68, dw=32, cd="sys") + if isinstance(mac_address, Signal): + dhcp_mac_address = mac_address + else: + dhcp_mac_address = Signal(48, reset=0x10E2D5000001) + self.dhcp = LiteEthDHCP(udp_port=dhcp_port, sys_clk_freq=self.sys_clk_freq) + self.comb += [ + self.dhcp.start.eq(dhcp_pads.start), + dhcp_pads.done.eq(self.dhcp.done), + dhcp_pads.timeout.eq(self.dhcp.timeout), + dhcp_pads.ip_address.eq(self.dhcp.ip_address), + ] + + # Etherbone -------------------------------------------------------------------------------- + + etherbone = core_config.get("etherbone", False) + etherbone_port = core_config.get("etherbone_port", 1234) + etherbone_buffer_depth = core_config.get("etherbone_buffer_depth", 16) + + if etherbone: + assert data_width == 32 + self.etherbone = LiteEthEtherbone( + udp=self.core.udp, + udp_port=etherbone_port, + buffer_depth=etherbone_buffer_depth, + cd="sys", + ) + axil_bus = axi.AXILiteInterface(address_width=32, data_width=32) + platform.add_extension(axil_bus.get_ios("mmap")) + self.submodules += axi.Wishbone2AXILite( + self.etherbone.wishbone.bus, axil_bus + ) + self.comb += axil_bus.connect_to_pads( + platform.request("mmap"), mode="master" + ) + + # UDP Ports -------------------------------------------------------------------------------- + for name, port_cfg in core_config["udp_ports"].items(): + # mode either `raw` or `stream`, default to streamer to be backwards compatible + mode = port_cfg.get("mode", "streamer") + assert mode == "raw" or mode == "streamer" + + if mode == "streamer": + self.add_streamer_port(platform, name, port_cfg) + elif mode == "raw": + self.add_raw_port(platform, name, port_cfg) + + +# Build -------------------------------------------------------------------------------------------- +def main(core_config): + # Convert YAML elements to Python/LiteX -------------------------------------------------------- + for k, v in core_config.items(): + replaces = {"False": False, "True": True, "None": None} + for r in replaces.keys(): + if v == r: + core_config[k] = replaces[r] + if k == "phy": + core_config[k] = getattr(liteeth_phys, core_config[k]) + if k in ["refclk_freq", "clk_freq"]: + core_config[k] = int(float(core_config[k])) + if k in ["phy_tx_delay", "phy_rx_delay"]: + core_config[k] = float(core_config[k]) + + # Generate core -------------------------------------------------------------------------------- + if "device" not in core_config: + core_config["device"] = "" + if core_config["vendor"] == "lattice": + toolchain = core_config.get("toolchain", "diamond") + platform = LatticePlatform(core_config["device"], io=[], toolchain=toolchain) + elif core_config["vendor"] == "xilinx": + toolchain = core_config.get("toolchain", "vivado") + platform = XilinxPlatform(core_config["device"], io=[], toolchain=toolchain) + else: + raise ValueError("Unsupported vendor: {}".format(core_config["vendor"])) + platform.add_extension(_io) + + soc = UDPCore(platform, core_config) + + with TemporaryDirectory() as path: + builder = Builder(soc, compile_gateware=False, output_dir=path) + builder.build(build_name="liteeth_core") + + file = open(path + "/gateware/liteeth_core.v") + data = file.read() + file.close() + + return data diff --git a/src/manta/ethernet/sink_bridge.py b/src/manta/ethernet/sink_bridge.py new file mode 100644 index 0000000..c10a290 --- /dev/null +++ b/src/manta/ethernet/sink_bridge.py @@ -0,0 +1,26 @@ +from amaranth import * +from manta.utils import * + + +class UDPSinkBridge(Elaboratable): + def __init__(self): + self.bus_i = Signal(InternalBus()) + + self.data_o = Signal(32) + self.last_o = Signal() + self.ready_i = Signal() + self.valid_o = Signal() + + def elaborate(self, platform): + m = Module() + + m.d.sync += self.data_o.eq(0) + m.d.sync += self.last_o.eq(0) + m.d.sync += self.valid_o.eq(0) + + with m.If((self.bus_i.valid) & (~self.bus_i.rw)): + m.d.sync += self.data_o.eq(self.bus_i.data) + m.d.sync += self.last_o.eq(self.bus_i.last) + m.d.sync += self.valid_o.eq(1) + + return m diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py new file mode 100644 index 0000000..e87967b --- /dev/null +++ b/src/manta/ethernet/source_bridge.py @@ -0,0 +1,37 @@ +from amaranth import * +from manta.utils import * + + +class UDPSourceBridge(Elaboratable): + def __init__(self): + self.bus_o = Signal(InternalBus()) + + self.data_i = Signal(32) + self.last_i = Signal() + self.ready_o = Signal() + self.valid_i = Signal() + + def elaborate(self, platform): + m = Module() + + state = Signal() # can either be 0, for read/write, or 1, for data + rw_buf = Signal().like(self.bus_o.rw) + + # Can always take more data + m.d.sync += self.ready_o.eq(1) + + m.d.sync += self.bus_o.eq(0) + with m.If(self.valid_i): + m.d.sync += state.eq(~state) + + with m.If(state == 0): + m.d.sync += rw_buf.eq(self.data_i) + + with m.Else(): + m.d.sync += self.bus_o.addr.eq(self.data_i[:16]) + m.d.sync += self.bus_o.data.eq(self.data_i[16:]) + m.d.sync += self.bus_o.rw.eq(rw_buf) + m.d.sync += self.bus_o.valid.eq(1) + m.d.sync += self.bus_o.last.eq(self.last_i) + + return m diff --git a/src/manta/manta.py b/src/manta/manta.py index c503fd2..35744a5 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -155,3 +155,25 @@ class Manta(Elaboratable): ports += instance.get_top_level_ports() return ports + + def generate_verilog(self, strip_internal_attrs=False): + from amaranth.back import verilog + + output = verilog.convert( + self, + name="manta", + ports=self.get_top_level_ports(), + strip_internal_attrs=strip_internal_attrs, + ) + + # Below is a hack! + # The Ethernet core is a Verilog snippet generated by LiteEth, + # which gets appended to the Amaranth output such that everything + # still lives within one file. + + # In the future this shouldn't be required once Amaranth SOC + # launches, but until then, this is likely the simplest approach. + if isinstance(self.interface, EthernetInterface): + output += self.interface.generate_liteeth_core() + + return output From 63e912fb63cf968dbd3d495ecefcbe4b2e00a63d Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 9 Feb 2024 22:49:58 -0800 Subject: [PATCH 42/89] fix grammar and diagrams --- doc/alternatives.md | 2 +- doc/architecture.md | 17 +- doc/assets/bus_architecture.drawio.svg | 66 +- doc/assets/io_core_architecture.drawio.svg | 270 +++++--- doc/assets/io_core_memory_map.drawio.svg | 251 ------- .../logic_analyzer_architecture.drawio.svg | 458 +++++++------ doc/assets/memory_architecture.drawio.svg | 386 ++++++----- doc/assets/system_architecture.drawio.svg | 505 +++++++------- doc/assets/uart_packets.drawio.svg | 627 ++++++++++-------- doc/ethernet_interface.md | 42 +- doc/index.md | 2 +- doc/installation.md | 23 +- doc/io_core.md | 8 +- doc/logic_analyzer_core.md | 6 +- doc/memory_core.md | 2 +- doc/uart_interface.md | 2 +- mkdocs.yml | 26 +- 17 files changed, 1392 insertions(+), 1301 deletions(-) delete mode 100644 doc/assets/io_core_memory_map.drawio.svg diff --git a/doc/alternatives.md b/doc/alternatives.md index 7758656..44f998d 100644 --- a/doc/alternatives.md +++ b/doc/alternatives.md @@ -55,7 +55,7 @@ An embedded logic analyzer for Lattice FPGAs, provided as part of the Diamond de ### Opal Kelly FrontPanel SDK -Unlike other entries in this list, Opal Kelly's FrontPanel SDK is not marketed as a debugger (although it can be used as such). Instead, it's designed to provide a host computer with a real time interface to FGPA signals, and present them on a graphical “front panel". These front panels exist as a GUI window on the host, and contain buttons, knobs, and indicators, much like a LabVIEW virtual instrument. Communication between the host and FPGA is accomplished with either USB or PCIe. Bindings for hosts running Windows, macOS, and Linux are provided, and target C, C++, C#, Python, Java, Ruby, and MATLAB. The FrontPanel SDK differs from other debuggers in that it provides a skeleton module into which the user logic is instantiated, instead of being instantiated inside the user's logic. +Unlike other entries in this list, Opal Kelly's FrontPanel SDK is not marketed as a debugger (although it can be used as such). Instead, it's designed to provide a host computer with a real time interface to FPGA signals, and present them on a graphical “front panel". These front panels exist as a GUI window on the host, and contain buttons, knobs, and indicators, much like a LabVIEW virtual instrument. Communication between the host and FPGA is accomplished with either USB or PCIe. Bindings for hosts running Windows, macOS, and Linux are provided, and target C, C++, C#, Python, Java, Ruby, and MATLAB. The FrontPanel SDK differs from other debuggers in that it provides a skeleton module into which the user logic is instantiated, instead of being instantiated inside the user's logic. - [Documentation](https://docs.opalkelly.com/fpsdk/) - [User's Guide](https://assets00.opalkelly.com/library/FrontPanel-UM.pdf) diff --git a/doc/architecture.md b/doc/architecture.md index be7f57b..588ab59 100644 --- a/doc/architecture.md +++ b/doc/architecture.md @@ -2,19 +2,19 @@ The whole system looks like the following: -![](assets/system_architecture.drawio.svg){:style="width:80%"} +

    Manta is operated via its Python API, which communicates with the connected FPGA over an interface API like `pySerial` or `Scapy`. These abstract away the OS device drivers, which function differently depending on the host machine's platform. The OS device drivers ultimately send out bytes to the FPGA, across either a USB or Ethernet cable. -Once sent across the wire, bytes are picked up by an interface transciever on the FPGA development board. This is either a USB-UART converter or a RMII PHY depending on if you're using UART or Ethernet. This chip is connected to the FPGA's IO, which routes the signals to the Verilog module generated by Manta. This module parses incoming messages, passes them down a set of daisy-chained cores, and then packetizes it and sends it back to the host. +Once sent across the wire, bytes are picked up by an interface transceiver on the FPGA development board. This is either a USB-UART converter or a RMII PHY depending on if you're using UART or Ethernet. This chip is connected to the FPGA's IO, which routes the signals to the Verilog module generated by Manta. This module parses incoming messages, passes them down a set of daisy-chained cores, and then packetizes it and sends it back to the host. ## Manta Architecture The logic Manta places on the FPGA consists of a series of cores connected in a chain along a common bus. Each core provides a unique method for interacting with the user’s logic, which it connects to by routing signals (called _probes_) between the user’s logic and the cores that interface with it. -![](assets/bus_architecture.drawio.svg){:style="width:40%"} +
    -These probes are presented as addressable memory, and are be controlled by reading and writing to their corresponing memory - not unlike registers on a microcontroller. Each core is allotted a section of address space at compile time, and operations addressed to a core’s address space control the behavior of the core. These cores are then daisy-chained along an internal bus, which permits a chain arbitrarily many cores to be placed on the bus. +These probes are presented as addressable memory, and are be controlled by reading and writing to their corresponding memory - not unlike registers on a microcontroller. Each core is allotted a section of address space at compile time, and operations addressed to a core’s address space control the behavior of the core. These cores are then daisy-chained along an internal bus, which permits a chain arbitrarily many cores to be placed on the bus. At the beginning of this chain is a module called a _receive bridge_, which converts incoming UART/Ethernet communication from the host into read and write requests, which are placed on the bus. These are called _bus transactions_, and once placed on the bus, they travel through each core before reaching the _transmit bridge_ at the end of the chain. This module places the result of the bus transaction back on the UART/Ethernet interface, and sends it back to the host. This produces a request-response style of communication between the host machine and the FPGA. @@ -37,7 +37,7 @@ Each core has a bus input and output port, so that cores can be daisy-chained to Ethernet and UART both allow a stream of bytes to be sent between the host and FPGA, but since they're just interfaces, they don't define how these bytes are structured. As a result, Manta implements its own messaging format, with the following structure: -![](assets/uart_packets.drawio.svg){:style="width:85%"} +
    Each of these messages is a string of ASCII characters consisting of a preamble, optional address and data fields, and an End of Line (EOL). The preamble denotes the type of operation, _R_ for a read and _W_ for a write. The address and data fields are encoded as hexadecimal digits, represented with the characters 0-9 and A-F in ASCII. As a result, four characters are needed to encode a 16-bit address or 16-bits of data. If the message specifies a write request, then it will contain a data field after the address field. Both request types will conclude with an End of Line, which consists of the two ASCII characters indicating a Carriage Return (CR) and a Line Feed (LF). @@ -64,7 +64,7 @@ When UART is used, these bytes are transmitted directly across the wire, but whe This is done with the architecture shown below: -![](assets/io_core_architecture.drawio.svg){:style="width:49%"} +
    Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple. @@ -73,7 +73,7 @@ Whatever the number of registers required, these are read from and written to by ## Logic Analyzer The Logic Analyzer Core's implementation on the FPGA consists of three primary components: -![](assets/logic_analyzer_architecture.drawio.svg){style="width:85%"} +
    - The _Finite State Machine (FSM)_, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains. - The _Trigger Block_, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the $N$-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's `trig` input. @@ -84,8 +84,7 @@ The Logic Analyzer Core's implementation on the FPGA consists of three primary c Each Memory core is actually a set of 16-bit wide BRAMs with their ports concatenated together, with any spare bits masked off. Here's a diagram: -![](assets/memory_architecture.drawio.svg) - +
    Since each $n$-bit wide block memory is actually $ceil(n/16)$ BRAMs under the hood, addressing the BRAMs correctly from Manta's internal bus is important. BRAMs are organized such that each 16-bit slice of a $N$-bit word in the Block Memory core are placed next to each other in bus address space. For instance, a 34-bit wide block memory would exist on Manta's internal bus as: diff --git a/doc/assets/bus_architecture.drawio.svg b/doc/assets/bus_architecture.drawio.svg index e4858e0..a8b8077 100644 --- a/doc/assets/bus_architecture.drawio.svg +++ b/doc/assets/bus_architecture.drawio.svg @@ -1,8 +1,68 @@ - - + + + + + - + diff --git a/doc/assets/io_core_architecture.drawio.svg b/doc/assets/io_core_architecture.drawio.svg index d5b5064..65f936d 100644 --- a/doc/assets/io_core_architecture.drawio.svg +++ b/doc/assets/io_core_architecture.drawio.svg @@ -1,122 +1,182 @@ - - + + + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + -
    +
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    output_0
    - + output_0 - - - + + + -
    +
    -
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    - + output_n - - + + -
    +
    -
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    - + bus - + -
    +
    -
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    - + input_n - - - + + + -
    +
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    strobe
    - + strobe - + -
    +
    -
    +

    IO Core

    @@ -124,37 +184,37 @@
    - + IO Core - - - + + + -
    +
    -
    +
    input_0
    - + input_0 - + -
    +
    -
    +
    ... @@ -162,165 +222,165 @@
    - + ... - + -
    +
    -
    +
    input_0 buffer
    - + input_0 buffer - + -
    +
    -
    +
    input_n buffer
    - + input_n buffer - + -
    +
    -
    +
    output_n buffer
    - + output_n buffer - - + + -
    +
    -
    +
    bus
    - + bus - - + + -
    -
    -
    +
    +
    +
    output_0
    - + output_0 - + -
    +
    -
    +
    output_0 buffer
    - + output_0 buffer - - + + -
    -
    -
    +
    +
    +
    input_0
    - + input_0 - - + + -
    -
    -
    +
    +
    +
    output_n
    - + output_n - - + + -
    -
    -
    +
    +
    +
    input_n
    - + input_n diff --git a/doc/assets/io_core_memory_map.drawio.svg b/doc/assets/io_core_memory_map.drawio.svg deleted file mode 100644 index 35576a4..0000000 --- a/doc/assets/io_core_memory_map.drawio.svg +++ /dev/null @@ -1,251 +0,0 @@ - - - - - - - -
    -
    -
    - foo[4:0] -
    -
    -
    -     - - foo[4:0] - -     -     - - - - -
    -
    -
    - bar[15:0] -
    -
    -
    -     - - bar[15:0] - -     -     - - - - -
    -
    -
    - baz[31:16] -
    -
    -
    -     - - baz[31:16] - -     -     - - - - -
    -
    -
    - baz[15:0] -
    -
    -
    -     - - baz[15:0] - -     -     - - - - -
    -
    -
    - zero pad -
    -
    -
    -     - - zero pad - -     -     - - - - -
    -
    -
    - baz[36:32] -
    -
    -
    -     - - baz[36:32] - -     -     - - - - -
    -
    -
    - zero pad -
    -
    -
    -     - - zero pad - -     -     - - - - -
    -
    -
    - 0x0000 -
    -
    -
    -     - - 0x0000 - -     -     - - - - -
    -
    -
    - 0x0001 -
    -
    -
    -     - - 0x0001 - -     -     - - - - -
    -
    -
    - 0x0002 -
    -
    -
    -     - - 0x0002 - -     -     - - - - -
    -
    -
    - 0x0003 -
    -
    -
    -     - - 0x0003 - -     -     - - - - -
    -
    -
    - 0x0004 -
    -
    -
    -     - - 0x0004 - -     -     - - - - -
    -
    -
    - 0 -
    -
    -
    -     - - 0 - -     -     - - - - -
    -
    -
    - 16 -
    -
    -
    -     - - 16 - -     -     -     - - - - - Text is not SVG - cannot display - - - -     \ No newline at end of file diff --git a/doc/assets/logic_analyzer_architecture.drawio.svg b/doc/assets/logic_analyzer_architecture.drawio.svg index c2123ab..4f3dc26 100644 --- a/doc/assets/logic_analyzer_architecture.drawio.svg +++ b/doc/assets/logic_analyzer_architecture.drawio.svg @@ -1,14 +1,76 @@ - - + + + + - - + + + -
    +
    -
    +
    block
    memory @@ -16,55 +78,55 @@
    - + block... - - + + -
    +
    -
    +
    bus
    - + bus - - - + + + -
    +
    -
    +
    bus
    - + bus - + -
    +
    -
    +
    fsm
    registers @@ -72,389 +134,389 @@
    - + fsm... - + -
    +
    -
    +
    fsm
    - + fsm - - + + -
    +
    -
    +
    bus
    - + bus - + -
    +
    -
    +
    trigger registers
    - + trigger re... - + -
    +
    -
    +
    trigger
    - + trigger - - + + -
    +
    -
    +
    arg
    - + arg - - + + -
    +
    -
    +
    op
    - + op - + -
    +
    -
    +
    trigger
    - + trigger - - + + -
    +
    -
    +
    arg
    - + arg - - + + -
    +
    -
    +
    op
    - + op - - + + -
    +
    -
    +
    trigger_mode
    - + trigger_mode - - + + -
    +
    -
    +
    request_start
    - + request_start - - + + -
    +
    -
    +
    request_stop
    - + request_stop - - + + -
    +
    -
    +
    read_pointer
    - + read_pointer - - + + -
    +
    -
    +
    write_pointer
    - + write_pointer - - + + -
    +
    -
    +
    state
    - + state - - + + -
    +
    -
    +
    trigger_location
    - + trigger_location - + -
    +
    -
    +
    ...
    - + ... - - + + -
    +
    -
    +
    bus
    - + bus - + -
    +
    -
    +
    port A
    - + port A - - + + -
    +
    -
    +
    data
    - + data - + -
    +
    -
    +
    port B
    - + port B - + -
    +
    -
    +

    Trigger Block @@ -464,121 +526,121 @@

    - + Trigger Block - - + + -
    +
    -
    +
    trig
    - + trig - + -
    +
    -
    +
    OR
    - + OR - - + + -
    +
    -
    +
    - + - - + + -
    +
    -
    +
    probe_2
    - + probe_2 - + -
    +
    -
    +
    - + - - + + -
    +
    -
    +
    probe_1
    - + probe_1 - - + + -
    +
    -
    +

    Logic Analyzer

    @@ -586,96 +648,96 @@
    - + Logic Analyzer - - + + -
    +
    -
    +
    probe_0
    - + probe_0 - + -
    +
    -
    +
    trigger
    - + trigger - - + + -
    +
    -
    +
    arg
    - + arg - - + + -
    +
    -
    +
    op
    - + op - - + + -
    +
    -
    +
    we
    - + we @@ -683,33 +745,33 @@ -
    +
    -
    +
    we
    - + we - - + + -
    +
    -
    +
    addr
    - + addr @@ -717,25 +779,25 @@ -
    +
    -
    +
    addr
    - + addr - - - - - - + + + + + + diff --git a/doc/assets/memory_architecture.drawio.svg b/doc/assets/memory_architecture.drawio.svg index ca3a1c9..ef58678 100644 --- a/doc/assets/memory_architecture.drawio.svg +++ b/doc/assets/memory_architecture.drawio.svg @@ -1,475 +1,537 @@ - - + + + + - - + + + -
    +
    -
    +
    block RAM
    - + block RAM - + -
    +
    -
    +
    port A
    - + port A - - + + -
    +
    -
    +
    addr
    - + addr - - + + -
    +
    -
    +
    din
    - + din - - + + -
    +
    -
    +
    dout
    - + dout - - + + -
    +
    -
    +
    we
    - + we - + -
    +
    -
    +
    port B
    - + port B - + -
    +
    -
    +
    Bus Controller
    - + Bus Controller - + -
    +
    -
    +
    block RAM
    - + block RAM - + -
    +
    -
    +
    port A
    - + port A - + -
    +
    -
    +
    port B
    - + port B - - - - - + + + + + -
    +
    -
    +
    user_addr
    - + user_addr - - + + -
    +
    -
    +
    user_din
    - + user_din - - + + -
    +
    -
    +
    user_dout
    - + user_dout - - + + -
    +
    -
    +
    user_we
    - + user_we - - + + -
    +
    -
    +
    addr
    - + addr - - + + -
    +
    -
    +
    din
    - + din - - + + -
    +
    -
    +
    dout
    - + dout - - + + -
    +
    -
    +
    we
    - + we - + -
    +
    -
    +
    block RAM
    - + block RAM - + -
    +
    -
    +
    port A
    - + port A - + -
    +
    -
    +
    port B
    - + port B - - + + -
    +
    -
    +
    addr
    - + addr - - + + -
    +
    -
    +
    din
    - + din - - + + -
    +
    -
    +
    dout
    - + dout - - + + -
    +
    -
    +
    we
    - + we - + -
    +
    -
    +
    ... @@ -479,111 +541,111 @@
    - + ... - - - + + + -
    +
    -
    +
    16 bits
    - + 16 bits - - - + + + -
    +
    -
    +
    16 bits
    - + 16 bits - - - + + + -
    +
    -
    +
    10 bits
    - + 10 bits - - + + -
    +
    -
    +
    bus
    - + bus - - + + -
    +
    -
    +
    bus
    - + bus - + -
    +
    -
    +

    Memory Core

    @@ -591,7 +653,7 @@
    - + Memory Core diff --git a/doc/assets/system_architecture.drawio.svg b/doc/assets/system_architecture.drawio.svg index 930a0c7..6e01b9f 100644 --- a/doc/assets/system_architecture.drawio.svg +++ b/doc/assets/system_architecture.drawio.svg @@ -1,15 +1,133 @@ - - + + + + - - - + + + + + + + + -
    +
    +
    +
    + Manta API +
    +
    +
    + + + Manta API + + + + + + + +
    +
    +
    + OS Device Driver +
    +
    +
    +     + + OS Device Driver + +     +     + + + + + + + +
    +
    +
    + Your Code! +
    +
    +
    +     + + Your Code! + +     +     + + + + +
    -
    +

    Host Machine

    @@ -17,305 +135,93 @@
    - + Host Machine - - - + -
    +
    -
    - User Application -
    -
    -
    - - - User Application - - - - - - - - - -
    -
    -
    - Manta API -
    -
    -
    -     - - Manta API - -     -     - - - - - - -
    -
    -
    - Interface API -
    -
    -
    -     - - Interface API - -     -     - - - - - -
    -
    -
    - USB/Ethernet Cable -
    -
    -
    -     - - USB/Ethernet Cable - -     -     - - - - -
    -
    -
    - OS Device Driver -
    -
    -
    -     - - OS Device Driver - -     -     - - - - -
    -
    -
    - Interface Transceiver -
    -
    - (USB UART -
    - Converter / Ethernet PHY) -
    -
    -
    -     - - Interface Trans... - -     -     - - - - - - -
    -
    -
    - rxd -
    -
    -
    -     - - rxd - -     -     - - - - -
    -
    -
    - bridge_rx -
    -
    -
    -     - - bridge_rx - -     -     - - - - -
    -
    -
    +
    logic_analyzer
    - + logic_analyzer - + -
    +
    -
    +
    io_core
    - + io_core - + -
    +
    -
    +
    block_memory
    - + block_memory - + -
    +
    -
    - bridge_tx +
    + Your RTL!
    - - bridge_tx + + Your RTL! - - - - - - - - - + + + + + + + + -
    -
    -
    - User Logic -
    -
    -
    -     - - User Logic - -     -     - - - - - - - - - - - - -
    -
    -
    - txd -
    -
    -
    -     - - txd - -     -     - - - - -
    -
    -
    -

    - FPGA Development Board -

    -
    -
    -
    -     - - FPGA Development Board - -     -     - - - - -
    -
    -
    +
    +
    +

    Manta RTL @@ -325,11 +231,110 @@

    - + Manta RTL + + + + +
    +
    +
    +

    + FPGA Development Board +

    +
    +
    +
    +     + + FPGA Development Board + +     +     + + + + + + + + + +
    +
    +
    + Network +
    + Connection +
    +
    +
    +     + + Network... + +     +     + + + + +
    +
    +
    + Ethernet PHY +
    +
    +
    +     + + Ethernet PHY + +     +     + + + + + + + + + +
    +
    +
    + USB Cable +
    +
    +
    +     + + USB Cable + +     +     + + + + +
    +
    +
    + USB-UART Converter +
    +
    +
    +     + + USB-UART Conver... + +     +     diff --git a/doc/assets/uart_packets.drawio.svg b/doc/assets/uart_packets.drawio.svg index b6c1fa6..e3cc3b0 100644 --- a/doc/assets/uart_packets.drawio.svg +++ b/doc/assets/uart_packets.drawio.svg @@ -1,758 +1,821 @@ - - + + + + - + + -
    +
    -
    +
    W
    - + W - + -
    +
    -
    +
    8
    - + 8 - + -
    +
    -
    +
    9
    - + 9 - + -
    +
    -
    +
    A
    - + A - + -
    +
    -
    +
    B
    - + B - + -
    +
    -
    +
    CR
    - + CR - + -
    +
    -
    +
    LF
    - + LF - - - + + + -
    +
    -
    +
    Write Address
    - + Write Address - - - + + + -
    +
    -
    +
    End Of Line
    - + End Of Line - - - + + + -
    +
    -
    +
    Preamble
    - + Preamble - + -
    +
    -
    +
    0
    - + 0 - + -
    +
    -
    +
    8
    - + 8 - + -
    +
    -
    +
    16
    - + 16 - + -
    +
    -
    +
    24
    - + 24 - + -
    +
    -
    +
    32
    - + 32 - + -
    +
    -
    +
    48
    - + 48 - + -
    +
    -
    +
    56
    - + 56 - + -
    +
    -
    +
    C
    - + C - + -
    +
    -
    +
    D
    - + D - + -
    +
    -
    +
    E
    - + E - + -
    +
    -
    +
    F
    - + F - - - + + + -
    +
    -
    +
    Write Data
    - + Write Data - + -
    +
    -
    +
    64
    - + 64 - + -
    +
    -
    +
    72
    - + 72 - + -
    +
    -
    +
    80
    - + 80 - + -
    +
    -
    +
    88
    - + 88 - + -
    +
    -
    +
    R
    - + R - + -
    +
    -
    +
    0
    - + 0 - + -
    +
    -
    +
    1
    - + 1 - + -
    +
    -
    +
    2
    - + 2 - + -
    +
    -
    +
    3
    - + 3 - + -
    +
    -
    +
    CR
    - + CR - + -
    +
    -
    +
    LF
    - + LF - - - + + + -
    +
    -
    +
    Read Address
    - + Read Address - - - + + + -
    +
    -
    +
    End Of Line
    - + End Of Line - - - + + + -
    +
    -
    +
    Preamble
    - + Preamble - + -
    +
    -
    +
    0
    - + 0 - + -
    +
    -
    +
    8
    - + 8 - + -
    +
    -
    +
    16
    - + 16 - + -
    +
    -
    +
    24
    - + 24 - + -
    +
    -
    +
    32
    - + 32 - + -
    +
    -
    +
    48
    - + 48 - + -
    +
    -
    +
    56
    - + 56 - + -
    +
    -
    +

    Read Request

    @@ -760,18 +823,18 @@
    - + Read Request - + -
    +
    -
    +

    Read Response

    @@ -779,18 +842,18 @@
    - + Read Response - + -
    +
    -
    +

    Write Request

    @@ -798,313 +861,313 @@
    - + Write Request - + -
    +
    -
    +
    D
    - + D - + -
    +
    -
    +
    4
    - + 4 - + -
    +
    -
    +
    5
    - + 5 - + -
    +
    -
    +
    6
    - + 6 - + -
    +
    -
    +
    7
    - + 7 - + -
    +
    -
    +
    CR
    - + CR - + -
    +
    -
    +
    LF
    - + LF - - - + + + -
    +
    -
    +
    Read Data
    - + Read Data - - - + + + -
    +
    -
    +
    End Of Line
    - + End Of Line - - - + + + -
    +
    -
    +
    Preamble
    - + Preamble - + -
    +
    -
    +
    0
    - + 0 - + -
    +
    -
    +
    8
    - + 8 - + -
    +
    -
    +
    16
    - + 16 - + -
    +
    -
    +
    24
    - + 24 - + -
    +
    -
    +
    32
    - + 32 - + -
    +
    -
    +
    48
    - + 48 - + -
    +
    -
    +
    56
    - + 56 - + -
    +
    -
    +

    Write Response

    @@ -1112,18 +1175,18 @@
    - + Write Response - + -
    +
    -
    +
    No Response @@ -1131,7 +1194,7 @@
    - + No Response diff --git a/doc/ethernet_interface.md b/doc/ethernet_interface.md index 416c31b..e78ae9b 100644 --- a/doc/ethernet_interface.md +++ b/doc/ethernet_interface.md @@ -1,15 +1,39 @@ -!!! warning "This section is under construction!" - - The Ethernet interface is just about to get refactored to implement a few performance gains, so what's here represents the Ethernet interface circa April 2023. Hang tight for new stuff! - ## Overview -For situations where the onboard UART is not available, Manta provides a 100Mbps Ethernet link for communicating between the host machine and target FPGA. This link implements a L2 MAC on the FPGA, designed to be directly connected to a host machine on a dedicated network adapter. The MAC is controlled by a bridge interface, which performs the exact same function as it does on the UART interface. Incoming packets are parsed into bus transactions, placed on the bus, and any response data is encapsulated into another packet sent to the host. +For scenarios where UART is not available or higher bandwidth is desired, Manta provides an Ethernet interface for communicating between the host and FPGA. This interface uses UDP for communication, and leverages the builtin Python `sockets` module on the host side, and the open-source [LiteEth](https://github.com/enjoy-digital/liteeth) Ethernet core on the FPGA side. -This is done by interacting with an Ethernet PHY, an onboard transceiver IC that converts between the FPGA's logic-level signaling and the voltages on the cable's twisted pairs. The communication between the Ethernet PHY and the FPGA is done over an interface that's dependent on the speed of the PHY. The 10/100 Mbps interface used on the Nexys A7-100T uses the RMII as defined in IEEE 802.3u. RMII is the second-oldest member in the Media Independent Interface family, with newer revisions of 802.3 supporting faster interfaces. +!!! warning "Not every device is supported!" -Manta's bus clock must be equivalent to the PHY's reference clock if Ethernet is to be used - in the case of the 100Mbps RMII PHY on the Nexys A7 used in 6.205, this is 50MHz. This doesn't pose a problem for user logic, which is connected through Manta's cores that perform CDC internally. It does mean that a reference clock for the PHY has to be synthesized outside of Manta itself, and the means by which this is done varies by FPGA vendor and toolchain. + Although Manta aims to be as platform-agnostic as possible, Ethernet PHYs and FPGA clock primitives are very particular devices. As a result, the supported devices are loosely restricted to those on [this list](https://github.com/enjoy-digital/liteeth?tab=readme-ov-file#-features). If a device you'd like to use isn't on the list, the community would love your help! -This MAC allows for the usage of packets with the structure shown below. The bus transaction being communicated is placed at the beginning of the packet's payload field, which IEEE 802.3 allows to vary in length from 46 to 1500 bytes. The 46-byte lower limit requires 41 bytes of zero padding to be added to the five bytes used to specify a bus transaction, and only one bus transactions is specified in each Ethernet frame. This abundance of unused space results in all packets being the same length, whether the packet contains a read request, write request, or read response. Packets containing write requests elicit no response from the FPGA, just as write requests delivered over UART produce no response. +Although UDP does not guarantee reliable packet delivery, this usually doesn't pose an issue in practice. Manta will throw a runtime error if packets are dropped, and the UDP checksum and Ethernet FCS guarantee that any data delivered is not corrupted. Together, these two behaviors prevent corrupted data from being provided to the user, as Manta will error before returning invalid data. As long as your network is not terribly congested, Manta will operate without issue. +## Configuration -These packets are addressed directly to the host's MAC address, which is obtained during code autogeneration. These packets also use a fixed Ethertype of `0x88B5`, which is specially reserved for "public use and for prototype and vendor-specific protocol development" in IEEE 802.1. This was done to create an Ethernet II frame instead of a legacy 802.3 frame, without having to implement a higher level protocol like TCP or UDP to safely use a fixed Ethertype. This allows the MAC to use modern Ethernet II frames safely, but save FPGA resources. \ No newline at end of file +The configuration of the Ethernet core is best shown by example: +```yaml +ethernet: + phy: LiteEthPHYRMII + vendor: xilinx + toolchain: vivado + + clk_freq: 50e6 + refclk_freq: 50e6 + + fpga_ip_addr: "192.168.0.110" + host_ip_addr: "192.168.0.100" +``` +This snippet at the end of the configuration file defines the interface. The following parameters must be set: + +- `phy` _(required)_: The name of the LiteEth PHY class to use. Valid values consist of any of the names in [this list](https://github.com/enjoy-digital/liteeth/blob/b4e28506238c5340f2ade7899c2223424cabd410/liteeth/phy/__init__.py#L25-L45). Select the appropriate one for your FPGA vendor and family. + +- `vendor` _(required)_: The vendor of the FPGA being designed for. Currently only values of `xilinx` and `lattice` are supported. Used to generate timing constraints files, which are currently unused. + +- `toolchain` _(required)_: The toolchain being used. Currently only values of `vivado` and `diamond` are supported. + +- `clk_freq` _(required)_: The frequency of the clock provided to the Manta instance. Used to configure a PLL in the FPGA fabric for generating the PHY's `refclk`. + +- `refclk_freq` _(required)_: The frequency of the reference clock to be provided to the Ethernet PHY. This clock is generated from Manta's main clock using a PLL inside the FPGA. This frequency must match the MII variant supported by the PHY, as well as speed that the PHY is being operated at. For instance, a RGMII PHY may be operated at either 125MHz in Gigabit mode, or 25MHz in 100Mbps mode. + +- `fpga_ip_addr` _(required)_: The IP address the FPGA will attempt to claim. Upon power-on, the FPGA will issue a DHCP request for this IP address. The easiest way to check if this was successful is by pinging the FPGA's IP, but if you have access to your network's router it may report a list of connected devices. + +- `host_ip_addr` _(required)_: The IP address of the host machine, which the FPGA will send packets back to. diff --git a/doc/index.md b/doc/index.md index 41bae4d..3aada17 100644 --- a/doc/index.md +++ b/doc/index.md @@ -49,7 +49,7 @@ You may find this core useful for: ## About Manta and its source code are released under a [GPLv3 license](https://github.com/fischermoseley/manta/blob/main/LICENSE.txt), and it was originally developed as part of my [Master's Thesis at MIT](https://hdl.handle.net/1721.1/151223) in 2023, done under the supervision of [Dr. Joe Steinmeyer](https://www.jodalyst.com/). The thesis itself is copyrighted by Fischer Moseley (me!), but feel free to use the following Bibtex if you'd like to cite it: -``` +```bibtex @misc{manta2023, author={Fischer Moseley}, title={Manta: An In-Situ Debugging Tool for Programmable Hardware}, diff --git a/doc/installation.md b/doc/installation.md index 9141181..8fc2624 100644 --- a/doc/installation.md +++ b/doc/installation.md @@ -1,20 +1,20 @@ Before installing, make sure to upgrade your `pip` to the latest version: -``` +```bash pip install --upgrade pip ``` ## Latest Version You can install the latest version of Manta directly from source with: -``` +```bash pip install --upgrade git+https://github.com/fischermoseley/manta.git ``` ## Editable Development Install If you're working on the source, you might want an editable installation with some extra dependencies used for development: -``` +```bash git clone https://github.com/fischermoseley/manta.git cd manta pip install -e ".[dev]" @@ -29,14 +29,15 @@ Later Manta will be availabe on the PyPI lists, and you'll be able to just `pip ## Dependencies Manta requires the following dependencies: -- Amaranth HDL, which comes with it's own built-in copy of Yosys. -- pyYAML, which is used for parsing configuration files written in YAML. -- pySerial, used for communicating with the FPGA over UART. -- pyVCD, used for writing waveforms captured by the Logic Analyzer Core to standard Value Change Dump (VCD) files. +- [Amaranth HDL](https://amaranth-lang.org/docs/amaranth/latest/), which comes with it's own built-in copy of Yosys. +- [LiteEth](https://github.com/enjoy-digital/liteeth), for sending and receiving UDP packets on the FPGA. +- [pySerial](https://pyserial.readthedocs.io/en/latest/index.html), for communicating with the FPGA over UART. +- [pyYAML](https://pyyaml.org/), for parsing configuration files written in YAML. +- [pyVCD](https://github.com/westerndigitalcorporation/pyvcd), for writing waveforms captured by the Logic Analyzer Core to standard Value Change Dump (VCD) files. As well as these dependencies for development, which are installed with the `[dev]` argument: -- Pytest, for testing. -- Black, used for formatting the Python source. -- mkdocs-material, for generating the documentation site. -- amaranth_boards, for building designs for hardware-in-the-loop testing done by the CI. +- [Pytest](https://pytest.org/), for unit testing. +- [Black](https://black.readthedocs.io/en/stable/), for formatting the Python source. +- [mkdocs-material](https://squidfunk.github.io/mkdocs-material/), for generating the documentation site. +- [amaranth_boards](https://github.com/amaranth-lang/amaranth-boards), for building designs for hardware-in-the-loop testing done by the CI. diff --git a/doc/io_core.md b/doc/io_core.md index ba86a53..da61255 100644 --- a/doc/io_core.md +++ b/doc/io_core.md @@ -32,7 +32,7 @@ Inside this configuration, the following parameters may be configured: - `name` _(required)_: The name of the IO core. This name is used to reference the core when working with the API, and can be whatever you'd like. - `type` _(required)_: This denotes that this is an IO core. All cores contain a `type` field, which must be set to `io` to be recognized as an IO core. - `inputs` _(optional)_: This lists all inputs from from the FPGA fabric to the host machine. Signals in this list may be read by the host, but ___cannot___ be written to. Technically specifying input probes is totally optional - it's perfectly fine to have an IO core with only output probes. -- `outputs` _(optional)_: This lists all outputs from the host machine to the FPGA fabric. Signals in this list are usually written to by the host, but they can also be read from. Doing so returns the value last written to the register. Just like the `inputs` parameter, this list is techically optional, and it's perfectly valid to have an IO core with input probes only. +- `outputs` _(optional)_: This lists all outputs from the host machine to the FPGA fabric. Signals in this list are usually written to by the host, but they can also be read from. Doing so returns the value last written to the register. Just like the `inputs` parameter, this list is technically optional, and it's perfectly valid to have an IO core with input probes only. - `initial_value` _(optional)_: This sets an initial value for an output probe to take after the FPGA powers on. This is done with an `initial` statement in Manta's Verilog, and is independent of the input clock or resets elsewhere in the FPGA. This parameter is optional, and if it isn't provided the probe will initialize to zero. - `user_clock` _(optional)_: If set to True, an extra input port will be added to the `manta` module for an clock input to run the IO core on. This lets the IO Core handle clock domain crossing through its internal buffers. If set to False, Manta will run the IO core from its internal clock (the one provided through `manta`'s `clk` port). More information on this is available in the [diagram](#how-it-works) below. This parameter is optional, and defaults to False. @@ -50,7 +50,7 @@ The IO core functionality is stored in the `Manta.IOCore`, `Manta.InputProbe`, a - [`int`, `bool`] _data_: The value to write to an output probe. May be signed or unsigned, but will raise an exception if the value is too large for the width of the port. - _returns_: None -This method is blocking. When called it will dispatch a request to the FPGA, and wait until a response has been receieved. +This method is blocking. When called it will dispatch a request to the FPGA, and wait until a response has been received. --- @@ -58,7 +58,7 @@ This method is blocking. When called it will dispatch a request to the FPGA, and - _returns_: The value of an input or output probe. In the case of an output probe, the value returned will be the last value written to the probe. -This method is blocking. When called it will dispatch a request to the FPGA, and wait until a response has been receieved. +This method is blocking. When called it will dispatch a request to the FPGA, and wait until a response has been received. --- @@ -84,4 +84,4 @@ While the IO core performs a very, very simple task, it carries a few caveats. - First, __it's not instantaneous__. Manta has designed to be as fast as possible, but setting and querying registers relies on passing messages between the host and FPGA, which is slow relative to FPGA clock speeds! If you're trying to set values in your design with cycle-accurate timing, this will not do that for you. However, the [Logic Analyzer's playback feature](./logic_analyzer_core.md#playback) might be helpful. -- Second, __the API methods are blocking__, and will wait for a response from the FPGA before resuming program execution. Depending on your application, you might want to run your IO Core operations in a seperate thread, but you can also decrease the execution time by using a faster interface between the host and FPGA. This means using a higher UART baudrate, or using Ethernet. +- Second, __the API methods are blocking__, and will wait for a response from the FPGA before resuming program execution. Depending on your application, you might want to run your IO Core operations in a separate thread, but you can also decrease the execution time by using a faster interface between the host and FPGA. This means using a higher UART baudrate, or using Ethernet. diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index 50debe6..450f20d 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -60,14 +60,14 @@ Each individual trigger is specified with the following structure: - `EQ`, for equal to. - `NEQ`, for not equal to. - These operations require a constant to compare against, referred to as an _argument_, which is descirbed below: + These operations require a constant to compare against, referred to as an _argument_, which is described below: - __argument__: A constant to compare against, if the operation specified requires one. On the FPGA, the argument will have just as many bits as the probe width. -Lastly, if you're not able to express your desired trigger condition in terms of the operators above, fear not! You can also specifiy an `external_trigger: true` entry in the config file, which exposes an input on Manta's top level for your own trigger. +Lastly, if you're not able to express your desired trigger condition in terms of the operators above, fear not! You can also specify an `external_trigger: true` entry in the config file, which exposes an input on Manta's top level for your own trigger. ### Trigger Position (optional) -Sometimes, you care more about what happens before a trigger is met than afterwards, or vice versa. To accomodate this, the logic analyzer has an optional _Trigger Position_ parameter, which sets when probe data is captured relative to the trigger condition being met. This is specified with the `trigger_position` entry in the configuration file, which sets how many samples to save prior to the trigger condition occuring. This is best explained with a picture: +Sometimes, you care more about what happens before a trigger is met than afterwards, or vice versa. To accommodate this, the logic analyzer has an optional _Trigger Position_ parameter, which sets when probe data is captured relative to the trigger condition being met. This is specified with the `trigger_position` entry in the configuration file, which sets how many samples to save prior to the trigger condition occurring. This is best explained with a picture: ![](assets/trigger_positions.png){style="width:90%"} diff --git a/doc/memory_core.md b/doc/memory_core.md index 7189648..26109f8 100644 --- a/doc/memory_core.md +++ b/doc/memory_core.md @@ -68,6 +68,6 @@ A Block Memory core is used in the [video_sprite](https://github.com/fischermose Since Manta's [data bus](architecture.md#data-bus) is only 16-bits wide, it's only possible to manipulate the BRAM core in 16-bit increments. This means that if you have a BRAM that's ≤16 bits wide, you'll only need to issue a single bus transaction to read/write one entry in the BRAM. However, if you have a BRAM that's ≥16 bits wide, you'll need to issue a bus transaction to update each 16-bit slice of it. For instance, updating a single entry in a 33-bit wide BRAM would require sending 3 messages to the FPGA: one for bits 1-16, another for bits 17-32, and one for bit 33. If your application expects each BRAM entry to update instantaneously, this could be problematic. -There's a few different ways to solve this - you could use an IO core to signal when a BRAM's contents or valid - or you could ping-pong between two BRAMs while one is being modified. The choice is yours, and Manta makes no attempt to presribe any particular approach. +There's a few different ways to solve this - you could use an IO core to signal when a BRAM's contents or valid - or you could ping-pong between two BRAMs while one is being modified. The choice is yours, and Manta makes no attempt to prescribe any particular approach. Lastly, the interface you use (and to a lesser extent, your operating system) will determine the space between bus transactions. For instance, 100Mbit Ethernet is a thousand times faster than 115200bps UART, so the time where the BRAM is invalid is a thousand times smaller. diff --git a/doc/uart_interface.md b/doc/uart_interface.md index 847f52b..8813004 100644 --- a/doc/uart_interface.md +++ b/doc/uart_interface.md @@ -12,7 +12,7 @@ uart: baudrate: 3000000 clock_freq: 100000000 ``` -This snippet defines the interface, and lives at the bottom of a Manta configuration file. Three parameters must be set: +This snippet at the end of the configuration file defines the interface. The following parameters must be set: - `port` _(required)_: The name of the serial port on the host machine that's connected to the FPGA. Depending on your platform, this could be `/dev/ttyUSBXX`, `/dev/tty.usbserialXXX`, or `COMX`. If set to `auto`, then Manta will try to find the right serial port by looking for a USB device with the same VID and PID as a FT2232 - a USB/UART converter chip that's super popular on FPGA dev boards. This doesn't always work, but it's super convenient when it does. If your port isn't automatically detected, then just specify the port manually. diff --git a/mkdocs.yml b/mkdocs.yml index ca1d1d0..67f50e5 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -17,18 +17,24 @@ theme: - navigation.expand palette: - - scheme: default - primary: custom - accent: light blue + - media: "(prefers-color-scheme)" toggle: - icon: material/brightness-7 - name: Switch to dark mode - - scheme: slate - primary: custom - accent: light blue - toggle: - icon: material/brightness-4 + icon: material/link name: Switch to light mode + - media: "(prefers-color-scheme: light)" + scheme: default + primary: blue + accent: custom + toggle: + icon: material/toggle-switch + name: Switch to dark mode + - media: "(prefers-color-scheme: dark)" + scheme: slate + primary: black + accent: custom + toggle: + icon: material/toggle-switch-off + name: Switch to system preference extra_css: - stylesheets/extra.css From 5e642101efe44d9f5f6cc114daa645da4463602a Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 10 Feb 2024 00:48:53 -0800 Subject: [PATCH 43/89] pass Ethernet config to LiteEth core generator --- src/manta/ethernet/__init__.py | 53 +++++++++++-------- src/manta/ethernet/liteeth_gen.py | 87 +++++++++++++++++++++++++++++-- 2 files changed, 114 insertions(+), 26 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index 4b16ee8..20ebf3c 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -192,38 +192,45 @@ class EthernetInterface(Elaboratable): sock.sendto(bytes_out, (self.fpga_ip_addr, self.udp_port)) def generate_liteeth_core(self): + """ + Generate a LiteEth core by calling a slightly modified form of the LiteEth + standalone core generator. This passes the contents of the 'ethernet' section + of the Manta configuration file to LiteEth, after modifying it slightly to + include the UDP ports and set a MAC address if the user didn't specify one. + """ + liteeth_config = self.config.copy() + # Randomly assign a MAC address if one is not specified in the configuration. # This will choose a MAC address in the Locally Administered, Administratively Assigned group. # For more information, see: # https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses - if "mac_address" not in self.config: - mac_address = list(f"{randint(0, (2**48) - 1):012x}") - mac_address[1] = "2" - mac_address = int("".join(mac_address), 16) + if "mac_address" not in liteeth_config: + addr = list(f"{randint(0, (2**48) - 1):012x}") + addr[1] = "2" + liteeth_config["mac_address"] = int("".join(addr), 16) - else: - mac_address = self.config["mac_address"] + # Force use of DHCP + liteeth_config["dhcp"] = True - liteeth_config = { - "phy": self.config["phy"], - "vendor": self.config["vendor"], - "toolchain": self.config["toolchain"], - "refclk_freq": self.config["refclk_freq"], - "clk_freq": self.config["clk_freq"], - "mac_address": mac_address, - "dhcp": True, - "data_width": 32, - "udp_ports": { - "udp0": { - "udp_port": self.udp_port, - "data_width": 32, - "tx_fifo_depth": 64, - "rx_fifo_depth": 64, - } - }, + # Use UDP + liteeth_config["core"] = "udp" + + # Use 32-bit words. Might be redundant, as I think using DHCP forces + # LiteEth to use 32-bit words + liteeth_config["data_width"] = 32 + + # Add UDP port + liteeth_config["udp_ports"] = { + "udp0": { + "udp_port": self.udp_port, + "data_width": 32, + "tx_fifo_depth": 64, + "rx_fifo_depth": 64, + } } # Generate the core from .liteeth_gen import main + return main(liteeth_config) diff --git a/src/manta/ethernet/liteeth_gen.py b/src/manta/ethernet/liteeth_gen.py index e07481e..5ba0f22 100755 --- a/src/manta/ethernet/liteeth_gen.py +++ b/src/manta/ethernet/liteeth_gen.py @@ -230,6 +230,8 @@ def get_udp_raw_port_ios(name, data_width): # PHY Core ----------------------------------------------------------------------------------------- + + class PHYCore(SoCMini): SoCMini.csr_map = { "ctrl": 0, @@ -322,8 +324,14 @@ class PHYCore(SoCMini): qpll_settings = QPLLSettings( refclksel=0b001, - fbdiv=4, - fbdiv_45={125e6: 5, 156.25e6: 4}[refclk_freq], + fbdiv={ + liteeth_phys.A7_1000BASEX: 4, + liteeth_phys.A7_2500BASEX: 5, + }[phy], + fbdiv_45={ + 125e6: 5, + 156.25e6: 4, + }[refclk_freq], refclk_div=1, ) qpll = QPLL(ethphy_pads.refclk, qpll_settings) @@ -371,7 +379,73 @@ class PHYCore(SoCMini): ) +# MAC Core ----------------------------------------------------------------------------------------- + + +class MACCore(PHYCore): + def __init__(self, platform, core_config): + # Parameters ------------------------------------------------------------------------------- + nrxslots = core_config.get("nrxslots", 2) + ntxslots = core_config.get("ntxslots", 2) + bus_standard = core_config["core"] + tx_cdc_depth = core_config.get("tx_cdc_depth", 32) + tx_cdc_buffered = core_config.get("tx_cdc_buffered", False) + rx_cdc_depth = core_config.get("rx_cdc_depth", 32) + rx_cdc_buffered = core_config.get("rx_cdc_buffered", False) + assert bus_standard in ["wishbone", "axi-lite"] + + # PHY -------------------------------------------------------------------------------------- + PHYCore.__init__(self, platform, core_config) + + # MAC -------------------------------------------------------------------------------------- + self.ethmac = ethmac = LiteEthMAC( + phy=self.ethphy, + dw=32, + interface="wishbone", + endianness=core_config["endianness"], + nrxslots=nrxslots, + ntxslots=ntxslots, + full_memory_we=core_config.get("full_memory_we", False), + tx_cdc_depth=tx_cdc_depth, + tx_cdc_buffered=tx_cdc_buffered, + rx_cdc_depth=rx_cdc_depth, + rx_cdc_buffered=rx_cdc_buffered, + ) + + if bus_standard == "wishbone": + # Wishbone Interface ----------------------------------------------------------------------- + wb_bus = wishbone.Interface() + platform.add_extension(wb_bus.get_ios("wishbone")) + self.comb += wb_bus.connect_to_pads( + self.platform.request("wishbone"), mode="slave" + ) + self.bus.add_master(master=wb_bus) + + if bus_standard == "axi-lite": + # AXI-Lite Interface ----------------------------------------------------------------------- + axil_bus = axi.AXILiteInterface(address_width=32, data_width=32) + platform.add_extension(axil_bus.get_ios("bus")) + self.submodules += axi.Wishbone2AXILite(ethmac.bus, axil_bus) + self.comb += axil_bus.connect_to_pads( + self.platform.request("bus"), mode="slave" + ) + self.bus.add_master(master=axil_bus) + + ethmac_region_size = (nrxslots + ntxslots) * buffer_depth + ethmac_region = SoCRegion( + origin=self.mem_map.get("ethmac", None), + size=ethmac_region_size, + cached=False, + ) + self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) + + # Interrupt Interface ---------------------------------------------------------------------- + self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq) + + # UDP Core ----------------------------------------------------------------------------------------- + + class UDPCore(PHYCore): def add_streamer_port(self, platform, name, port_cfg): # Use default Data-Width of 8-bit when not specified. @@ -571,6 +645,8 @@ class UDPCore(PHYCore): # Build -------------------------------------------------------------------------------------------- + + def main(core_config): # Convert YAML elements to Python/LiteX -------------------------------------------------------- for k, v in core_config.items(): @@ -598,7 +674,12 @@ def main(core_config): raise ValueError("Unsupported vendor: {}".format(core_config["vendor"])) platform.add_extension(_io) - soc = UDPCore(platform, core_config) + if core_config["core"] in ["wishbone", "axi-lite"]: + soc = MACCore(platform, core_config) + elif core_config["core"] == "udp": + soc = UDPCore(platform, core_config) + else: + raise ValueError("Unknown core: {}".format(core_config["core"])) with TemporaryDirectory() as path: builder = Builder(soc, compile_gateware=False, output_dir=path) From 75a0fe46ff3eea12ed296a276f823590db067fab Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 10 Feb 2024 01:13:11 -0800 Subject: [PATCH 44/89] fix PLL information in Ethernet docs --- doc/architecture.md | 4 +--- doc/ethernet_interface.md | 12 +++++++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/doc/architecture.md b/doc/architecture.md index 588ab59..53ed0db 100644 --- a/doc/architecture.md +++ b/doc/architecture.md @@ -4,9 +4,7 @@ The whole system looks like the following:
    -Manta is operated via its Python API, which communicates with the connected FPGA over an interface API like `pySerial` or `Scapy`. These abstract away the OS device drivers, which function differently depending on the host machine's platform. The OS device drivers ultimately send out bytes to the FPGA, across either a USB or Ethernet cable. - -Once sent across the wire, bytes are picked up by an interface transceiver on the FPGA development board. This is either a USB-UART converter or a RMII PHY depending on if you're using UART or Ethernet. This chip is connected to the FPGA's IO, which routes the signals to the Verilog module generated by Manta. This module parses incoming messages, passes them down a set of daisy-chained cores, and then packetizes it and sends it back to the host. +Manta consists of two parts - a Python API running on a host machine, and an autogenerated block of RTL that's included with your logic on a FPGA. Either UART or Ethernet is used for communication, which allows the host machine to operate the debugging cores on the FPGA. ## Manta Architecture diff --git a/doc/ethernet_interface.md b/doc/ethernet_interface.md index e78ae9b..2d7b77f 100644 --- a/doc/ethernet_interface.md +++ b/doc/ethernet_interface.md @@ -1,7 +1,7 @@ ## Overview For scenarios where UART is not available or higher bandwidth is desired, Manta provides an Ethernet interface for communicating between the host and FPGA. This interface uses UDP for communication, and leverages the builtin Python `sockets` module on the host side, and the open-source [LiteEth](https://github.com/enjoy-digital/liteeth) Ethernet core on the FPGA side. -!!! warning "Not every device is supported!" +!!! info "Not every device is supported!" Although Manta aims to be as platform-agnostic as possible, Ethernet PHYs and FPGA clock primitives are very particular devices. As a result, the supported devices are loosely restricted to those on [this list](https://github.com/enjoy-digital/liteeth?tab=readme-ov-file#-features). If a device you'd like to use isn't on the list, the community would love your help! @@ -30,10 +30,16 @@ This snippet at the end of the configuration file defines the interface. The fol - `toolchain` _(required)_: The toolchain being used. Currently only values of `vivado` and `diamond` are supported. -- `clk_freq` _(required)_: The frequency of the clock provided to the Manta instance. Used to configure a PLL in the FPGA fabric for generating the PHY's `refclk`. +- `clk_freq` _(required)_: The frequency of the clock provided to the Manta instance. -- `refclk_freq` _(required)_: The frequency of the reference clock to be provided to the Ethernet PHY. This clock is generated from Manta's main clock using a PLL inside the FPGA. This frequency must match the MII variant supported by the PHY, as well as speed that the PHY is being operated at. For instance, a RGMII PHY may be operated at either 125MHz in Gigabit mode, or 25MHz in 100Mbps mode. +- `refclk_freq` _(required)_: The frequency of the reference clock to be provided to the Ethernet PHY. This frequency must match the MII variant supported by the PHY, as well as speed that the PHY is being operated at. For instance, a RGMII PHY may be operated at either 125MHz in Gigabit mode, or 25MHz in 100Mbps mode. - `fpga_ip_addr` _(required)_: The IP address the FPGA will attempt to claim. Upon power-on, the FPGA will issue a DHCP request for this IP address. The easiest way to check if this was successful is by pinging the FPGA's IP, but if you have access to your network's router it may report a list of connected devices. - `host_ip_addr` _(required)_: The IP address of the host machine, which the FPGA will send packets back to. + +Lastly, any additonal arguments provided in the `ethernet` section of the config file will be passed to the LiteEth standalone core generator. As a result, the [examples](https://github.com/enjoy-digital/liteeth/tree/master/examples) provided by LiteEth may be of some service to you if you're bringing up a different FPGA! + +!!! warning "LiteEth doesn't always generate its own `refclk`!" + + Although LitEth is built on Migen and LiteX which support PLLs and other clock generation primitives, I haven't seen it instantiate one to synthesize a suitable `refclk` at the appropriate frequency from the input clock. As a result, for now it's recommended to generate your `refclk` outside Manta, and then use it to clock your Manta instance. \ No newline at end of file From a1fddf555e7eae265bc9e2339b2a40fbd2ef224e Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 12 Feb 2024 08:50:43 -0800 Subject: [PATCH 45/89] move init'ing UARTInterface from config to classmethod --- src/manta/manta.py | 2 +- src/manta/uart/__init__.py | 162 +++++++++++++++++++------------------ 2 files changed, 83 insertions(+), 81 deletions(-) diff --git a/src/manta/manta.py b/src/manta/manta.py index 35744a5..50a83e7 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -63,7 +63,7 @@ class Manta(Elaboratable): def get_interface(self): if "uart" in self.config: - return UARTInterface(self.config["uart"]) + return UARTInterface.from_config(self.config["uart"]) elif "ethernet" in self.config: return EthernetInterface(self.config["ethernet"]) diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index a735897..f974209 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -8,26 +8,31 @@ from serial import Serial class UARTInterface(Elaboratable): - def __init__(self, config): - self.config = config - self.check_config(self.config) - - self.port = config["port"] - self.clock_freq = config["clock_freq"] - self.baudrate = config["baudrate"] - self.clocks_per_baud = int(self.clock_freq // self.baudrate) - - self.define_signals() + def __init__(self, port, baudrate, clock_freq, chunk_size=256): + self._port = port + self._baudrate = baudrate + self._clock_freq = clock_freq + self._chunk_size = chunk_size + self._clocks_per_baud = int(self._clock_freq // self._baudrate) + self._check_config() # Set chunk_size, which is the max amount of bytes that the core will # dump to the OS driver at a time. Since the FPGA will return bytes # almost instantaneously, this prevents the OS's input buffer from # overflowing, and dropping bytes. - self.chunk_size = 256 # in bytes - if "chunk_size" in config: - self.chunk_size = config["chunk_size"] - def check_config(self, config): + self.rx = Signal() + self.tx = Signal() + + self.bus_o = Signal(InternalBus()) + self.bus_i = Signal(InternalBus()) + + @classmethod + def from_config(cls, config): + port = config.get("port") + clock_freq = config.get("clock_freq") + baudrate = config.get("baudrate") + # Warn if unrecognized options have been given recognized_options = ["port", "clock_freq", "baudrate", "chunk_size"] for option in config: @@ -36,84 +41,88 @@ class UARTInterface(Elaboratable): f"Ignoring unrecognized option '{option}' in UART interface config." ) + if "chunk_size" in config: + return cls(port, baudrate, clock_freq, config["chunk_size"]) + + else: + return cls(port, baudrate, clock_freq) + + def _check_config(self): # Ensure a serial port has been given - if "port" not in config: + if self._port is None: raise ValueError("No serial port provided to UART interface.") # Ensure clock frequency is provided and positive - if "clock_freq" not in config: + if self._clock_freq is None: raise ValueError("No clock frequency provided to UART interface.") - if config["clock_freq"] <= 0: + if self._clock_freq <= 0: raise ValueError("Non-positive clock frequency provided to UART interface.") # Check that baudrate is provided and positive - if "baudrate" not in config: + if self._baudrate is None: raise ValueError("No baudrate provided to UART interface.") - if config["baudrate"] <= 0: + if self._baudrate <= 0: raise ValueError("Non-positive baudrate provided to UART interface.") # Confirm the actual baudrate is within 5% of the target baudrate - clock_freq = config["clock_freq"] - baudrate = config["baudrate"] - clocks_per_baud = clock_freq // baudrate - actual_baudrate = clock_freq / clocks_per_baud - error = 100 * abs(actual_baudrate - baudrate) / baudrate + actual_baudrate = self._clock_freq / self._clocks_per_baud + error = 100 * abs(actual_baudrate - self._baudrate) / self._baudrate if error > 5: raise ValueError( "UART interface is unable to match targeted baudrate with specified clock frequency." ) - def get_serial_device(self): + def _get_serial_device(self): """ Return an open PySerial serial device if one exists, otherwise, open one. """ - if hasattr(self, "serial_device"): - return self.serial_device + + # Check if we've already opened a device + if hasattr(self, "_serial_device"): + return self._serial_device + + if self._port != "auto": + self._serial_device = Serial(self._port, self._baudrate, timeout=1) + return self._serial_device + + # Try to autodetect which port to use based on the PID/VID of the device attached. + # This looks for the PID/VID of the FT2232, the primary chip used on the icestick + # and Digilent dev boards. However, folks will likely want to connect other things + # in the future, so in the future we'll probably want to look for other chips as + # well. + + # The FT2232 exposes two serial ports - and for whatever reason it usually has the + # 0th device used for JTAG programming, and the 1st used for UART. So we'll grab + # the 1st. + + import serial.tools.list_ports + + ports = [] + for port in serial.tools.list_ports.comports(): + if (port.vid == 0x403) and (port.pid == 0x6010): + ports.append(port) + + if len(ports) != 2: + raise ValueError( + f"Expected to see two serial ports for FT2232 device, but instead see {len(ports)}." + ) + + if ports[0].serial_number != ports[1].serial_number: + raise ValueError( + f"Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices." + ) + + if ports[0].location > ports[1].location: + chosen_port = ports[0].device else: - if self.port != "auto": - self.serial_device = Serial(self.port, self.baudrate, timeout=1) - return self.serial_device + chosen_port = ports[1].device - else: - # Try to autodetect which port to use based on the PID/VID of the device attached. - # This looks for the PID/VID of the FT2232, the primary chip used on the icestick - # and Digilent dev boards. However, folks will likely want to connect other things - # in the future, so in the future we'll probably want to look for other chips as - # well. - - # The FT2232 exposes two serial ports - and for whatever reason it usually has the - # 0th device used for JTAG programming, and the 1st used for UART. So we'll grab - # the 1st. - - import serial.tools.list_ports - - ports = [] - for port in serial.tools.list_ports.comports(): - if (port.vid == 0x403) and (port.pid == 0x6010): - ports.append(port) - - if len(ports) != 2: - raise ValueError( - f"Expected to see two serial ports for FT2232 device, but instead see {len(ports)}." - ) - - if ports[0].serial_number != ports[1].serial_number: - raise ValueError( - f"Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices." - ) - - if ports[0].location > ports[1].location: - chosen_port = ports[0].device - - else: - chosen_port = ports[1].device - - self.serial_device = Serial(chosen_port, self.baudrate, timeout=1) - return self.serial_device + self._serial_device = Serial(chosen_port, self._baudrate, timeout=1) + return self._serial_device def get_top_level_ports(self): return [self.rx, self.tx] @@ -133,8 +142,8 @@ class UARTInterface(Elaboratable): raise ValueError("Read address must be an integer or list of integers.") # Send read requests, and get responses - ser = self.get_serial_device() - addr_chunks = split_into_chunks(addrs, self.chunk_size) + ser = self._get_serial_device() + addr_chunks = split_into_chunks(addrs, self._chunk_size) datas = [] for addr_chunk in addr_chunks: @@ -152,7 +161,7 @@ class UARTInterface(Elaboratable): # Split received bytes into individual responses and decode responses = split_into_chunks(bytes_in, 7) - data_chunk = [self.decode_read_response(r) for r in responses] + data_chunk = [self._decode_read_response(r) for r in responses] datas += data_chunk return datas @@ -186,10 +195,10 @@ class UARTInterface(Elaboratable): # Encode addrs and datas into write requests bytes_out = "".join([f"W{a:04X}{d:04X}\r\n" for a, d in zip(addrs, datas)]) bytes_out = bytes_out.encode("ascii") - ser = self.get_serial_device() + ser = self._get_serial_device() ser.write(bytes_out) - def decode_read_response(self, response_bytes): + def _decode_read_response(self, response_bytes): """ Check that read response is formatted properly, and extract the encoded data if so. """ @@ -221,21 +230,14 @@ class UARTInterface(Elaboratable): return int(response_ascii[1:5], 16) - def define_signals(self): - self.rx = Signal() - self.tx = Signal() - - self.bus_o = Signal(InternalBus()) - self.bus_i = Signal(InternalBus()) - def elaborate(self, platform): # fancy submoduling and such goes in here m = Module() - m.submodules.uart_rx = uart_rx = UARTReceiver(self.clocks_per_baud) + m.submodules.uart_rx = uart_rx = UARTReceiver(self._clocks_per_baud) m.submodules.bridge_rx = bridge_rx = ReceiveBridge() m.submodules.bridge_tx = bridge_tx = TransmitBridge() - m.submodules.uart_tx = uart_tx = UARTTransmitter(self.clocks_per_baud) + m.submodules.uart_tx = uart_tx = UARTTransmitter(self._clocks_per_baud) m.d.comb += [ # UART RX -> Internal Bus From 1487cfe9a26181aeb097065324bd93116bf4e2f7 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 17 Feb 2024 13:31:27 -0800 Subject: [PATCH 46/89] banish relative imports --- src/manta/__init__.py | 4 +-- src/manta/__main__.py | 2 +- src/manta/cli.py | 4 +-- src/manta/ethernet/__init__.py | 13 +++++----- src/manta/io_core.py | 2 +- src/manta/logic_analyzer/__init__.py | 10 ++++---- src/manta/logic_analyzer/fsm.py | 2 +- src/manta/logic_analyzer/sample_mem.py | 2 +- src/manta/logic_analyzer/trigger_block.py | 2 +- src/manta/manta.py | 10 ++++---- src/manta/memory_core.py | 2 +- src/manta/uart/__init__.py | 31 ++++++++++++----------- 12 files changed, 42 insertions(+), 42 deletions(-) diff --git a/src/manta/__init__.py b/src/manta/__init__.py index 60b9f60..f95e36e 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -1,5 +1,5 @@ -from .manta import Manta -from .cli import main +from manta.manta import Manta +from manta.cli import main if __name__ == "__main__": main() diff --git a/src/manta/__main__.py b/src/manta/__main__.py index 4e28416..2c4044f 100644 --- a/src/manta/__main__.py +++ b/src/manta/__main__.py @@ -1,3 +1,3 @@ -from .cli import main +from manta.cli import main main() diff --git a/src/manta/cli.py b/src/manta/cli.py index 0d64bd5..c65a167 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -1,5 +1,5 @@ -from .manta import Manta -from .utils import * +from manta.manta import Manta +from manta.utils import * from sys import argv from pkg_resources import get_distribution diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index 20ebf3c..f8f44fa 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -1,7 +1,7 @@ from amaranth import * -from ..utils import * -from .source_bridge import UDPSourceBridge -from .sink_bridge import UDPSinkBridge +from manta.utils import * +from manta.ethernet.source_bridge import UDPSourceBridge +from manta.ethernet.sink_bridge import UDPSinkBridge from random import randint import socket @@ -195,10 +195,9 @@ class EthernetInterface(Elaboratable): """ Generate a LiteEth core by calling a slightly modified form of the LiteEth standalone core generator. This passes the contents of the 'ethernet' section - of the Manta configuration file to LiteEth, after modifying it slightly to - include the UDP ports and set a MAC address if the user didn't specify one. + of the Manta configuration file to LiteEth, after modifying it slightly. """ - liteeth_config = self.config.copy() + liteeth_config = self._config.copy() # Randomly assign a MAC address if one is not specified in the configuration. # This will choose a MAC address in the Locally Administered, Administratively Assigned group. @@ -231,6 +230,6 @@ class EthernetInterface(Elaboratable): } # Generate the core - from .liteeth_gen import main + from manta.ethernet.liteeth_gen import main return main(liteeth_config) diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 40009df..39c0634 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -1,5 +1,5 @@ from amaranth import * -from .utils import * +from manta.utils import * from math import ceil diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 470843d..fddcfa6 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -1,9 +1,9 @@ from amaranth import * -from ..utils import * -from .trigger_block import LogicAnalyzerTriggerBlock -from .fsm import LogicAnalyzerFSM, States, TriggerModes -from .sample_mem import LogicAnalyzerSampleMemory -from .playback import LogicAnalyzerPlayback +from manta.utils import * +from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock +from manta.logic_analyzer.fsm import LogicAnalyzerFSM, States, TriggerModes +from manta.logic_analyzer.sample_mem import LogicAnalyzerSampleMemory +from manta.logic_analyzer.playback import LogicAnalyzerPlayback class LogicAnalyzerCore(Elaboratable): diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 9efe17a..2c8215d 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -1,7 +1,7 @@ from amaranth import * from amaranth.lib.enum import IntEnum from math import ceil, log2 -from ..io_core import IOCore +from manta.io_core import IOCore class States(IntEnum): diff --git a/src/manta/logic_analyzer/sample_mem.py b/src/manta/logic_analyzer/sample_mem.py index b6806fd..fc8f218 100644 --- a/src/manta/logic_analyzer/sample_mem.py +++ b/src/manta/logic_analyzer/sample_mem.py @@ -1,5 +1,5 @@ from amaranth import * -from ..memory_core import ReadOnlyMemoryCore +from manta.memory_core import ReadOnlyMemoryCore class LogicAnalyzerSampleMemory(ReadOnlyMemoryCore): diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 7dca023..3cfbba5 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -1,5 +1,5 @@ from amaranth import * -from ..io_core import IOCore +from manta.io_core import IOCore class LogicAnalyzerTriggerBlock(Elaboratable): diff --git a/src/manta/manta.py b/src/manta/manta.py index 50a83e7..313af71 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -1,10 +1,10 @@ from amaranth import * -from .uart import UARTInterface +from manta.uart import UARTInterface -from .ethernet import EthernetInterface -from .io_core import IOCore -from .memory_core import ReadOnlyMemoryCore -from .logic_analyzer import LogicAnalyzerCore +from manta.ethernet import EthernetInterface +from manta.io_core import IOCore +from manta.memory_core import ReadOnlyMemoryCore +from manta.logic_analyzer import LogicAnalyzerCore class Manta(Elaboratable): diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 17bfd33..50c78f8 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -1,5 +1,5 @@ from amaranth import * -from .utils import * +from manta.utils import * from math import ceil diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index f974209..9a57482 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -1,9 +1,9 @@ from amaranth import * -from ..utils import * -from .receiver import UARTReceiver -from .receive_bridge import ReceiveBridge -from .transmitter import UARTTransmitter -from .transmit_bridge import TransmitBridge +from manta.utils import * +from manta.uart.receiver import UARTReceiver +from manta.uart.receive_bridge import ReceiveBridge +from manta.uart.transmitter import UARTTransmitter +from manta.uart.transmit_bridge import TransmitBridge from serial import Serial @@ -16,11 +16,7 @@ class UARTInterface(Elaboratable): self._clocks_per_baud = int(self._clock_freq // self._baudrate) self._check_config() - # Set chunk_size, which is the max amount of bytes that the core will - # dump to the OS driver at a time. Since the FPGA will return bytes - # almost instantaneously, this prevents the OS's input buffer from - # overflowing, and dropping bytes. - + # Top-Level Ports self.rx = Signal() self.tx = Signal() @@ -139,9 +135,14 @@ class UARTInterface(Elaboratable): # Make sure all list elements are integers if not all(isinstance(a, int) for a in addrs): - raise ValueError("Read address must be an integer or list of integers.") + raise TypeError("Read address must be an integer or list of integers.") + + # Send read requests in chunks, and read bytes after each. + # The input buffer exposed by the OS on most hosts isn't terribly deep, + # so sending in chunks (instead of all at once) prevents the OS's input + # buffer from overflowing and dropping bytes, as the FPGA will send + # responses instantly after it's received a request. - # Send read requests, and get responses ser = self._get_serial_device() addr_chunks = split_into_chunks(addrs, self._chunk_size) datas = [] @@ -178,15 +179,15 @@ class UARTInterface(Elaboratable): # Make sure address and datas are all integers if not isinstance(addrs, list) or not isinstance(datas, list): - raise ValueError( + raise TypeError( "Write addresses and data must be an integer or list of integers." ) if not all(isinstance(a, int) for a in addrs): - raise ValueError("Write addresses must be all be integers.") + raise TypeError("Write addresses must be all be integers.") if not all(isinstance(d, int) for d in datas): - raise ValueError("Write data must all be integers.") + raise TypeError("Write data must all be integers.") # Since the FPGA doesn't issue any responses to write requests, we # the host's input buffer isn't written to, and we don't need to From 8aedb8e9688f791d9742b55dbb707707e24489b0 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 17 Feb 2024 14:09:29 -0800 Subject: [PATCH 47/89] add config check to ethernet interface --- src/manta/ethernet/__init__.py | 122 ++++++++++++++++++---------- src/manta/ethernet/sink_bridge.py | 5 ++ src/manta/ethernet/source_bridge.py | 5 ++ 3 files changed, 90 insertions(+), 42 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index f8f44fa..f68885b 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -7,11 +7,18 @@ import socket class EthernetInterface(Elaboratable): + """A module for communicating with Manta over Ethernet, using UDP. + + Provides methods for generating synthesizable logic for the FPGA, + as well as methods for reading and writing to memory by the host. + """ + def __init__(self, config): - self.config = config - self.fpga_ip_addr = config["fpga_ip_addr"] - self.host_ip_addr = config["host_ip_addr"] - self.udp_port = config["udp_port"] + self._config = config + self._fpga_ip_addr = config.get("fpga_ip_addr") + self._host_ip_addr = config.get("host_ip_addr") + self._udp_port = config.get("udp_port") + self._check_config() self.bus_i = Signal(InternalBus()) self.bus_o = Signal(InternalBus()) @@ -25,18 +32,49 @@ class EthernetInterface(Elaboratable): self.rmii_tx_data = Signal(2) self.rmii_tx_en = Signal() - self.dhcp_start = Signal() - self.dhcp_timer = Signal(range(int(100e6))) + self._dhcp_start = Signal() + self._dhcp_timer = Signal(range(int(100e6))) - self.source_data = Signal(32) - self.source_last = Signal() - self.source_ready = Signal() - self.source_valid = Signal() + self._source_data = Signal(32) + self._source_last = Signal() + self._source_ready = Signal() + self._source_valid = Signal() + + self._sink_data = Signal(32) + self._sink_last = Signal() + self._sink_ready = Signal() + self._sink_valid = Signal() + + def _check_config(self): + # Make sure UDP port is an integer in the range 0-65535 + if not isinstance(self._udp_port, int): + raise TypeError("UDP Port must be specified as an integer between 0 and 65535.") + + if not 0 <= self._udp_port <= 65535: + raise ValueError("UDP Port must be between 0 and 65535.") + + # Make sure Host IP address is four bytes separated by a period + if not isinstance(self._host_ip_addr, str): + raise TypeError("Host IP must be specified as a string in the form 'xxx.xxx.xxx.xxx'.") + + if len(self._host_ip_addr.split(".")) != 4: + raise ValueError("Host IP must be specified in the form 'xxx.xxx.xxx.xxx'.") + + for byte in self._host_ip_addr.split("."): + if not 0 <= int(byte) <= 255: + raise ValueError(f"Invalid byte in Host IP: {byte}") + + # Make sure FPGA IP is four bytes separated by a period + if not isinstance(self._fpga_ip_addr, str): + raise TypeError("FPGA IP must be specified as a string in the form 'xxx.xxx.xxx.xxx'.") + + if len(self._fpga_ip_addr.split(".")) != 4: + raise ValueError("FPGA IP must be specified in the form 'xxx.xxx.xxx.xxx'.") + + for byte in self._fpga_ip_addr.split("."): + if not 0 <= int(byte) <= 255: + raise ValueError(f"Invalid byte in FPGA IP: {byte}") - self.sink_data = Signal(32) - self.sink_last = Signal() - self.sink_ready = Signal() - self.sink_valid = Signal() def get_top_level_ports(self): ports = [ @@ -51,17 +89,17 @@ class EthernetInterface(Elaboratable): ] return ports - def binarize_ip_addr(self, ip_addr): + def _binarize_ip_addr(self, ip_addr): octets = [bin(int(o))[2:].zfill(8) for o in ip_addr.split(".")] return int("".join(octets), 2) def elaborate(self, platform): m = Module() - with m.If(self.dhcp_timer < int(50e6)): - m.d.sync += self.dhcp_timer.eq(self.dhcp_timer + 1) + with m.If(self._dhcp_timer < int(50e6)): + m.d.sync += self._dhcp_timer.eq(self._dhcp_timer + 1) - m.d.sync += self.dhcp_start.eq(self.dhcp_timer == (int(50e6) - 2)) + m.d.sync += self._dhcp_start.eq(self._dhcp_timer == (int(50e6) - 2)) m.submodules.liteeth = Instance( "liteeth_core", @@ -79,37 +117,37 @@ class EthernetInterface(Elaboratable): # DHCP # ("o", "dhcp_done", 1), # ("o", "dhcp_ip_address", 1), - ("i", "dhcp_start", self.dhcp_start), + ("i", "dhcp_start", self._dhcp_start), # ("o", "dhcp_timeout", 1), - ("i", "ip_address", self.binarize_ip_addr(self.fpga_ip_addr)), + ("i", "ip_address", self._binarize_ip_addr(self._fpga_ip_addr)), # UDP Port - ("i", "udp0_udp_port", self.udp_port), + ("i", "udp0_udp_port", self._udp_port), # UDP from host - ("o", "udp0_source_data", self.source_data), + ("o", "udp0_source_data", self._source_data), # ("o", "udp0_source_error", 1), - ("o", "udp0_source_last", self.source_last), - ("i", "udp0_source_ready", self.source_ready), - ("o", "udp0_source_valid", self.source_valid), + ("o", "udp0_source_last", self._source_last), + ("i", "udp0_source_ready", self._source_ready), + ("o", "udp0_source_valid", self._source_valid), # UDP back to host - ("i", "udp0_ip_address", self.binarize_ip_addr(self.host_ip_addr)), - ("i", "udp0_sink_data", self.sink_data), - ("i", "udp0_sink_last", self.sink_last), - ("o", "udp0_sink_ready", self.sink_ready), - ("i", "udp0_sink_valid", self.sink_valid), + ("i", "udp0_ip_address", self._binarize_ip_addr(self._host_ip_addr)), + ("i", "udp0_sink_data", self._sink_data), + ("i", "udp0_sink_last", self._sink_last), + ("o", "udp0_sink_ready", self._sink_ready), + ("i", "udp0_sink_valid", self._sink_valid), ) m.submodules.source_bridge = source_bridge = UDPSourceBridge() m.submodules.sink_bridge = sink_bridge = UDPSinkBridge() - m.d.comb += source_bridge.data_i.eq(self.source_data) - m.d.comb += source_bridge.last_i.eq(self.source_last) - m.d.comb += self.source_ready.eq(source_bridge.ready_o) - m.d.comb += source_bridge.valid_i.eq(self.source_valid) + m.d.comb += source_bridge.data_i.eq(self._source_data) + m.d.comb += source_bridge.last_i.eq(self._source_last) + m.d.comb += self._source_ready.eq(source_bridge.ready_o) + m.d.comb += source_bridge.valid_i.eq(self._source_valid) - m.d.comb += self.sink_data.eq(sink_bridge.data_o) - m.d.comb += self.sink_last.eq(sink_bridge.last_o) - m.d.comb += sink_bridge.ready_i.eq(self.sink_ready) - m.d.comb += self.sink_valid.eq(sink_bridge.valid_o) + m.d.comb += self._sink_data.eq(sink_bridge.data_o) + m.d.comb += self._sink_last.eq(sink_bridge.last_o) + m.d.comb += sink_bridge.ready_i.eq(self._sink_ready) + m.d.comb += self._sink_valid.eq(sink_bridge.valid_o) m.d.comb += sink_bridge.bus_i.eq(self.bus_i) m.d.comb += self.bus_o.eq(source_bridge.bus_o) @@ -132,7 +170,7 @@ class EthernetInterface(Elaboratable): # Send read requests, and get responses sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - sock.bind((self.host_ip_addr, self.udp_port)) + sock.bind((self._host_ip_addr, self._udp_port)) chunk_size = 64 # 128 addr_chunks = split_into_chunks(addrs, chunk_size) datas = [] @@ -144,7 +182,7 @@ class EthernetInterface(Elaboratable): bytes_out += int(addr).to_bytes(2, byteorder="little") bytes_out += int(0).to_bytes(2, byteorder="little") - sock.sendto(bytes_out, (self.fpga_ip_addr, self.udp_port)) + sock.sendto(bytes_out, (self._fpga_ip_addr, self._udp_port)) data, addr = sock.recvfrom(4 * chunk_size) # Split into groups of four bytes @@ -189,7 +227,7 @@ class EthernetInterface(Elaboratable): bytes_out += int(data).to_bytes(2, byteorder="little") sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - sock.sendto(bytes_out, (self.fpga_ip_addr, self.udp_port)) + sock.sendto(bytes_out, (self._fpga_ip_addr, self._udp_port)) def generate_liteeth_core(self): """ @@ -222,7 +260,7 @@ class EthernetInterface(Elaboratable): # Add UDP port liteeth_config["udp_ports"] = { "udp0": { - "udp_port": self.udp_port, + "udp_port": self._udp_port, "data_width": 32, "tx_fifo_depth": 64, "rx_fifo_depth": 64, diff --git a/src/manta/ethernet/sink_bridge.py b/src/manta/ethernet/sink_bridge.py index c10a290..09dda83 100644 --- a/src/manta/ethernet/sink_bridge.py +++ b/src/manta/ethernet/sink_bridge.py @@ -3,6 +3,11 @@ from manta.utils import * class UDPSinkBridge(Elaboratable): + """A module for bridging Manta's internal bus to an AXI stream of UDP + packet data. + + Connects to the LiteEth core's "sink" port. + """ def __init__(self): self.bus_i = Signal(InternalBus()) diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py index e87967b..9cbcdd2 100644 --- a/src/manta/ethernet/source_bridge.py +++ b/src/manta/ethernet/source_bridge.py @@ -3,6 +3,11 @@ from manta.utils import * class UDPSourceBridge(Elaboratable): + """A module for bridging the AXI-stream of incoming UDP packet data to + Manta's internal bus. + + Connects to the LiteEth core's "source" port. + """ def __init__(self): self.bus_o = Signal(InternalBus()) From 68aeb1a4a8ae3177f22694ceb1ce79740e82e808 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 17 Feb 2024 15:04:50 -0800 Subject: [PATCH 48/89] add underscores for private objects --- src/manta/ethernet/__init__.py | 30 +++++--- src/manta/ethernet/sink_bridge.py | 4 +- src/manta/ethernet/source_bridge.py | 4 +- src/manta/uart/__init__.py | 16 +++- src/manta/uart/receive_bridge.py | 115 +++++++++++++++------------- src/manta/uart/receiver.py | 61 ++++++++------- src/manta/uart/transmit_bridge.py | 79 ++++++++++--------- src/manta/uart/transmitter.py | 39 ++++++---- 8 files changed, 200 insertions(+), 148 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index f68885b..2fd1104 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -7,7 +7,8 @@ import socket class EthernetInterface(Elaboratable): - """A module for communicating with Manta over Ethernet, using UDP. + """ + A module for communicating with Manta over Ethernet, using UDP. Provides methods for generating synthesizable logic for the FPGA, as well as methods for reading and writing to memory by the host. @@ -48,14 +49,18 @@ class EthernetInterface(Elaboratable): def _check_config(self): # Make sure UDP port is an integer in the range 0-65535 if not isinstance(self._udp_port, int): - raise TypeError("UDP Port must be specified as an integer between 0 and 65535.") + raise TypeError( + "UDP Port must be specified as an integer between 0 and 65535." + ) if not 0 <= self._udp_port <= 65535: raise ValueError("UDP Port must be between 0 and 65535.") # Make sure Host IP address is four bytes separated by a period if not isinstance(self._host_ip_addr, str): - raise TypeError("Host IP must be specified as a string in the form 'xxx.xxx.xxx.xxx'.") + raise TypeError( + "Host IP must be specified as a string in the form 'xxx.xxx.xxx.xxx'." + ) if len(self._host_ip_addr.split(".")) != 4: raise ValueError("Host IP must be specified in the form 'xxx.xxx.xxx.xxx'.") @@ -66,7 +71,9 @@ class EthernetInterface(Elaboratable): # Make sure FPGA IP is four bytes separated by a period if not isinstance(self._fpga_ip_addr, str): - raise TypeError("FPGA IP must be specified as a string in the form 'xxx.xxx.xxx.xxx'.") + raise TypeError( + "FPGA IP must be specified as a string in the form 'xxx.xxx.xxx.xxx'." + ) if len(self._fpga_ip_addr.split(".")) != 4: raise ValueError("FPGA IP must be specified in the form 'xxx.xxx.xxx.xxx'.") @@ -75,8 +82,11 @@ class EthernetInterface(Elaboratable): if not 0 <= int(byte) <= 255: raise ValueError(f"Invalid byte in FPGA IP: {byte}") - def get_top_level_ports(self): + """ + Return the Amaranth signals that should be included as ports in the top-level + Manta module. + """ ports = [ self.rmii_clocks_ref_clk, self.rmii_crs_dv, @@ -125,7 +135,7 @@ class EthernetInterface(Elaboratable): # UDP from host ("o", "udp0_source_data", self._source_data), # ("o", "udp0_source_error", 1), - ("o", "udp0_source_last", self._source_last), + ("o", "udp0_source_last", self._source_last), ("i", "udp0_source_ready", self._source_ready), ("o", "udp0_source_valid", self._source_valid), # UDP back to host @@ -166,7 +176,7 @@ class EthernetInterface(Elaboratable): # Make sure all list elements are integers if not all(isinstance(a, int) for a in addrs): - raise ValueError("Read address must be an integer or list of integers.") + raise TypeError("Read address must be an integer or list of integers.") # Send read requests, and get responses sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) @@ -205,15 +215,15 @@ class EthernetInterface(Elaboratable): # Make sure address and datas are all integers if not isinstance(addrs, list) or not isinstance(datas, list): - raise ValueError( + raise TypeError( "Write addresses and data must be an integer or list of integers." ) if not all(isinstance(a, int) for a in addrs): - raise ValueError("Write addresses must be all be integers.") + raise TypeError("Write addresses must be all be integers.") if not all(isinstance(d, int) for d in datas): - raise ValueError("Write data must all be integers.") + raise TypeError("Write data must all be integers.") # Since the FPGA doesn't issue any responses to write requests, we # the host's input buffer isn't written to, and we don't need to diff --git a/src/manta/ethernet/sink_bridge.py b/src/manta/ethernet/sink_bridge.py index 09dda83..ecff0d0 100644 --- a/src/manta/ethernet/sink_bridge.py +++ b/src/manta/ethernet/sink_bridge.py @@ -3,11 +3,13 @@ from manta.utils import * class UDPSinkBridge(Elaboratable): - """A module for bridging Manta's internal bus to an AXI stream of UDP + """ + A module for bridging Manta's internal bus to an AXI stream of UDP packet data. Connects to the LiteEth core's "sink" port. """ + def __init__(self): self.bus_i = Signal(InternalBus()) diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py index 9cbcdd2..9506636 100644 --- a/src/manta/ethernet/source_bridge.py +++ b/src/manta/ethernet/source_bridge.py @@ -3,11 +3,13 @@ from manta.utils import * class UDPSourceBridge(Elaboratable): - """A module for bridging the AXI-stream of incoming UDP packet data to + """ + A module for bridging the AXI-stream of incoming UDP packet data to Manta's internal bus. Connects to the LiteEth core's "source" port. """ + def __init__(self): self.bus_o = Signal(InternalBus()) diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index 9a57482..60bab24 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -8,6 +8,13 @@ from serial import Serial class UARTInterface(Elaboratable): + """ + A module for communicating with Manta over UART. + + Provides methods for generating synthesizable logic for the FPGA, + as well as methods for reading and writing to memory by the host. + """ + def __init__(self, port, baudrate, clock_freq, chunk_size=256): self._port = port self._baudrate = baudrate @@ -73,7 +80,7 @@ class UARTInterface(Elaboratable): def _get_serial_device(self): """ - Return an open PySerial serial device if one exists, otherwise, open one. + Return an open PySerial serial device if one exists, otherwise, open one and return it. """ # Check if we've already opened a device @@ -121,6 +128,10 @@ class UARTInterface(Elaboratable): return self._serial_device def get_top_level_ports(self): + """ + Return the Amaranth signals that should be included as ports in the top-level + Manta module. + """ return [self.rx, self.tx] def read(self, addrs): @@ -201,7 +212,7 @@ class UARTInterface(Elaboratable): def _decode_read_response(self, response_bytes): """ - Check that read response is formatted properly, and extract the encoded data if so. + Check that read response is formatted properly, and return the encoded data if so. """ # Make sure response is not empty @@ -232,7 +243,6 @@ class UARTInterface(Elaboratable): return int(response_ascii[1:5], 16) def elaborate(self, platform): - # fancy submoduling and such goes in here m = Module() m.submodules.uart_rx = uart_rx = UARTReceiver(self._clocks_per_baud) diff --git a/src/manta/uart/receive_bridge.py b/src/manta/uart/receive_bridge.py index 4abbc7b..07179b1 100644 --- a/src/manta/uart/receive_bridge.py +++ b/src/manta/uart/receive_bridge.py @@ -1,71 +1,78 @@ from amaranth import * +from amaranth.lib.enum import IntEnum from amaranth.lib.data import ArrayLayout +class States(IntEnum): + IDLE = 0 + READ = 1 + WRITE = 2 + + class ReceiveBridge(Elaboratable): + """ + A module for bridging the stream of bytes from the UARTReceiver + module to Manta's internal bus. + """ + def __init__(self): # Top-Level Ports self.data_i = Signal(8) self.valid_i = Signal() - self.addr_o = Signal(16, reset=0) - self.data_o = Signal(16, reset=0) - self.rw_o = Signal(1, reset=0) - self.valid_o = Signal(1, reset=0) - - # State Machine - self.IDLE_STATE = 0 - self.READ_STATE = 1 - self.WRITE_STATE = 2 + self.addr_o = Signal(16) + self.data_o = Signal(16) + self.rw_o = Signal(1) + self.valid_o = Signal(1) # Internal Signals - self.buffer = Signal(ArrayLayout(4, 8), reset_less=True) - self.state = Signal(2, reset=self.IDLE_STATE) - self.byte_num = Signal(4, reset=0) - self.is_eol = Signal() - self.is_ascii_hex = Signal() - self.from_ascii_hex = Signal(8) + self._buffer = Signal(ArrayLayout(4, 8)) + self._state = Signal(States) + self._byte_num = Signal(4) + self._is_eol = Signal() + self._is_ascii_hex = Signal() + self._from_ascii_hex = Signal(8) - def drive_ascii_signals(self, m): + def _drive_ascii_signals(self, m): # Decode 0-9 with m.If((self.data_i >= 0x30) & (self.data_i <= 0x39)): - m.d.comb += self.is_ascii_hex.eq(1) - m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x30) + m.d.comb += self._is_ascii_hex.eq(1) + m.d.comb += self._from_ascii_hex.eq(self.data_i - 0x30) # Decode A-F with m.Elif((self.data_i >= 0x41) & (self.data_i <= 0x46)): - m.d.comb += self.is_ascii_hex.eq(1) - m.d.comb += self.from_ascii_hex.eq(self.data_i - 0x41 + 10) + m.d.comb += self._is_ascii_hex.eq(1) + m.d.comb += self._from_ascii_hex.eq(self.data_i - 0x41 + 10) with m.Else(): - m.d.comb += self.is_ascii_hex.eq(0) - m.d.comb += self.from_ascii_hex.eq(0) + m.d.comb += self._is_ascii_hex.eq(0) + m.d.comb += self._from_ascii_hex.eq(0) with m.If((self.data_i == ord("\r")) | (self.data_i == ord("\n"))): - m.d.comb += self.is_eol.eq(1) + m.d.comb += self._is_eol.eq(1) with m.Else(): - m.d.comb += self.is_eol.eq(0) + m.d.comb += self._is_eol.eq(0) - def drive_output_bus(self, m): + def _drive_output_bus(self, m): with m.If( - (self.state == self.READ_STATE) & (self.byte_num == 4) & (self.is_eol) + (self._state == States.READ) & (self._byte_num == 4) & (self._is_eol) ): m.d.comb += self.addr_o.eq( - Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) + Cat(self._buffer[3], self._buffer[2], self._buffer[1], self._buffer[0]) ) m.d.comb += self.data_o.eq(0) m.d.comb += self.valid_o.eq(1) m.d.comb += self.rw_o.eq(0) with m.Elif( - (self.state == self.WRITE_STATE) & (self.byte_num == 8) & (self.is_eol) + (self._state == States.WRITE) & (self._byte_num == 8) & (self._is_eol) ): m.d.comb += self.addr_o.eq( - Cat(self.buffer[3], self.buffer[2], self.buffer[1], self.buffer[0]) + Cat(self._buffer[3], self._buffer[2], self._buffer[1], self._buffer[0]) ) m.d.comb += self.data_o.eq( - Cat(self.buffer[7], self.buffer[6], self.buffer[5], self.buffer[4]) + Cat(self._buffer[7], self._buffer[6], self._buffer[5], self._buffer[4]) ) m.d.comb += self.valid_o.eq(1) m.d.comb += self.rw_o.eq(1) @@ -76,53 +83,57 @@ class ReceiveBridge(Elaboratable): m.d.comb += self.rw_o.eq(0) m.d.comb += self.valid_o.eq(0) - def drive_fsm(self, m): + def _drive_fsm(self, m): with m.If(self.valid_i): - with m.If(self.state == self.IDLE_STATE): - m.d.sync += self.byte_num.eq(0) + with m.If(self._state == States.IDLE): + m.d.sync += self._byte_num.eq(0) with m.If(self.data_i == ord("R")): - m.d.sync += self.state.eq(self.READ_STATE) + m.d.sync += self._state.eq(States.READ) with m.Elif(self.data_i == ord("W")): - m.d.sync += self.state.eq(self.WRITE_STATE) + m.d.sync += self._state.eq(States.WRITE) - with m.If(self.state == self.READ_STATE): + with m.If(self._state == States.READ): # buffer bytes if we don't have enough - with m.If(self.byte_num < 4): + with m.If(self._byte_num < 4): # if bytes aren't valid ASCII then return to IDLE state - with m.If(self.is_ascii_hex == 0): - m.d.sync += self.state.eq(self.IDLE_STATE) + with m.If(self._is_ascii_hex == 0): + m.d.sync += self._state.eq(States.IDLE) # otherwise buffer them with m.Else(): - m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) - m.d.sync += self.byte_num.eq(self.byte_num + 1) + m.d.sync += self._buffer[self._byte_num].eq( + self._from_ascii_hex + ) + m.d.sync += self._byte_num.eq(self._byte_num + 1) with m.Else(): - m.d.sync += self.state.eq(self.IDLE_STATE) + m.d.sync += self._state.eq(States.IDLE) - with m.If(self.state == self.WRITE_STATE): + with m.If(self._state == States.WRITE): # buffer bytes if we don't have enough - with m.If(self.byte_num < 8): + with m.If(self._byte_num < 8): # if bytes aren't valid ASCII then return to IDLE state - with m.If(self.is_ascii_hex == 0): - m.d.sync += self.state.eq(self.IDLE_STATE) + with m.If(self._is_ascii_hex == 0): + m.d.sync += self._state.eq(States.IDLE) # otherwise buffer them with m.Else(): - m.d.sync += self.buffer[self.byte_num].eq(self.from_ascii_hex) - m.d.sync += self.byte_num.eq(self.byte_num + 1) + m.d.sync += self._buffer[self._byte_num].eq( + self._from_ascii_hex + ) + m.d.sync += self._byte_num.eq(self._byte_num + 1) with m.Else(): - m.d.sync += self.state.eq(self.IDLE_STATE) + m.d.sync += self._state.eq(States.IDLE) pass def elaborate(self, platform): m = Module() - self.drive_ascii_signals(m) - self.drive_output_bus(m) - self.drive_fsm(m) + self._drive_ascii_signals(m) + self._drive_output_bus(m) + self._drive_fsm(m) return m diff --git a/src/manta/uart/receiver.py b/src/manta/uart/receiver.py index 70650cf..d42c8ea 100644 --- a/src/manta/uart/receiver.py +++ b/src/manta/uart/receiver.py @@ -2,58 +2,63 @@ from amaranth import * class UARTReceiver(Elaboratable): + """ + A module for receiving bytes on a 8N1 UART at a configurable + baudrate. Outputs bytes as a stream. + """ + def __init__(self, clocks_per_baud): - self.clocks_per_baud = clocks_per_baud + self._clocks_per_baud = clocks_per_baud # Top-Level Ports self.rx = Signal() - self.data_o = Signal(8, reset=0) - self.valid_o = Signal(1, reset=0) + self.data_o = Signal(8) + self.valid_o = Signal(1) # Internal Signals - self.busy = Signal() - self.bit_index = Signal(range(10)) - self.baud_counter = Signal(range(2 * clocks_per_baud)) + self._busy = Signal() + self._bit_index = Signal(range(10)) + self._baud_counter = Signal(range(2 * clocks_per_baud)) - self.rx_d = Signal() - self.rx_q = Signal() - self.rx_q_prev = Signal() + self._rx_d = Signal() + self._rx_q = Signal() + self._rx_q_prev = Signal() def elaborate(self, platform): m = Module() # Two Flip-Flop Synchronizer m.d.sync += [ - self.rx_d.eq(self.rx), - self.rx_q.eq(self.rx_d), - self.rx_q_prev.eq(self.rx_q), + self._rx_d.eq(self.rx), + self._rx_q.eq(self._rx_d), + self._rx_q_prev.eq(self._rx_q), ] m.d.sync += self.valid_o.eq(0) - with m.If(~self.busy): - with m.If((~self.rx_q) & (self.rx_q_prev)): - m.d.sync += self.busy.eq(1) - m.d.sync += self.bit_index.eq(8) - m.d.sync += self.baud_counter.eq( - self.clocks_per_baud + (self.clocks_per_baud // 2) - 2 + with m.If(~self._busy): + with m.If((~self._rx_q) & (self._rx_q_prev)): + m.d.sync += self._busy.eq(1) + m.d.sync += self._bit_index.eq(8) + m.d.sync += self._baud_counter.eq( + self._clocks_per_baud + (self._clocks_per_baud // 2) - 2 ) with m.Else(): - with m.If(self.baud_counter == 0): - with m.If(self.bit_index == 0): + with m.If(self._baud_counter == 0): + with m.If(self._bit_index == 0): m.d.sync += self.valid_o.eq(1) - m.d.sync += self.busy.eq(0) - m.d.sync += self.bit_index.eq(0) - m.d.sync += self.baud_counter.eq(0) + m.d.sync += self._busy.eq(0) + m.d.sync += self._bit_index.eq(0) + m.d.sync += self._baud_counter.eq(0) with m.Else(): - # m.d.sync += self.data_o.eq(Cat(self.rx_q, self.data_o[0:7])) - m.d.sync += self.data_o.eq(Cat(self.data_o[1:8], self.rx_q)) - m.d.sync += self.bit_index.eq(self.bit_index - 1) - m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + # m.d.sync += self.data_o.eq(Cat(self._rx_q, self.data_o[0:7])) + m.d.sync += self.data_o.eq(Cat(self.data_o[1:8], self._rx_q)) + m.d.sync += self._bit_index.eq(self._bit_index - 1) + m.d.sync += self._baud_counter.eq(self._clocks_per_baud - 1) with m.Else(): - m.d.sync += self.baud_counter.eq(self.baud_counter - 1) + m.d.sync += self._baud_counter.eq(self._baud_counter - 1) return m diff --git a/src/manta/uart/transmit_bridge.py b/src/manta/uart/transmit_bridge.py index 3f1b640..2505309 100644 --- a/src/manta/uart/transmit_bridge.py +++ b/src/manta/uart/transmit_bridge.py @@ -2,86 +2,91 @@ from amaranth import * class TransmitBridge(Elaboratable): + """ + A module for bridging Manta's internal bus to the stream of bytes + expected by the UARTTransmitter module. + """ + def __init__(self): # Top-Level Ports self.data_i = Signal(16) self.rw_i = Signal() self.valid_i = Signal() - self.data_o = Signal(8, reset=0) + self.data_o = Signal(8) self.start_o = Signal(1) self.done_i = Signal() # Internal Signals - self.buffer = Signal(16, reset=0) - self.count = Signal(4, reset=0) - self.busy = Signal(1, reset=0) - self.to_ascii_hex = Signal(8) - self.n = Signal(4) + self._buffer = Signal(16) + self._count = Signal(4) + self._busy = Signal(1) + self._to_ascii_hex = Signal(8) + self._n = Signal(4) def elaborate(self, platform): m = Module() - m.d.comb += self.start_o.eq(self.busy) + m.d.comb += self.start_o.eq(self._busy) - with m.If(~self.busy): + with m.If(~self._busy): with m.If((self.valid_i) & (~self.rw_i)): - m.d.sync += self.busy.eq(1) - m.d.sync += self.buffer.eq(self.data_i) + m.d.sync += self._busy.eq(1) + m.d.sync += self._buffer.eq(self.data_i) with m.Else(): # uart_tx is transmitting a byte: with m.If(self.done_i): - m.d.sync += self.count.eq(self.count + 1) + m.d.sync += self._count.eq(self._count + 1) # Message has been transmitted - with m.If(self.count > 5): - m.d.sync += self.count.eq(0) + with m.If(self._count > 5): + m.d.sync += self._count.eq(0) # Go back to idle, or transmit next message with m.If((self.valid_i) & (~self.rw_i)): - m.d.sync += self.buffer.eq(self.data_i) + m.d.sync += self._buffer.eq(self.data_i) with m.Else(): - m.d.sync += self.busy.eq(0) + m.d.sync += self._busy.eq(0) # define to_ascii_hex - with m.If(self.n < 10): - m.d.comb += self.to_ascii_hex.eq(self.n + 0x30) + with m.If(self._n < 10): + m.d.comb += self._to_ascii_hex.eq(self._n + 0x30) with m.Else(): - m.d.comb += self.to_ascii_hex.eq(self.n + 0x41 - 10) + m.d.comb += self._to_ascii_hex.eq(self._n + 0x41 - 10) # run the sequence - with m.If(self.count == 0): - m.d.comb += self.n.eq(0) + with m.If(self._count == 0): + m.d.comb += self._n.eq(0) m.d.comb += self.data_o.eq(ord("D")) - with m.Elif(self.count == 1): - m.d.comb += self.n.eq(self.buffer[12:16]) - m.d.comb += self.data_o.eq(self.to_ascii_hex) + with m.Elif(self._count == 1): + m.d.comb += self._n.eq(self._buffer[12:16]) + m.d.comb += self.data_o.eq(self._to_ascii_hex) - with m.Elif(self.count == 2): - m.d.comb += self.n.eq(self.buffer[8:12]) - m.d.comb += self.data_o.eq(self.to_ascii_hex) + with m.Elif(self._count == 2): + m.d.comb += self._n.eq(self._buffer[8:12]) + m.d.comb += self.data_o.eq(self._to_ascii_hex) - with m.Elif(self.count == 3): - m.d.comb += self.n.eq(self.buffer[4:8]) - m.d.comb += self.data_o.eq(self.to_ascii_hex) + with m.Elif(self._count == 3): + m.d.comb += self._n.eq(self._buffer[4:8]) + m.d.comb += self.data_o.eq(self._to_ascii_hex) - with m.Elif(self.count == 4): - m.d.comb += self.n.eq(self.buffer[0:4]) - m.d.comb += self.data_o.eq(self.to_ascii_hex) + with m.Elif(self._count == 4): + m.d.comb += self._n.eq(self._buffer[0:4]) + m.d.comb += self.data_o.eq(self._to_ascii_hex) - with m.Elif(self.count == 5): - m.d.comb += self.n.eq(0) + with m.Elif(self._count == 5): + m.d.comb += self._n.eq(0) m.d.comb += self.data_o.eq(ord("\r")) - with m.Elif(self.count == 6): - m.d.comb += self.n.eq(0) + with m.Elif(self._count == 6): + m.d.comb += self._n.eq(0) m.d.comb += self.data_o.eq(ord("\n")) with m.Else(): - m.d.comb += self.n.eq(0) + m.d.comb += self._n.eq(0) m.d.comb += self.data_o.eq(0) return m diff --git a/src/manta/uart/transmitter.py b/src/manta/uart/transmitter.py index b67a1ab..2084c0a 100644 --- a/src/manta/uart/transmitter.py +++ b/src/manta/uart/transmitter.py @@ -2,8 +2,13 @@ from amaranth import * class UARTTransmitter(Elaboratable): + """ + A module for transmitting bytes on a 8N1 UART at a configurable + baudrate. Accepts bytes as a stream. + """ + def __init__(self, clocks_per_baud): - self.clocks_per_baud = clocks_per_baud + self._clocks_per_baud = clocks_per_baud # Top-Level Ports self.data_i = Signal(8) @@ -13,38 +18,40 @@ class UARTTransmitter(Elaboratable): self.tx = Signal(reset=1) # Internal Signals - self.baud_counter = Signal(range(clocks_per_baud)) - self.buffer = Signal(9) - self.bit_index = Signal(4) + self._baud_counter = Signal(range(self._clocks_per_baud)) + self._buffer = Signal(9) + self._bit_index = Signal(4) def elaborate(self, platform): m = Module() with m.If((self.start_i) & (self.done_o)): - m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) - m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) - m.d.sync += self.bit_index.eq(0) + m.d.sync += self._baud_counter.eq(self._clocks_per_baud - 1) + m.d.sync += self._buffer.eq(Cat(self.data_i, 1)) + m.d.sync += self._bit_index.eq(0) m.d.sync += self.done_o.eq(0) m.d.sync += self.tx.eq(0) with m.Elif(~self.done_o): - m.d.sync += self.baud_counter.eq(self.baud_counter - 1) - m.d.sync += self.done_o.eq((self.baud_counter == 1) & (self.bit_index == 9)) + m.d.sync += self._baud_counter.eq(self._baud_counter - 1) + m.d.sync += self.done_o.eq( + (self._baud_counter == 1) & (self._bit_index == 9) + ) # A baud period has elapsed - with m.If(self.baud_counter == 0): - m.d.sync += self.baud_counter.eq(self.clocks_per_baud - 1) + with m.If(self._baud_counter == 0): + m.d.sync += self._baud_counter.eq(self._clocks_per_baud - 1) # Clock out another bit if there are any left - with m.If(self.bit_index < 9): - m.d.sync += self.tx.eq(self.buffer.bit_select(self.bit_index, 1)) - m.d.sync += self.bit_index.eq(self.bit_index + 1) + with m.If(self._bit_index < 9): + m.d.sync += self.tx.eq(self._buffer.bit_select(self._bit_index, 1)) + m.d.sync += self._bit_index.eq(self._bit_index + 1) # Byte has been sent, send out next one or go to idle with m.Else(): with m.If(self.start_i): - m.d.sync += self.buffer.eq(Cat(self.data_i, 1)) - m.d.sync += self.bit_index.eq(0) + m.d.sync += self._buffer.eq(Cat(self.data_i, 1)) + m.d.sync += self._bit_index.eq(0) m.d.sync += self.tx.eq(0) with m.Else(): From 0e1bc30802fbce9fac62c89a8dbc755c0b10cb31 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 17 Feb 2024 15:18:57 -0800 Subject: [PATCH 49/89] wrap docstrings at 80 chars --- src/manta/ethernet/__init__.py | 24 +++++++++++++----------- src/manta/ethernet/sink_bridge.py | 6 ++---- src/manta/ethernet/source_bridge.py | 6 ++---- src/manta/logic_analyzer/__init__.py | 3 ++- src/manta/logic_analyzer/playback.py | 13 ++++--------- src/manta/logic_analyzer/sample_mem.py | 5 +++++ src/manta/uart/__init__.py | 23 +++++++++++++---------- src/manta/uart/receive_bridge.py | 4 ++-- src/manta/uart/receiver.py | 4 ++-- src/manta/uart/transmit_bridge.py | 4 ++-- src/manta/uart/transmitter.py | 4 ++-- 11 files changed, 49 insertions(+), 47 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index 2fd1104..e283237 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -10,8 +10,8 @@ class EthernetInterface(Elaboratable): """ A module for communicating with Manta over Ethernet, using UDP. - Provides methods for generating synthesizable logic for the FPGA, - as well as methods for reading and writing to memory by the host. + Provides methods for generating synthesizable logic for the FPGA, as well + as methods for reading and writing to memory by the host. """ def __init__(self, config): @@ -84,8 +84,8 @@ class EthernetInterface(Elaboratable): def get_top_level_ports(self): """ - Return the Amaranth signals that should be included as ports in the top-level - Manta module. + Return the Amaranth signals that should be included as ports in the + top-level Manta module. """ ports = [ self.rmii_clocks_ref_clk, @@ -166,8 +166,8 @@ class EthernetInterface(Elaboratable): def read(self, addrs): """ - Read the data stored in a set of address on Manta's internal memory. Addresses - must be specified as either integers or a list of integers. + Read the data stored in a set of address on Manta's internal memory. + Addresses must be specified as either integers or a list of integers. """ # Handle a single integer address @@ -205,8 +205,9 @@ class EthernetInterface(Elaboratable): def write(self, addrs, datas): """ - Write the provided data into the provided addresses in Manta's internal memory. - Addresses and data must be specified as either integers or a list of integers. + Write the provided data into the provided addresses in Manta's internal + memory. Addresses and data must be specified as either integers or a + list of integers. """ # Handle a single integer address and data @@ -241,9 +242,10 @@ class EthernetInterface(Elaboratable): def generate_liteeth_core(self): """ - Generate a LiteEth core by calling a slightly modified form of the LiteEth - standalone core generator. This passes the contents of the 'ethernet' section - of the Manta configuration file to LiteEth, after modifying it slightly. + Generate a LiteEth core by calling a slightly modified form of the + LiteEth standalone core generator. This passes the contents of the + 'ethernet' section of the Manta configuration file to LiteEth, after + modifying it slightly. """ liteeth_config = self._config.copy() diff --git a/src/manta/ethernet/sink_bridge.py b/src/manta/ethernet/sink_bridge.py index ecff0d0..621d8b9 100644 --- a/src/manta/ethernet/sink_bridge.py +++ b/src/manta/ethernet/sink_bridge.py @@ -4,10 +4,8 @@ from manta.utils import * class UDPSinkBridge(Elaboratable): """ - A module for bridging Manta's internal bus to an AXI stream of UDP - packet data. - - Connects to the LiteEth core's "sink" port. + A module for bridging Manta's internal bus to an AXI stream of UDP packet + data. Connects to the LiteEth core's "sink" port. """ def __init__(self): diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py index 9506636..91b7fbc 100644 --- a/src/manta/ethernet/source_bridge.py +++ b/src/manta/ethernet/source_bridge.py @@ -4,10 +4,8 @@ from manta.utils import * class UDPSourceBridge(Elaboratable): """ - A module for bridging the AXI-stream of incoming UDP packet data to - Manta's internal bus. - - Connects to the LiteEth core's "source" port. + A module for bridging the AXI-stream of incoming UDP packet data to Manta's + internal bus. Connects to the LiteEth core's "source" port. """ def __init__(self): diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index fddcfa6..0d34941 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -7,7 +7,8 @@ from manta.logic_analyzer.playback import LogicAnalyzerPlayback class LogicAnalyzerCore(Elaboratable): - """A logic analzyer, implemented in the FPGA fabric. Connects to the rest of the cores + """ + A logic analzyer, implemented in the FPGA fabric. Connects to the rest of the cores over Manta's internal bus, and may be operated from a user's machine through the Python API. Parameters: diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index 50100e6..3cf17aa 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -2,16 +2,11 @@ from amaranth import * class LogicAnalyzerPlayback(Elaboratable): - """A synthesizable module that plays back data captured by a LogicAnalyzerCore. + """ + A synthesizable module that plays back data captured by a LogicAnalyzerCore. - Parameters: - ---------- - data : list[int] - The raw captured data taken by the LogicAnalyzerCore. This consists of the values of - all the input probes concatenated together at every timestep. - - config : dict - The configuration of the LogicAnalyzerCore that took this capture. + Takes a list of all the samples captured by a core, along with the config + of the core used to take it. """ def __init__(self, data, config): diff --git a/src/manta/logic_analyzer/sample_mem.py b/src/manta/logic_analyzer/sample_mem.py index fc8f218..045fabb 100644 --- a/src/manta/logic_analyzer/sample_mem.py +++ b/src/manta/logic_analyzer/sample_mem.py @@ -3,6 +3,11 @@ from manta.memory_core import ReadOnlyMemoryCore class LogicAnalyzerSampleMemory(ReadOnlyMemoryCore): + """ + A module that wraps a ReadOnlyMemoryCore, using the config from a LogicAnalyzerCore + to determine the parameters with which to instantiate the core. + """ + def __init__(self, config, base_addr, interface): width = sum(config["probes"].values()) depth = config["sample_depth"] diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index 60bab24..d584ad5 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -11,8 +11,8 @@ class UARTInterface(Elaboratable): """ A module for communicating with Manta over UART. - Provides methods for generating synthesizable logic for the FPGA, - as well as methods for reading and writing to memory by the host. + Provides methods for generating synthesizable logic for the FPGA, as well + as methods for reading and writing to memory by the host. """ def __init__(self, port, baudrate, clock_freq, chunk_size=256): @@ -80,7 +80,8 @@ class UARTInterface(Elaboratable): def _get_serial_device(self): """ - Return an open PySerial serial device if one exists, otherwise, open one and return it. + Return an open PySerial serial device if one exists, otherwise, open + one and return it. """ # Check if we've already opened a device @@ -129,15 +130,15 @@ class UARTInterface(Elaboratable): def get_top_level_ports(self): """ - Return the Amaranth signals that should be included as ports in the top-level - Manta module. + Return the Amaranth signals that should be included as ports in the + top-level Manta module. """ return [self.rx, self.tx] def read(self, addrs): """ - Read the data stored in a set of address on Manta's internal memory. Addresses - must be specified as either integers or a list of integers. + Read the data stored in a set of address on Manta's internal memory. + Addresses must be specified as either integers or a list of integers. """ # Handle a single integer address @@ -180,8 +181,9 @@ class UARTInterface(Elaboratable): def write(self, addrs, datas): """ - Write the provided data into the provided addresses in Manta's internal memory. - Addresses and data must be specified as either integers or a list of integers. + Write the provided data into the provided addresses in Manta's internal + memory. Addresses and data must be specified as either integers or a + list of integers. """ # Handle a single integer address and data @@ -212,7 +214,8 @@ class UARTInterface(Elaboratable): def _decode_read_response(self, response_bytes): """ - Check that read response is formatted properly, and return the encoded data if so. + Check that read response is formatted properly, and return the encoded + data if so. """ # Make sure response is not empty diff --git a/src/manta/uart/receive_bridge.py b/src/manta/uart/receive_bridge.py index 07179b1..d78c4bd 100644 --- a/src/manta/uart/receive_bridge.py +++ b/src/manta/uart/receive_bridge.py @@ -11,8 +11,8 @@ class States(IntEnum): class ReceiveBridge(Elaboratable): """ - A module for bridging the stream of bytes from the UARTReceiver - module to Manta's internal bus. + A module for bridging the stream of bytes from the UARTReceiver module to + Manta's internal bus. """ def __init__(self): diff --git a/src/manta/uart/receiver.py b/src/manta/uart/receiver.py index d42c8ea..2fe65df 100644 --- a/src/manta/uart/receiver.py +++ b/src/manta/uart/receiver.py @@ -3,8 +3,8 @@ from amaranth import * class UARTReceiver(Elaboratable): """ - A module for receiving bytes on a 8N1 UART at a configurable - baudrate. Outputs bytes as a stream. + A module for receiving bytes on a 8N1 UART at a configurable baudrate. + Outputs bytes as a stream. """ def __init__(self, clocks_per_baud): diff --git a/src/manta/uart/transmit_bridge.py b/src/manta/uart/transmit_bridge.py index 2505309..abb1c82 100644 --- a/src/manta/uart/transmit_bridge.py +++ b/src/manta/uart/transmit_bridge.py @@ -3,8 +3,8 @@ from amaranth import * class TransmitBridge(Elaboratable): """ - A module for bridging Manta's internal bus to the stream of bytes - expected by the UARTTransmitter module. + A module for bridging Manta's internal bus to the stream of bytes expected + by the UARTTransmitter module. """ def __init__(self): diff --git a/src/manta/uart/transmitter.py b/src/manta/uart/transmitter.py index 2084c0a..cea5764 100644 --- a/src/manta/uart/transmitter.py +++ b/src/manta/uart/transmitter.py @@ -3,8 +3,8 @@ from amaranth import * class UARTTransmitter(Elaboratable): """ - A module for transmitting bytes on a 8N1 UART at a configurable - baudrate. Accepts bytes as a stream. + A module for transmitting bytes on a 8N1 UART at a configurable baudrate. + Accepts bytes as a stream. """ def __init__(self, clocks_per_baud): From ea6b3f73b9a2b98e4565da486910aeb133243e87 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 17 Feb 2024 16:07:29 -0800 Subject: [PATCH 50/89] add docstrings --- src/manta/ethernet/__init__.py | 3 + src/manta/io_core.py | 60 ++++++---- src/manta/logic_analyzer/__init__.py | 34 +++--- src/manta/logic_analyzer/fsm.py | 10 +- src/manta/logic_analyzer/playback.py | 4 + src/manta/logic_analyzer/trigger_block.py | 17 ++- src/manta/manta.py | 4 + src/manta/memory_core.py | 137 ++++++++++++---------- src/manta/uart/__init__.py | 3 + 9 files changed, 167 insertions(+), 105 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index e283237..1d779a9 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -12,6 +12,9 @@ class EthernetInterface(Elaboratable): Provides methods for generating synthesizable logic for the FPGA, as well as methods for reading and writing to memory by the host. + + More information available in the online documentation at: + https://fischermoseley.github.io/manta/ethernet_interface/ """ def __init__(self, config): diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 39c0634..91322d80 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -5,20 +5,26 @@ from math import ceil class IOCore(Elaboratable): """ - Contains the HDL to instantiate an IO core on a FPGA, and the functions to interact with it. For - more information on the core itself, check out the IO core documentation. + A module for setting and getting the values of registers of arbitrary size + on a FPGA. + + Provides methods for generating synthesizable logic for the FPGA, as well + as methods for reading and writing the value of a register. + + More information available in the online documentation at: + https://fischermoseley.github.io/manta/io_core/ """ def __init__(self, config, base_addr, interface): - self.config = config + self._config = config self.base_addr = base_addr self.interface = interface + self._check_config(self._config) - self.check_config(self.config) self.define_signals() self.mmap, self.max_addr = self.assign_memory() - def check_config(self, config): + def _check_config(self, config): # make sure ports are defined if "inputs" not in config and "outputs" not in config: raise ValueError("No input or output ports specified.") @@ -91,14 +97,14 @@ class IOCore(Elaboratable): self.bus_o = Signal(InternalBus()) # Input Probes (and buffers) - if "inputs" in self.config: - for name, width in self.config["inputs"].items(): + if "inputs" in self._config: + for name, width in self._config["inputs"].items(): setattr(self, name, Signal(width, name=name)) setattr(self, name + "_buf", Signal(width, name=name + "_buf")) # Output Probes (and buffers) - if "outputs" in self.config: - for name, attrs in self.config["outputs"].items(): + if "outputs" in self._config: + for name, attrs in self._config["outputs"].items(): if isinstance(attrs, dict): width = attrs["width"] initial_value = attrs["initial_value"] @@ -148,11 +154,11 @@ class IOCore(Elaboratable): # Add all input and output probes all_probes = {} - if "inputs" in self.config: - all_probes = {**all_probes, **self.config["inputs"]} + if "inputs" in self._config: + all_probes = {**all_probes, **self._config["inputs"]} - if "outputs" in self.config: - all_probes = {**all_probes, **self.config["outputs"]} + if "outputs" in self._config: + all_probes = {**all_probes, **self._config["outputs"]} for name, attrs in all_probes.items(): # Handle output probes that might have initial value specified in addition to width @@ -184,15 +190,15 @@ class IOCore(Elaboratable): # Update buffers from probes with m.If(self.strobe): # Input buffers - if "inputs" in self.config: - for name in self.config["inputs"]: + if "inputs" in self._config: + for name in self._config["inputs"]: input_probe = getattr(self, name) input_probe_buf = getattr(self, name + "_buf") m.d.sync += input_probe_buf.eq(input_probe) # Output buffers - if "outputs" in self.config: - for name in self.config["outputs"]: + if "outputs" in self._config: + for name in self._config["outputs"]: output_probe = getattr(self, name) output_probe_buf = getattr(self, name + "_buf") m.d.sync += output_probe.eq(output_probe_buf) @@ -213,23 +219,31 @@ class IOCore(Elaboratable): return m def get_top_level_ports(self): + """ + Return the Amaranth signals that should be included as ports in the + top-level Manta module. + """ ports = [] - if "inputs" in self.config: - for name in self.config["inputs"].keys(): + if "inputs" in self._config: + for name in self._config["inputs"].keys(): ports.append(getattr(self, name)) - if "outputs" in self.config: - for name in self.config["outputs"].keys(): + if "outputs" in self._config: + for name in self._config["outputs"].keys(): ports.append(getattr(self, name)) return ports def get_max_addr(self): + """ + Return the maximum addresses in memory used by the core. The address space used + by the core extends from `base_addr` to the number returned by this function. + """ return self.max_addr def set_probe(self, probe_name, value): # check that probe is an output probe - if probe_name not in self.config["outputs"]: + if probe_name not in self._config["outputs"]: raise ValueError(f"Output probe '{probe_name}' not found.") # check that value is an integer @@ -237,7 +251,7 @@ class IOCore(Elaboratable): raise ValueError("Value must be an integer.") # get the width of the probe, make sure value isn't too large for the probe - attrs = self.config["outputs"][probe_name] + attrs = self._config["outputs"][probe_name] if isinstance(attrs, int): width = attrs diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 0d34941..66e62a0 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -8,28 +8,14 @@ from manta.logic_analyzer.playback import LogicAnalyzerPlayback class LogicAnalyzerCore(Elaboratable): """ - A logic analzyer, implemented in the FPGA fabric. Connects to the rest of the cores - over Manta's internal bus, and may be operated from a user's machine through the Python API. - - Parameters: - ---------- - config : dict - Configuration options. This is taken from the section of Manta's configuration YAML that - describes the core. - - base_addr : int - Where to place the core in Manta's internal memory map. This determines the beginning of - the core's address space. The end of the core's address space may be obtained by calling - the get_max_addr() method. - - interface : UARTInterface or EthernetInterface - The interface used to communicate with the core. - - Attributes: - ---------- - None + A module for generating a logic analyzer on the FPGA, with configurable + triggers, trigger position, and trigger modes. + Provides methods for generating synthesizable logic for the FPGA, as well + as methods for reading and writing the value of a register. + More information available in the online documentation at: + https://fischermoseley.github.io/manta/logic_analyzer_core/ """ def __init__(self, config, base_addr, interface): @@ -186,6 +172,10 @@ class LogicAnalyzerCore(Elaboratable): return m def get_top_level_ports(self): + """ + Return the Amaranth signals that should be included as ports in the + top-level Manta module. + """ return self.probes def get_probe(self, name): @@ -196,6 +186,10 @@ class LogicAnalyzerCore(Elaboratable): raise ValueError(f"Probe '{name}' not found in Logic Analyzer core.") def get_max_addr(self): + """ + Return the maximum addresses in memory used by the core. The address space used + by the core extends from `base_addr` to the number returned by this function. + """ return self.sample_mem.get_max_addr() def capture(self, verbose=False): diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 2c8215d..d90322a 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -19,7 +19,11 @@ class TriggerModes(IntEnum): class LogicAnalyzerFSM(Elaboratable): - """ """ + """ + A module containing the state machine for a LogicAnalyzerCore. Primarily + responsible for controlling the write port of the Logic Analyzer's sample + memory in each trigger mode (immediate, incremental, single-shot). + """ def __init__(self, config, base_addr, interface): self.config = config @@ -47,6 +51,10 @@ class LogicAnalyzerFSM(Elaboratable): self.bus_o = self.r.bus_o def get_max_addr(self): + """ + Return the maximum addresses in memory used by the core. The address space used + by the core extends from `base_addr` to the number returned by this function. + """ return self.r.get_max_addr() def increment_mod_sample_depth(self, m, signal): diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index 3cf17aa..3fc72e4 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -72,4 +72,8 @@ class LogicAnalyzerPlayback(Elaboratable): return m def get_top_level_ports(self): + """ + Return the Amaranth signals that should be included as ports in the + exported Verilog module. + """ return [self.start, self.valid] + list(self.top_level_probes.values()) diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 3cfbba5..f0bf5f6 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -3,7 +3,12 @@ from manta.io_core import IOCore class LogicAnalyzerTriggerBlock(Elaboratable): - """ """ + """ + A module containing an instance of a LogicAnalyzerTrigger for each input + probe. The operations and arguments of these LogicAnalyzerTriggers are set + with an internal IOCore, which is connected to the internal bus, and allows + the triggers to be reprogrammed without reflashing the FPGA. + """ def __init__(self, probes, base_addr, interface): # Instantiate a bunch of trigger blocks @@ -26,6 +31,10 @@ class LogicAnalyzerTriggerBlock(Elaboratable): self.trig = Signal(1) def get_max_addr(self): + """ + Return the maximum addresses in memory used by the core. The address space used + by the core extends from `base_addr` to the number returned by this function. + """ return self.r.get_max_addr() def clear_triggers(self): @@ -71,6 +80,12 @@ class LogicAnalyzerTriggerBlock(Elaboratable): class LogicAnalyzerTrigger(Elaboratable): + """ + A module containing a programmable "trigger" for a given input signal, + which asserts its output when the programmed "trigger condition" is met. + This condition is programmed through the `op` and `arg` inputs. + """ + def __init__(self, signal): self.operations = { "DISABLE": 0, diff --git a/src/manta/manta.py b/src/manta/manta.py index 313af71..3625a19 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -149,6 +149,10 @@ class Manta(Elaboratable): return m def get_top_level_ports(self): + """ + Return the Amaranth signals that should be included as ports in the + top-level Manta module. + """ ports = self.interface.get_top_level_ports() for name, instance in self.cores.items(): diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 50c78f8..a99549a 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -4,21 +4,39 @@ from math import ceil class ReadOnlyMemoryCore(Elaboratable): + """ + A module for generating a memory on the FPGA, with a read port tied to + Manta's internal bus, and a write port provided to user logic. + + Provides methods for generating synthesizable logic for the FPGA, as well + as methods for reading and writing the value of a register. + + More information available in the online documentation at: + https://fischermoseley.github.io/manta/memory_core/ + """ + def __init__(self, config, base_addr, interface): - self.config = config - self.base_addr = base_addr - self.interface = interface + self._config = config + self._base_addr = base_addr + self._interface = interface + self._check_config(config) - self.check_config(config) + self._depth = self._config["depth"] + self._width = self._config["width"] + self._max_addr = self._base_addr + (self._depth * ceil(self._width / 16)) - self.depth = self.config["depth"] - self.width = self.config["width"] - self.max_addr = self.base_addr + (self.depth * ceil(self.width / 16)) + # Bus Connections + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) - self.define_signals() - self.define_mems() + # User Port + self.user_addr = Signal(range(self._depth)) + self.user_data = Signal(self._width) + self.user_we = Signal(1) - def check_config(self, config): + self._define_mems() + + def _check_config(self, config): # Check for unrecognized options valid_options = ["type", "depth", "width"] for option in config: @@ -45,56 +63,46 @@ class ReadOnlyMemoryCore(Elaboratable): if config["width"] <= 0: raise ValueError("Width of memory core must be positive. ") - def define_signals(self): - # Bus Input/Pipelining/Output - self.bus_i = Signal(InternalBus()) - self.bus_pipe = [Signal(InternalBus()) for _ in range(3)] - self.bus_o = Signal(InternalBus()) - - # User Port - self.user_addr = Signal(range(self.depth)) - self.user_data = Signal(self.width) - self.user_we = Signal(1) - - def pipeline_bus(self, m): - m.d.sync += self.bus_pipe[0].eq(self.bus_i) + def _pipeline_bus(self, m): + self._bus_pipe = [Signal(InternalBus()) for _ in range(3)] + m.d.sync += self._bus_pipe[0].eq(self.bus_i) for i in range(1, 3): - m.d.sync += self.bus_pipe[i].eq(self.bus_pipe[i - 1]) + m.d.sync += self._bus_pipe[i].eq(self._bus_pipe[i - 1]) - m.d.sync += self.bus_o.eq(self.bus_pipe[2]) + m.d.sync += self.bus_o.eq(self._bus_pipe[2]) - def define_mems(self): - # ok there's three cases: - # 1. integer number of 16 bit mems - # 2. integer number of 16 bit mems + partial mem - # 3. just the partial mem (width < 16) + def _define_mems(self): + # There's three cases that must be handled: + # 1. Integer number of 16 bit mems + # 2. Integer number of 16 bit mems + partial mem + # 3. Just the partial mem (width < 16) # Only one, partial-width memory is needed - if self.width < 16: - self.mems = [Memory(depth=self.depth, width=self.width)] + if self._width < 16: + self._mems = [Memory(depth=self._depth, width=self._width)] # Only full-width memories are needed - elif self.width % 16 == 0: - self.mems = [ - Memory(depth=self.depth, width=16) for _ in range(self.width // 16) + elif self._width % 16 == 0: + self._mems = [ + Memory(depth=self._depth, width=16) for _ in range(self._width // 16) ] # Both full-width and partial memories are needed else: - self.mems = [ - Memory(depth=self.depth, width=16) for i in range(self.width // 16) + self._mems = [ + Memory(depth=self._depth, width=16) for i in range(self._width // 16) ] - self.mems += [Memory(depth=self.depth, width=self.width % 16)] + self._mems += [Memory(depth=self._depth, width=self._width % 16)] - def handle_read_ports(self, m): + def _handle_read_ports(self, m): # These are tied to the bus - for i, mem in enumerate(self.mems): + for i, mem in enumerate(self._mems): read_port = mem.read_port() m.d.comb += read_port.en.eq(1) - start_addr = self.base_addr + (i * self.depth) - stop_addr = start_addr + self.depth - 1 + start_addr = self._base_addr + (i * self._depth) + stop_addr = start_addr + self._depth - 1 # Throw BRAM operations into the front of the pipeline with m.If( @@ -107,16 +115,16 @@ class ReadOnlyMemoryCore(Elaboratable): # Pull BRAM reads from the back of the pipeline with m.If( - (self.bus_pipe[2].valid) - & (~self.bus_pipe[2].rw) - & (self.bus_pipe[2].addr >= start_addr) - & (self.bus_pipe[2].addr <= stop_addr) + (self._bus_pipe[2].valid) + & (~self._bus_pipe[2].rw) + & (self._bus_pipe[2].addr >= start_addr) + & (self._bus_pipe[2].addr <= stop_addr) ): m.d.sync += self.bus_o.data.eq(read_port.data) - def handle_write_ports(self, m): + def _handle_write_ports(self, m): # These are given to the user - for i, mem in enumerate(self.mems): + for i, mem in enumerate(self._mems): write_port = mem.write_port() m.d.comb += write_port.addr.eq(self.user_addr) @@ -127,19 +135,27 @@ class ReadOnlyMemoryCore(Elaboratable): m = Module() # Add memories as submodules - for i, mem in enumerate(self.mems): + for i, mem in enumerate(self._mems): m.submodules[f"mem_{i}"] = mem - self.pipeline_bus(m) - self.handle_read_ports(m) - self.handle_write_ports(m) + self._pipeline_bus(m) + self._handle_read_ports(m) + self._handle_write_ports(m) return m def get_top_level_ports(self): + """ + Return the Amaranth signals that should be included as ports in the + top-level Manta module. + """ return [self.user_addr, self.user_data, self.user_we] def get_max_addr(self): - return self.max_addr + """ + Return the maximum addresses in memory used by the core. The address space used + by the core extends from `base_addr` to the number returned by this function. + """ + return self._max_addr def read_from_user_addr(self, addrs): """ @@ -147,8 +163,9 @@ class ReadOnlyMemoryCore(Elaboratable): """ # Convert user address space to bus address space - # (for instance, for a core with base address 10 and width 33, - # reading from address 4 is actually a read from address 14 and address 14 + depth, and address 14 + 2*depth) + # (for instance, for a core with base address 10 and width 33, + # reading from address 4 is actually a read from address 14 + # and address 14 + depth, and address 14 + 2*depth) if isinstance(addrs, int): return self.read_from_user_addr([addrs])[0] @@ -156,11 +173,11 @@ class ReadOnlyMemoryCore(Elaboratable): bus_addrs = [] for addr in addrs: bus_addrs += [ - addr + self.base_addr + i * self.depth for i in range(len(self.mems)) + addr + self._base_addr + i * self._depth for i in range(len(self._mems)) ] - datas = self.interface.read(bus_addrs) - data_chunks = split_into_chunks(datas, len(self.mems)) + datas = self._interface.read(bus_addrs) + data_chunks = split_into_chunks(datas, len(self._mems)) return [words_to_value(chunk) for chunk in data_chunks] # def write_to_user_addr(self, addrs, datas): @@ -171,11 +188,11 @@ class ReadOnlyMemoryCore(Elaboratable): # bus_addrs = [] # for addr in addrs: # bus_addrs += [ - # addr + self.base_addr + i * self.depth for i in range(len(self.mems)) + # addr + self._base_addr + i * self._depth for i in range(len(self._mems)) # ] # bus_datas = [] # for data in datas: # bus_datas += value_to_words(data) - # self.interface.write(bus_addrs, bus_datas) + # self._interface.write(bus_addrs, bus_datas) diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index d584ad5..2e38cf4 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -13,6 +13,9 @@ class UARTInterface(Elaboratable): Provides methods for generating synthesizable logic for the FPGA, as well as methods for reading and writing to memory by the host. + + More information available in the online documentation at: + https://fischermoseley.github.io/manta/uart_interface/ """ def __init__(self, port, baudrate, clock_freq, chunk_size=256): From 3f724b333684b1e89991a871dbdb25860e2f9b72 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 17 Feb 2024 21:34:17 -0800 Subject: [PATCH 51/89] add width check function to utils --- src/manta/logic_analyzer/__init__.py | 5 +++-- src/manta/logic_analyzer/fsm.py | 5 +++-- src/manta/logic_analyzer/trigger_block.py | 5 +++-- src/manta/memory_core.py | 5 +++-- src/manta/utils.py | 23 +++++++++++++++++------ 5 files changed, 29 insertions(+), 14 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 66e62a0..b46a449 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -187,8 +187,9 @@ class LogicAnalyzerCore(Elaboratable): def get_max_addr(self): """ - Return the maximum addresses in memory used by the core. The address space used - by the core extends from `base_addr` to the number returned by this function. + Return the maximum addresses in memory used by the core. The address + space used by the core extends from `base_addr` to the number returned + by this function. """ return self.sample_mem.get_max_addr() diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index d90322a..461fa8b 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -52,8 +52,9 @@ class LogicAnalyzerFSM(Elaboratable): def get_max_addr(self): """ - Return the maximum addresses in memory used by the core. The address space used - by the core extends from `base_addr` to the number returned by this function. + Return the maximum addresses in memory used by the core. The address + space used by the core extends from `base_addr` to the number returned + by this function. """ return self.r.get_max_addr() diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index f0bf5f6..487a9c4 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -32,8 +32,9 @@ class LogicAnalyzerTriggerBlock(Elaboratable): def get_max_addr(self): """ - Return the maximum addresses in memory used by the core. The address space used - by the core extends from `base_addr` to the number returned by this function. + Return the maximum addresses in memory used by the core. The address + space used by the core extends from `base_addr` to the number returned + by this function. """ return self.r.get_max_addr() diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index a99549a..6d92ee4 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -152,8 +152,9 @@ class ReadOnlyMemoryCore(Elaboratable): def get_max_addr(self): """ - Return the maximum addresses in memory used by the core. The address space used - by the core extends from `base_addr` to the number returned by this function. + Return the maximum addresses in memory used by the core. The address + space used by the core extends from `base_addr` to the number returned + by this function. """ return self._max_addr diff --git a/src/manta/utils.py b/src/manta/utils.py index 1e63bcb..7fe12f2 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -38,16 +38,27 @@ def words_to_value(data): concatenates them together in little-endian order. """ - for d in data: - if d > 0 and d > 2**16 - 1: - raise ValueError("Unsigned integer too large.") - - if d < 0 and d < -(2**15): - raise ValueError("Signed integer too large.") + [check_value_fits_in_bits(d, 16) for d in data] return int("".join([f"{i:016b}" for i in data[::-1]]), 2) +def check_value_fits_in_bits(value, n_bits): + """ + Rasies an exception if the provided value isn't an integer that cannot + be expressed with the provided number of bits. + """ + + if not isinstance(value, int): + raise TypeError("Value must be an integer.") + + if value > 0 and value > 2**n_bits - 1: + raise ValueError("Unsigned integer too large.") + + if value < 0 and value < -(2 ** (n_bits - 1)): + raise ValueError("Signed integer too large.") + + def value_to_words(data, n_words): """ Takes a integer, interprets it as a set of 16-bit integers From 0c0f31be64d9208dbed5a9b7e1fb91a901fe05a5 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 18 Feb 2024 13:50:26 -0800 Subject: [PATCH 52/89] rewrite IO Core --- src/manta/io_core.py | 390 +++++++++++++++++---------------------- src/manta/manta.py | 2 +- test/test_io_core_hw.py | 32 +++- test/test_io_core_sim.py | 102 ++++------ 4 files changed, 232 insertions(+), 294 deletions(-) diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 91322d80..648be7c 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -15,171 +15,133 @@ class IOCore(Elaboratable): https://fischermoseley.github.io/manta/io_core/ """ - def __init__(self, config, base_addr, interface): - self._config = config - self.base_addr = base_addr - self.interface = interface - self._check_config(self._config) + def __init__(self, base_addr, interface, inputs=[], outputs=[]): + self._base_addr = base_addr + self._interface = interface + self._inputs = inputs + self._outputs = outputs - self.define_signals() - self.mmap, self.max_addr = self.assign_memory() + # Bus Connections + self.bus_i = Signal(InternalBus()) + self.bus_o = Signal(InternalBus()) - def _check_config(self, config): - # make sure ports are defined - if "inputs" not in config and "outputs" not in config: - raise ValueError("No input or output ports specified.") + # Internal Signals + self._strobe = Signal() + self._input_bufs = [Signal(p.width, name=p.name + "_buf") for p in self._inputs] + self._output_bufs = [ + Signal(p.width, name=p.name + "_buf", reset=p.reset) for p in self._outputs + ] - # check for unrecognized options - valid_options = ["type", "inputs", "outputs", "user_clock"] + self._make_memory_map() + + @classmethod + def from_config(cls, config, base_addr, interface): + inputs = config.get("inputs", []) + outputs = config.get("outputs", []) + + # Make sure IO core has at least one input or output + if not inputs and not outputs: + raise ValueError("Must specify at least one input or output port.") + + # Warn about unrecognized options + valid_options = ["type", "inputs", "outputs"] for option in config: if option not in valid_options: warn(f"Ignoring unrecognized option '{option}' in IO core.'") - # check that user_clock is a bool - if "user_clock" in config: - if not isinstance(config["user_clock"], bool): - raise ValueError("Option user_clock must be a boolean.") - - # check that inputs is only dicts of format name:width - if "inputs" in config: - for name, attrs in config["inputs"].items(): - if not isinstance(name, str): - raise ValueError( - f'Input probe "{name}" has invalid name, names must be strings.' - ) - - if not isinstance(attrs, int): - raise ValueError(f'Input probe "{name}" must have integer width.') - - if not attrs > 0: - raise ValueError(f'Input probe "{name}" must have positive width.') - - if "outputs" in config: - for name, attrs in config["outputs"].items(): - if not isinstance(name, str): - raise ValueError( - f'Output probe "{name}" has invalid name, names must be strings.' - ) - - if not isinstance(attrs, int) and not isinstance(attrs, dict): - raise ValueError(f'Unrecognized format for output probe "{name}".') - - if isinstance(attrs, int): - if not attrs > 0: - raise ValueError( - f'Output probe "{name}" must have positive width.' - ) - - if isinstance(attrs, dict): - # check that each output probe has only recognized options - valid_options = ["width", "initial_value"] - for option in attrs: - if option not in valid_options: - warn(f'Ignoring unrecognized option "{option}" in IO core.') - - # check that widths are appropriate - if "width" not in attrs: - raise ValueError(f"No width specified for output probe {name}.") - - if not isinstance(attrs["width"], int): - raise ValueError( - f'Output probe "{name}" must have integer width.' - ) - - if not attrs["width"] > 0: - raise ValueError( - f'Input probe "{name}" must have positive width.' - ) - - def define_signals(self): - # Bus Input/Output - self.bus_i = Signal(InternalBus()) - self.bus_o = Signal(InternalBus()) - - # Input Probes (and buffers) - if "inputs" in self._config: - for name, width in self._config["inputs"].items(): - setattr(self, name, Signal(width, name=name)) - setattr(self, name + "_buf", Signal(width, name=name + "_buf")) - - # Output Probes (and buffers) - if "outputs" in self._config: - for name, attrs in self._config["outputs"].items(): - if isinstance(attrs, dict): - width = attrs["width"] - initial_value = attrs["initial_value"] - else: - width = attrs - initial_value = 0 - - setattr(self, name, Signal(width, name=name, reset=initial_value)) - setattr( - self, - name + "_buf", - Signal(width, name=name + "_buf", reset=initial_value), + # Define input signals + input_signals = [] + for name, width in inputs.items(): + if not isinstance(name, str): + raise ValueError( + f'Input probe "{name}" has invalid name, names must be strings.' ) - # Strobe Register - self.strobe = Signal(reset=0) + if not isinstance(width, int): + raise ValueError(f"Input probe '{name}' must have integer width.") - def assign_memory(self): - """ - the memory map is a dict that maps registers (in memory) to their locations (in memory) - as well as their Signals (from Amaranth). This looks like the following: + if not width > 0: + raise ValueError(f"Input probe '{name}' must have positive width.") - { - strobe: - addrs: [0x0000] - signals: [self.strobe] - probe0_buf: - addrs: [0x0001] - signals: [self.probe0_buf] - probe1_buf: - addrs: [0x0002] - signals: [self.probe1_buf] - probe2_buf: - addrs: [0x0003] - signals: [self.probe2_buf] - probe3_buf: - addrs: [0x0004, 0x0005] - signals: [self.probe3_buf[0:15], self.probe3_buf[16:19]] - ... and so on - } + input_signals += [Signal(width, name=name)] - """ - mmap = {} + # Define output signals + output_signals = [] + for name, attrs in outputs.items(): + if not isinstance(name, str): + raise ValueError( + f'Output probe "{name}" has invalid name, names must be strings.' + ) - # Add strobe register first - mmap["strobe"] = dict(addrs=[self.base_addr], signals=[self.strobe]) + if not isinstance(attrs, int) and not isinstance(attrs, dict): + raise ValueError(f'Unrecognized format for output probe "{name}".') - # Add all input and output probes - all_probes = {} - if "inputs" in self._config: - all_probes = {**all_probes, **self._config["inputs"]} + if isinstance(attrs, int): + if not attrs > 0: + raise ValueError(f'Output probe "{name}" must have positive width.') - if "outputs" in self._config: - all_probes = {**all_probes, **self._config["outputs"]} - - for name, attrs in all_probes.items(): - # Handle output probes that might have initial value specified in addition to width - if isinstance(attrs, dict): - width = attrs["width"] - else: width = attrs + initial_value = 0 - # Assign addresses - last_used_addr = list(mmap.values())[-1]["addrs"][-1] - addrs = [last_used_addr + 1 + i for i in range(ceil(width / 16))] + if isinstance(attrs, dict): + # check that each output probe has only recognized options + valid_options = ["width", "initial_value"] + for option in attrs: + if option not in valid_options: + warn(f'Ignoring unrecognized option "{option}" in IO core.') - # Slice signal into 16-bit chunks - signal = getattr(self, name + "_buf") - signals = [signal[16 * i : 16 * (i + 1)] for i in range(ceil(width / 16))] + # check that widths are appropriate + if "width" not in attrs: + raise ValueError(f"No width specified for output probe {name}.") - mmap[name + "_buf"] = {"addrs": addrs, "signals": signals} + if not isinstance(attrs["width"], int): + raise ValueError(f'Output probe "{name}" must have integer width.') - # Compute maximum address used by the core - max_addr = list(mmap.values())[-1]["addrs"][-1] - return mmap, max_addr + if not attrs["width"] > 0: + raise ValueError(f'Input probe "{name}" must have positive width.') + + width = attrs["width"] + + initial_value = 0 + if "initial_value" in attrs: + if not isinstance(attrs["initial_value"], int): + raise ValueError("Initial value must be an integer.") + + check_value_fits_in_bits(attrs["initial_value"], width) + initial_value = attrs["initial_value"] + + output_signals += [Signal(width, name=name, reset=initial_value)] + + return cls(base_addr, interface, inputs=input_signals, outputs=output_signals) + + def _make_memory_map(self): + self._memory_map = {} + + # Add strobe register + self._memory_map["strobe"] = dict( + signals=[self._strobe], addrs=[self._base_addr] + ) + + # Assign memory to all inputs and outputs + ios = self._inputs + self._outputs + io_bufs = self._input_bufs + self._output_bufs + last_used_addr = self._base_addr + + for io, io_buf in zip(ios, io_bufs): + n_slices = ceil(io.width / 16) + signals = split_into_chunks(io_buf, 16) + addrs = [i + last_used_addr + 1 for i in range(n_slices)] + + self._memory_map[io.name] = dict(signals=signals, addrs=addrs) + + last_used_addr = addrs[-1] + + # Save the last used address, for use later. + # Normally we'd just grab this from self._memory_map, but Python + # dictionaries don't guaruntee that insertion order is preserved, + # so it's more convenient to just save it now. + + self._max_addr = last_used_addr def elaborate(self, platform): m = Module() @@ -187,34 +149,27 @@ class IOCore(Elaboratable): # Shuffle bus transactions along m.d.sync += self.bus_o.eq(self.bus_i) - # Update buffers from probes - with m.If(self.strobe): - # Input buffers - if "inputs" in self._config: - for name in self._config["inputs"]: - input_probe = getattr(self, name) - input_probe_buf = getattr(self, name + "_buf") - m.d.sync += input_probe_buf.eq(input_probe) + # Update input_buffers from inputs + for i, i_buf in zip(self._inputs, self._input_bufs): + with m.If(self._strobe): + m.d.sync += i_buf.eq(i) - # Output buffers - if "outputs" in self._config: - for name in self._config["outputs"]: - output_probe = getattr(self, name) - output_probe_buf = getattr(self, name + "_buf") - m.d.sync += output_probe.eq(output_probe_buf) + # Update outputs from output_buffers + for o, o_buf in zip(self._outputs, self._output_bufs): + with m.If(self._strobe): + m.d.sync += o.eq(o_buf) # Handle register reads and writes - with m.If((self.bus_i.addr >= self.base_addr)): - with m.If((self.bus_o.addr <= self.max_addr)): - for entry in self.mmap.values(): - for addr, signal in zip(entry["addrs"], entry["signals"]): - with m.If(self.bus_i.rw): - with m.If(self.bus_i.addr == addr): - m.d.sync += signal.eq(self.bus_i.data) + for io in self._memory_map.values(): + for addr, signal in zip(io["addrs"], io["signals"]): + with m.If(self.bus_i.addr == addr): + # Writes + with m.If(self.bus_i.rw): + m.d.sync += signal.eq(self.bus_i.data) - with m.Else(): - with m.If(self.bus_i.addr == addr): - m.d.sync += self.bus_o.data.eq(signal) + # Reads + with m.Else(): + m.d.sync += self.bus_o.data.eq(signal) return m @@ -223,65 +178,64 @@ class IOCore(Elaboratable): Return the Amaranth signals that should be included as ports in the top-level Manta module. """ - ports = [] - if "inputs" in self._config: - for name in self._config["inputs"].keys(): - ports.append(getattr(self, name)) - - if "outputs" in self._config: - for name in self._config["outputs"].keys(): - ports.append(getattr(self, name)) - - return ports + return [self._inputs + self._outputs] def get_max_addr(self): """ - Return the maximum addresses in memory used by the core. The address space used - by the core extends from `base_addr` to the number returned by this function. + Return the maximum addresses in memory used by the core. The address + space used by the core extends from `base_addr` to the number returned + by this function. """ - return self.max_addr + return self._max_addr - def set_probe(self, probe_name, value): - # check that probe is an output probe - if probe_name not in self._config["outputs"]: - raise ValueError(f"Output probe '{probe_name}' not found.") + def set_probe(self, name, value): + """ + Set the value of an output probe on the FPGA. The value may be either + an unsigned or signed integer, but must fit within the width of the + probe. + """ - # check that value is an integer - if not isinstance(value, int): - raise ValueError("Value must be an integer.") + # Check that probe exists in memory map + probe = self._memory_map.get(name) + if not probe: + raise KeyError(f"Probe '{name}' not found in IO core.") - # get the width of the probe, make sure value isn't too large for the probe - attrs = self._config["outputs"][probe_name] - if isinstance(attrs, int): - width = attrs + # Check that the probe is an output + if not any([o.name == name for o in self._outputs]): + raise KeyError(f"Probe '{name}' is not an output of the IO core.") - if isinstance(attrs, dict): - width = attrs["width"] + # Check that value isn't too big for the register + n_bits = sum([len(s) for s in probe["signals"]]) + check_value_fits_in_bits(value, n_bits) - if value > 0 and value > 2**width - 1: - raise ValueError("Unsigned integer too large.") - - if value < 0 and value < -(2 ** (width - 1)): - raise ValueError("Signed integer too large.") - - # set value in buffer - addrs = self.mmap[probe_name + "_buf"]["addrs"] + # Write value to core + addrs = probe["addrs"] datas = value_to_words(value, len(addrs)) - self.interface.write(addrs, datas) + self._interface.write(addrs, datas) - # pulse strobe register - strobe_addr = self.mmap["strobe"]["addrs"][0] - self.interface.write(strobe_addr, 0) - self.interface.write(strobe_addr, 1) - self.interface.write(strobe_addr, 0) + # Pulse strobe register + self._interface.write(self._base_addr, 0) + self._interface.write(self._base_addr, 1) + self._interface.write(self._base_addr, 0) - def get_probe(self, probe_name): - # pulse strobe register - strobe_addr = self.mmap["strobe"]["addrs"][0] - self.interface.write(strobe_addr, 0) - self.interface.write(strobe_addr, 1) - self.interface.write(strobe_addr, 0) + def get_probe(self, name): + """ + Get the present value of a probe on the FPGA, which is returned as an + unsigned integer. This function may be called on both input and output + probes, but output probes will return the last value written to them + (or their initial value, if no value has been written to them yet). + """ - # get value from buffer - addrs = self.mmap[probe_name + "_buf"]["addrs"] - return words_to_value(self.interface.read(addrs)) + # Check that probe exists in memory map + probe = self._memory_map.get(name) + if not probe: + raise KeyError(f"Probe with name {name} not found in IO core.") + + # Pulse strobe register + self._interface.write(self._base_addr, 0) + self._interface.write(self._base_addr, 1) + self._interface.write(self._base_addr, 0) + + # Get value from buffer + datas = self._interface.read(probe["addrs"]) + return words_to_value(datas) diff --git a/src/manta/manta.py b/src/manta/manta.py index 3625a19..9384957 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -78,7 +78,7 @@ class Manta(Elaboratable): base_addr = 0 for name, attrs in self.config["cores"].items(): if attrs["type"] == "io": - core = IOCore(attrs, base_addr, self.interface) + core = IOCore.from_config(attrs, base_addr, self.interface) elif attrs["type"] == "logic_analyzer": core = LogicAnalyzerCore(attrs, base_addr, self.interface) diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 1e6f31c..2c984f8 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -39,17 +39,39 @@ class IOCoreLoopbackTest(Elaboratable): }, } + def get_probe(self, name): + # This is a hack! And should be removed once the full Amaranth-native + # API is built out + for i in self.manta.io_core._inputs: + if i.name == name: + return i + + for o in self.manta.io_core._outputs: + if o.name == name: + return o + + return None + def elaborate(self, platform): m = Module() m.submodules.manta = self.manta uart_pins = platform.request("uart") + probe0 = self.get_probe("probe0") + probe1 = self.get_probe("probe1") + probe2 = self.get_probe("probe2") + probe3 = self.get_probe("probe3") + probe4 = self.get_probe("probe4") + probe5 = self.get_probe("probe5") + probe6 = self.get_probe("probe6") + probe7 = self.get_probe("probe7") + m.d.comb += [ - self.manta.io_core.probe0.eq(self.manta.io_core.probe4), - self.manta.io_core.probe1.eq(self.manta.io_core.probe5), - self.manta.io_core.probe2.eq(self.manta.io_core.probe6), - self.manta.io_core.probe3.eq(self.manta.io_core.probe7), + probe0.eq(probe4), + probe1.eq(probe5), + probe2.eq(probe6), + probe3.eq(probe7), self.manta.interface.rx.eq(uart_pins.rx.i), uart_pins.tx.o.eq(self.manta.interface.tx), ] @@ -126,4 +148,4 @@ def test_output_probe_initial_values_xilinx(): @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_output_probe_initial_values_ice40(): - IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB2").verify() + IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB3").verify() diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py index 5ef1405..3bda812 100644 --- a/test/test_io_core_sim.py +++ b/test/test_io_core_sim.py @@ -1,57 +1,36 @@ +from amaranth import * from amaranth.sim import Simulator from manta.io_core import IOCore from manta.utils import * from random import randint -config = { - "type": "io", - "inputs": {"probe0": 1, "probe1": 2, "probe2": 8, "probe3": 20}, - "outputs": { - "probe4": {"width": 1, "initial_value": 1}, - "probe5": {"width": 2, "initial_value": 2}, - "probe6": 8, - "probe7": {"width": 20, "initial_value": 65538}, - }, -} +probe0 = Signal(1) +probe1 = Signal(2) +probe2 = Signal(8) +probe3 = Signal(20) +inputs = [probe0, probe1, probe2, probe3] -io_core = IOCore(config, base_addr=0, interface=None) +probe4 = Signal(1, reset=1) +probe5 = Signal(2, reset=2) +probe6 = Signal(8) +probe7 = Signal(20, reset=65538) +outputs = [probe4, probe5, probe6, probe7] + +io_core = IOCore(base_addr=0, interface=None, inputs=inputs, outputs=outputs) def pulse_strobe_register(): - strobe_addr = io_core.mmap["strobe"]["addrs"][0] + strobe_addr = io_core._memory_map["strobe"]["addrs"][0] yield from write_register(io_core, strobe_addr, 0) yield from write_register(io_core, strobe_addr, 1) yield from write_register(io_core, strobe_addr, 0) -def test_output_probe_initial_values(): - def testbench(): - # Verify all output probes initialize to the values in the config - for name, attrs in config["outputs"].items(): - initial_value = 0 - if isinstance(attrs, dict): - if "initial_value" in attrs: - initial_value = attrs["initial_value"] - - output_probe = getattr(io_core, name) - value = yield output_probe - - if value != initial_value: - raise ValueError( - f"Output probe {name} initialized to {value} instead of {initial_value}" - ) - - else: - print(f"Output probe {name} initialized to {value} as expected.") - - simulate(io_core, testbench) - - def test_input_probe_buffer_initial_value(): def testbench(): # Verify all input probe buffers initialize to zero - for name, width in config["inputs"].items(): - addrs = io_core.mmap[name + "_buf"]["addrs"] + for i in inputs: + addrs = io_core._memory_map[i.name]["addrs"] for addr in addrs: yield from verify_register(io_core, addr, 0) @@ -62,13 +41,9 @@ def test_input_probe_buffer_initial_value(): def test_output_probe_buffer_initial_value(): def testbench(): # Verify all output probe buffers initialize to the values in the config - for name, attrs in config["outputs"].items(): - addrs = io_core.mmap[name + "_buf"]["addrs"] - - datas = [0] * len(addrs) - if isinstance(attrs, dict): - if "initial_value" in attrs: - datas = value_to_words(attrs["initial_value"], len(addrs)) + for o in outputs: + addrs = io_core._memory_map[o.name]["addrs"] + datas = value_to_words(o.reset, len(addrs)) for addr, data in zip(addrs, datas): yield from verify_register(io_core, addr, data) @@ -78,14 +53,9 @@ def test_output_probe_buffer_initial_value(): def test_output_probes_are_writeable(): def testbench(): - for name, attrs in config["outputs"].items(): - if isinstance(attrs, dict): - width = attrs["width"] - else: - width = attrs - - addrs = io_core.mmap[name + "_buf"]["addrs"] - test_value = randint(0, (2**width) - 1) + for o in outputs: + addrs = io_core._memory_map[o.name]["addrs"] + test_value = randint(0, (2**o.width) - 1) datas = value_to_words(test_value, len(addrs)) # write value to registers @@ -101,14 +71,9 @@ def test_output_probes_are_writeable(): def test_output_probes_update(): def testbench(): - for name, attrs in config["outputs"].items(): - if isinstance(attrs, dict): - width = attrs["width"] - else: - width = attrs - - addrs = io_core.mmap[name + "_buf"]["addrs"] - test_value = randint(0, (2**width) - 1) + for o in outputs: + addrs = io_core._memory_map[o.name]["addrs"] + test_value = randint(0, (2**o.width) - 1) datas = value_to_words(test_value, len(addrs)) # write value to registers @@ -119,34 +84,31 @@ def test_output_probes_update(): yield from pulse_strobe_register() # check that outputs took updated value - output_probe = getattr(io_core, name) - value = yield (output_probe) + value = yield (o) if value != test_value: raise ValueError( - f"Output probe {name} took value {value} instead of {test_value} after pulsing strobe." + f"Output probe {o.name} took value {value} instead of {test_value} after pulsing strobe." ) else: - print(f"Output probe {name} took value {value} after pulsing strobe.") + print(f"Output probe {o.name} took value {value} after pulsing strobe.") simulate(io_core, testbench) def test_input_probes_update(): def testbench(): - for name, width in config["inputs"].items(): - test_value = randint(0, (2**width) - 1) - + for i in inputs: # set input probe value - input_probe = getattr(io_core, name) - yield input_probe.eq(test_value) + test_value = randint(0, (2**i.width) - 1) + yield i.eq(test_value) # pulse strobe register yield from pulse_strobe_register() # check that values are as expected once read back - addrs = io_core.mmap[name + "_buf"]["addrs"] + addrs = io_core._memory_map[i.name]["addrs"] datas = value_to_words(test_value, len(addrs)) for addr, data in zip(addrs, datas): From e2450ddbffcb7378d611ab38fa6da341ad858be1 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 18 Feb 2024 15:50:51 -0800 Subject: [PATCH 53/89] complete IO core refactor --- src/manta/io_core.py | 6 +- src/manta/logic_analyzer/__init__.py | 36 +++++---- src/manta/logic_analyzer/fsm.py | 83 ++++++++++--------- src/manta/logic_analyzer/trigger_block.py | 97 +++++++++++------------ test/test_io_core_hw.py | 2 +- test/test_logic_analyzer_fsm_sim.py | 72 ++++++++--------- test/test_logic_analyzer_sim.py | 13 ++- test/test_mem_core_hw.py | 23 +++++- test/test_uart_rx_sim.py | 4 +- test/test_uart_tx_sim.py | 4 +- 10 files changed, 179 insertions(+), 161 deletions(-) diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 648be7c..61bc5be 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -36,8 +36,8 @@ class IOCore(Elaboratable): @classmethod def from_config(cls, config, base_addr, interface): - inputs = config.get("inputs", []) - outputs = config.get("outputs", []) + inputs = config.get("inputs", {}) + outputs = config.get("outputs", {}) # Make sure IO core has at least one input or output if not inputs and not outputs: @@ -178,7 +178,7 @@ class IOCore(Elaboratable): Return the Amaranth signals that should be included as ports in the top-level Manta module. """ - return [self._inputs + self._outputs] + return self._inputs + self._outputs def get_max_addr(self): """ diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index b46a449..d88cbef 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -165,7 +165,7 @@ class LogicAnalyzerCore(Elaboratable): self.bus_o.eq(sample_mem.bus_o), # Non-bus Connections fsm.trigger.eq(trig_blk.trig), - sample_mem.user_addr.eq(fsm.r.write_pointer), + sample_mem.user_addr.eq(fsm.write_pointer), sample_mem.user_we.eq(fsm.write_enable), ] @@ -211,14 +211,14 @@ class LogicAnalyzerCore(Elaboratable): # If core is not in IDLE state, request that it return to IDLE print_if_verbose(" -> Resetting core...") - state = self.fsm.r.get_probe("state") + state = self.fsm.registers.get_probe("state") if state != States.IDLE: - self.fsm.r.set_probe("request_start", 0) - self.fsm.r.set_probe("request_stop", 0) - self.fsm.r.set_probe("request_stop", 1) - self.fsm.r.set_probe("request_stop", 0) + self.fsm.registers.set_probe("request_start", 0) + self.fsm.registers.set_probe("request_stop", 0) + self.fsm.registers.set_probe("request_stop", 1) + self.fsm.registers.set_probe("request_stop", 0) - if self.fsm.r.get_probe("state") != States.IDLE: + if self.fsm.registers.get_probe("state") != States.IDLE: raise ValueError("Logic analyzer did not reset to IDLE state.") # Set triggers @@ -232,28 +232,32 @@ class LogicAnalyzerCore(Elaboratable): print_if_verbose(" -> Setting trigger mode...") if "trigger_mode" in self.config: mode = self.config["trigger_mode"].upper() - self.fsm.r.set_probe("trigger_mode", TriggerModes[mode]) + self.fsm.registers.set_probe("trigger_mode", TriggerModes[mode]) else: - self.fsm.r.set_probe("trigger_mode", TriggerModes.SINGLE_SHOT) + self.fsm.registers.set_probe("trigger_mode", TriggerModes.SINGLE_SHOT) # Set trigger location print_if_verbose(" -> Setting trigger location...") if "trigger_location" in self.config: - self.fsm.r.set_probe("trigger_location", self.config["trigger_location"]) + self.fsm.registers.set_probe( + "trigger_location", self.config["trigger_location"] + ) else: - self.fsm.r.set_probe("trigger_location", self.config["sample_depth"] // 2) + self.fsm.registers.set_probe( + "trigger_location", self.config["sample_depth"] // 2 + ) # Send a start request to the state machine print_if_verbose(" -> Starting capture...") - self.fsm.r.set_probe("request_start", 0) - self.fsm.r.set_probe("request_start", 1) - self.fsm.r.set_probe("request_start", 0) + self.fsm.registers.set_probe("request_start", 0) + self.fsm.registers.set_probe("request_start", 1) + self.fsm.registers.set_probe("request_start", 0) # Poll the state machine's state, and wait for the capture to complete print_if_verbose(" -> Waiting for capture to complete...") - while self.fsm.r.get_probe("state") != States.CAPTURED: + while self.fsm.registers.get_probe("state") != States.CAPTURED: pass # Read out the entirety of the sample memory @@ -264,7 +268,7 @@ class LogicAnalyzerCore(Elaboratable): # Revolve the memory around the read_pointer, such that all the beginning # of the caputure is at the first element print_if_verbose(" -> Checking read pointer and revolving memory...") - read_pointer = self.fsm.r.get_probe("read_pointer") + read_pointer = self.fsm.registers.get_probe("read_pointer") data = raw_capture[read_pointer:] + raw_capture[:read_pointer] return LogicAnalyzerCapture(data, self.config) diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 461fa8b..cdf4b3c 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -26,29 +26,39 @@ class LogicAnalyzerFSM(Elaboratable): """ def __init__(self, config, base_addr, interface): - self.config = config + self._sample_depth = config["sample_depth"] + + # Outputs to rest of Logic Analyzer self.trigger = Signal(1) self.write_enable = Signal(1) - register_config = { - "inputs": { - "state": 4, - "read_pointer": ceil(log2(self.config["sample_depth"])), - "write_pointer": ceil(log2(self.config["sample_depth"])), - }, - "outputs": { - "trigger_location": ceil(log2(self.config["sample_depth"])), - "trigger_mode": 2, - "request_start": 1, - "request_stop": 1, - }, - } + # Outputs from FSM, inputs from IOCore + self.state = Signal(States) + self.read_pointer = Signal(range(self._sample_depth)) + self.write_pointer = Signal(range(self._sample_depth)) + inputs = [ + self.state, + self.read_pointer, + self.write_pointer, + ] - self.r = IOCore(register_config, base_addr, interface) + # Inputs to FSM, outputs from IOCore + self.trigger_location = Signal(range(self._sample_depth)) + self.trigger_mode = Signal(TriggerModes) + self.request_start = Signal() + self.request_stop = Signal() + outputs = [ + self.trigger_location, + self.trigger_mode, + self.request_start, + self.request_stop, + ] + + self.registers = IOCore(base_addr, interface, inputs, outputs) # Bus Input/Output - self.bus_i = self.r.bus_i - self.bus_o = self.r.bus_o + self.bus_i = self.registers.bus_i + self.bus_o = self.registers.bus_o def get_max_addr(self): """ @@ -56,38 +66,33 @@ class LogicAnalyzerFSM(Elaboratable): space used by the core extends from `base_addr` to the number returned by this function. """ - return self.r.get_max_addr() - - def increment_mod_sample_depth(self, m, signal): - # m.d.sync += signal.eq((signal + 1) % self.config["sample_depth"]) - - with m.If(signal == self.config["sample_depth"] - 1): - m.d.sync += signal.eq(0) - - with m.Else(): - m.d.sync += signal.eq(signal + 1) + return self.registers.get_max_addr() def elaborate(self, platform): m = Module() - m.submodules.registers = self.r + m.submodules.registers = self.registers - sample_depth = self.config["sample_depth"] - request_start = self.r.request_start - request_stop = self.r.request_stop - trigger_mode = self.r.trigger_mode - trigger_location = self.r.trigger_location - state = self.r.state + sample_depth = self._sample_depth + request_start = self.request_start + request_stop = self.request_stop + trigger_mode = self.trigger_mode + trigger_location = self.trigger_location + state = self.state write_enable = self.write_enable - write_pointer = self.r.write_pointer - read_pointer = self.r.read_pointer + write_pointer = self.write_pointer + read_pointer = self.read_pointer - prev_request_start = Signal(1) - prev_request_stop = Signal(1) + prev_request_start = Signal().like(request_start) + prev_request_stop = Signal().like(request_stop) + # Compute next_write_pointer as write_pointer + 1 % sample_depth next_write_pointer = Signal().like(write_pointer) + with m.If(write_pointer == self._sample_depth - 1): + m.d.comb += next_write_pointer.eq(0) - m.d.comb += next_write_pointer.eq((write_pointer + 1) % sample_depth) + with m.Else(): + m.d.comb += next_write_pointer.eq(write_pointer + 1) # Rising edge detection for start/stop requests m.d.sync += prev_request_start.eq(request_start) diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 487a9c4..652f5be 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -1,4 +1,5 @@ from amaranth import * +from amaranth.lib.enum import IntEnum from manta.io_core import IOCore @@ -12,23 +13,20 @@ class LogicAnalyzerTriggerBlock(Elaboratable): def __init__(self, probes, base_addr, interface): # Instantiate a bunch of trigger blocks - self.probes = probes - self.triggers = [LogicAnalyzerTrigger(p) for p in self.probes] + self._probes = probes + self._triggers = [LogicAnalyzerTrigger(p) for p in self._probes] # Make IO core for everything - outputs = {} - for p in self.probes: - outputs[p.name + "_arg"] = p.width - outputs[p.name + "_op"] = 4 - - self.r = IOCore({"outputs": outputs}, base_addr, interface) + ops = [t.op for t in self._triggers] + args = [t.arg for t in self._triggers] + self.registers = IOCore(base_addr, interface, outputs=ops + args) # Bus Input/Output - self.bus_i = self.r.bus_i - self.bus_o = self.r.bus_o + self.bus_i = self.registers.bus_i + self.bus_o = self.registers.bus_o # Global trigger. High if any probe is triggered. - self.trig = Signal(1) + self.trig = Signal() def get_max_addr(self): """ @@ -36,13 +34,13 @@ class LogicAnalyzerTriggerBlock(Elaboratable): space used by the core extends from `base_addr` to the number returned by this function. """ - return self.r.get_max_addr() + return self.registers.get_max_addr() def clear_triggers(self): # reset all triggers to disabled with no argument - for p in self.probes: - self.r.set_probe(p.name + "_op", 0) - self.r.set_probe(p.name + "_arg", 0) + for p in self._probes: + self.registers.set_probe(p.name + "_op", Operations.DISABLE) + self.registers.set_probe(p.name + "_arg", 0) def set_triggers(self, config): # set triggers @@ -52,34 +50,42 @@ class LogicAnalyzerTriggerBlock(Elaboratable): # Handle triggers that don't need an argument if len(components) == 2: name, op = components - self.r.set_probe(name + "_op", self.triggers[0].operations[op]) + self.registers.set_probe(name + "_op", Operations[op].value) # Handle triggers that do need an argument elif len(components) == 3: name, op, arg = components - self.r.set_probe(name + "_op", self.triggers[0].operations[op]) - self.r.set_probe(name + "_arg", int(arg)) + self.registers.set_probe(name + "_op", Operations[op].value) + self.registers.set_probe(name + "_arg", int(arg)) def elaborate(self, platform): m = Module() # Add IO Core as submodule - m.submodules.registers = self.r + m.submodules.registers = self.registers # Add triggers as submodules - for t in self.triggers: + for t in self._triggers: m.submodules[t.signal.name + "_trigger"] = t - # Connect IO core registers to triggers - for probe, trigger in zip(self.probes, self.triggers): - m.d.comb += trigger.arg.eq(getattr(self.r, probe.name + "_arg")) - m.d.comb += trigger.op.eq(getattr(self.r, probe.name + "_op")) - - m.d.comb += self.trig.eq(Cat([t.triggered for t in self.triggers]).any()) + m.d.comb += self.trig.eq(Cat([t.triggered for t in self._triggers]).any()) return m +class Operations(IntEnum): + DISABLE = 0 + RISING = 1 + FALLING = 2 + CHANGING = 3 + GT = 4 + LT = 5 + GEQ = 6 + LEQ = 7 + EQ = 8 + NEQ = 9 + + class LogicAnalyzerTrigger(Elaboratable): """ A module containing a programmable "trigger" for a given input signal, @@ -88,23 +94,10 @@ class LogicAnalyzerTrigger(Elaboratable): """ def __init__(self, signal): - self.operations = { - "DISABLE": 0, - "RISING": 1, - "FALLING": 2, - "CHANGING": 3, - "GT": 4, - "LT": 5, - "GEQ": 6, - "LEQ": 7, - "EQ": 8, - "NEQ": 9, - } - self.signal = signal - self.op = Signal(range(len(self.operations))) - self.arg = Signal().like(signal) - self.triggered = Signal(1) + self.op = Signal(Operations, name=signal.name + "_op") + self.arg = Signal(signal.width, name=signal.name + "_arg") + self.triggered = Signal() def elaborate(self, platform): m = Module() @@ -113,34 +106,34 @@ class LogicAnalyzerTrigger(Elaboratable): prev = Signal().like(self.signal) m.d.sync += prev.eq(self.signal) - with m.If(self.op == self.operations["DISABLE"]): + with m.If(self.op == Operations.DISABLE): m.d.comb += self.triggered.eq(0) - with m.Elif(self.op == self.operations["RISING"]): + with m.Elif(self.op == Operations.RISING): m.d.comb += self.triggered.eq(self.signal > prev) - with m.Elif(self.op == self.operations["FALLING"]): + with m.Elif(self.op == Operations.FALLING): m.d.comb += self.triggered.eq(self.signal < prev) - with m.Elif(self.op == self.operations["CHANGING"]): + with m.Elif(self.op == Operations.CHANGING): m.d.comb += self.triggered.eq(self.signal != prev) - with m.Elif(self.op == self.operations["GT"]): + with m.Elif(self.op == Operations.GT): m.d.comb += self.triggered.eq(self.signal > self.arg) - with m.Elif(self.op == self.operations["LT"]): + with m.Elif(self.op == Operations.LT): m.d.comb += self.triggered.eq(self.signal < self.arg) - with m.Elif(self.op == self.operations["GEQ"]): + with m.Elif(self.op == Operations.GEQ): m.d.comb += self.triggered.eq(self.signal >= self.arg) - with m.Elif(self.op == self.operations["LEQ"]): + with m.Elif(self.op == Operations.LEQ): m.d.comb += self.triggered.eq(self.signal <= self.arg) - with m.Elif(self.op == self.operations["EQ"]): + with m.Elif(self.op == Operations.EQ): m.d.comb += self.triggered.eq(self.signal == self.arg) - with m.Elif(self.op == self.operations["NEQ"]): + with m.Elif(self.op == Operations.NEQ): m.d.comb += self.triggered.eq(self.signal != self.arg) with m.Else(): diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 2c984f8..13f29c6 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -148,4 +148,4 @@ def test_output_probe_initial_values_xilinx(): @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_output_probe_initial_values_ice40(): - IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB3").verify() + IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB2").verify() diff --git a/test/test_logic_analyzer_fsm_sim.py b/test/test_logic_analyzer_fsm_sim.py index c2b4e70..7e7043c 100644 --- a/test/test_logic_analyzer_fsm_sim.py +++ b/test/test_logic_analyzer_fsm_sim.py @@ -9,12 +9,12 @@ fsm = LogicAnalyzerFSM(config, base_addr=0, interface=None) def test_signals_reset_correctly(): def testbench(): # Make sure pointers and write enable reset to zero - for sig in [fsm.r.write_pointer, fsm.r.read_pointer, fsm.write_enable]: + for sig in [fsm.write_pointer, fsm.read_pointer, fsm.write_enable]: if (yield sig) != 0: raise ValueError # Make sure state resets to IDLE - if (yield fsm.r.state != States.IDLE): + if (yield fsm.state != States.IDLE): raise ValueError simulate(fsm, testbench) @@ -24,9 +24,9 @@ def test_single_shot_no_wait_for_trigger(): def testbench(): # Configure and start FSM yield fsm.trigger.eq(1) - yield fsm.r.trigger_mode.eq(TriggerModes.SINGLE_SHOT) - yield fsm.r.trigger_location.eq(4) - yield fsm.r.request_start.eq(1) + yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.trigger_location.eq(4) + yield fsm.request_start.eq(1) # Wait until write_enable is asserted while not (yield fsm.write_enable): @@ -35,11 +35,11 @@ def test_single_shot_no_wait_for_trigger(): # Wait 8 clock cycles for capture to complete for i in range(8): # Make sure that read_pointer does not increase - if (yield fsm.r.read_pointer) != 0: + if (yield fsm.read_pointer) != 0: raise ValueError # Make sure that write_pointer increases by one each cycle - if (yield fsm.r.write_pointer) != i: + if (yield fsm.write_pointer) != i: raise ValueError yield @@ -48,11 +48,11 @@ def test_single_shot_no_wait_for_trigger(): yield # Check that write_pointer points to the end of memory - if (yield fsm.r.write_pointer) != 7: + if (yield fsm.write_pointer) != 7: raise ValueError # Check that state is CAPTURED - if (yield fsm.r.state) != States.CAPTURED: + if (yield fsm.state) != States.CAPTURED: raise ValueError simulate(fsm, testbench, "single_shot_no_wait_for_trigger.vcd") @@ -61,9 +61,9 @@ def test_single_shot_no_wait_for_trigger(): def test_single_shot_wait_for_trigger(): def testbench(): # Configure and start FSM - yield fsm.r.trigger_mode.eq(TriggerModes.SINGLE_SHOT) - yield fsm.r.trigger_location.eq(4) - yield fsm.r.request_start.eq(1) + yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.trigger_location.eq(4) + yield fsm.request_start.eq(1) yield yield @@ -73,8 +73,8 @@ def test_single_shot_wait_for_trigger(): # Wait 4 clock cycles to get to IN_POSITION for i in range(4): - rp = yield fsm.r.read_pointer - wp = yield fsm.r.write_pointer + rp = yield fsm.read_pointer + wp = yield fsm.write_pointer # Make sure that read_pointer does not increase if rp != 0: @@ -101,13 +101,13 @@ def test_single_shot_wait_for_trigger(): yield # Check that write_pointer points to the end of memory - rp = yield fsm.r.read_pointer - wp = yield fsm.r.write_pointer - if (wp + 1) % fsm.config["sample_depth"] != rp: + rp = yield fsm.read_pointer + wp = yield fsm.write_pointer + if (wp + 1) % config["sample_depth"] != rp: raise ValueError # Check that state is CAPTURED - if (yield fsm.r.state) != States.CAPTURED: + if (yield fsm.state) != States.CAPTURED: raise ValueError simulate(fsm, testbench, "single_shot_wait_for_trigger.vcd") @@ -116,8 +116,8 @@ def test_single_shot_wait_for_trigger(): def test_immediate(): def testbench(): # Configure and start FSM - yield fsm.r.trigger_mode.eq(TriggerModes.IMMEDIATE) - yield fsm.r.request_start.eq(1) + yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE) + yield fsm.request_start.eq(1) yield yield @@ -125,9 +125,9 @@ def test_immediate(): if not (yield fsm.write_enable): raise ValueError - for i in range(fsm.config["sample_depth"]): - rp = yield fsm.r.read_pointer - wp = yield fsm.r.write_pointer + for i in range(config["sample_depth"]): + rp = yield fsm.read_pointer + wp = yield fsm.write_pointer if rp != 0: raise ValueError @@ -141,15 +141,15 @@ def test_immediate(): yield # Check that write_pointer points to the end of memory - rp = yield fsm.r.read_pointer - wp = yield fsm.r.write_pointer + rp = yield fsm.read_pointer + wp = yield fsm.write_pointer if rp != 0: raise ValueError if wp != 7: raise ValueError # Check that state is CAPTURED - if (yield fsm.r.state) != States.CAPTURED: + if (yield fsm.state) != States.CAPTURED: raise ValueError simulate(fsm, testbench, "immediate.vcd") @@ -158,8 +158,8 @@ def test_immediate(): def test_incremental(): def testbench(): # Configure and start FSM - yield fsm.r.trigger_mode.eq(TriggerModes.INCREMENTAL) - yield fsm.r.request_start.eq(1) + yield fsm.trigger_mode.eq(TriggerModes.INCREMENTAL) + yield fsm.request_start.eq(1) yield yield @@ -177,7 +177,7 @@ def test_incremental(): yield # Check that state is CAPTURED - if (yield fsm.r.state) != States.CAPTURED: + if (yield fsm.state) != States.CAPTURED: raise ValueError simulate(fsm, testbench, "incremental.vcd") @@ -186,8 +186,8 @@ def test_incremental(): def test_single_shot_write_enable(): def testbench(): # Configure FSM - yield fsm.r.trigger_mode.eq(TriggerModes.SINGLE_SHOT) - yield fsm.r.trigger_location.eq(4) + yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.trigger_location.eq(4) yield # Make sure write is not enabled before starting the FSM @@ -195,11 +195,11 @@ def test_single_shot_write_enable(): raise ValueError # Start the FSM, ensure write enable is asserted throughout the capture - yield fsm.r.request_start.eq(1) + yield fsm.request_start.eq(1) yield yield - for _ in range(fsm.config["sample_depth"]): + for _ in range(config["sample_depth"]): if not (yield fsm.write_enable): raise ValueError @@ -224,7 +224,7 @@ def test_single_shot_write_enable(): def test_immediate_write_enable(): def testbench(): # Configure FSM - yield fsm.r.trigger_mode.eq(TriggerModes.IMMEDIATE) + yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE) yield # Make sure write is not enabled before starting the FSM @@ -232,11 +232,11 @@ def test_immediate_write_enable(): raise ValueError # Start the FSM, ensure write enable is asserted throughout the capture - yield fsm.r.request_start.eq(1) + yield fsm.request_start.eq(1) yield yield - for _ in range(fsm.config["sample_depth"]): + for _ in range(config["sample_depth"]): if not (yield fsm.write_enable): raise ValueError diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index ebce934..0346bd6 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -1,5 +1,6 @@ from amaranth.sim import Simulator from manta.logic_analyzer import LogicAnalyzerCore +from manta.logic_analyzer.trigger_block import Operations from manta.utils import * from random import sample @@ -32,8 +33,8 @@ def print_data_at_addr(addr): def set_fsm_register(name, data): - addr = la.fsm.r.mmap[f"{name}_buf"]["addrs"][0] - strobe_addr = la.fsm.r.base_addr + addr = la.fsm.registers._memory_map[name]["addrs"][0] + strobe_addr = la.fsm.registers._base_addr yield from write_register(la, strobe_addr, 0) yield from write_register(la, addr, data) @@ -42,8 +43,8 @@ def set_fsm_register(name, data): def set_trig_blk_register(name, data): - addr = la.trig_blk.r.mmap[f"{name}_buf"]["addrs"][0] - strobe_addr = la.trig_blk.r.base_addr + addr = la.trig_blk.registers._memory_map[name]["addrs"][0] + strobe_addr = la.trig_blk.registers._base_addr yield from write_register(la, strobe_addr, 0) yield from write_register(la, addr, data) @@ -67,9 +68,7 @@ def test_single_shot_capture(): yield from set_fsm_register("request_stop", 0) # setting triggers - yield from set_trig_blk_register( - "curly_op", la.trig_blk.triggers[0].operations["EQ"] - ) + yield from set_trig_blk_register("curly_op", Operations.EQ) yield from set_trig_blk_register("curly_arg", 4) # setting trigger mode diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index e9c0710..78bd024 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -48,16 +48,33 @@ class MemoryCoreLoopbackTest(Elaboratable): }, } + def get_probe(self, name): + # This is a hack! And should be removed once the full Amaranth-native + # API is built out + for i in self.manta.io_core._inputs: + if i.name == name: + return i + + for o in self.manta.io_core._outputs: + if o.name == name: + return o + + return None + def elaborate(self, platform): m = Module() m.submodules.manta = self.manta uart_pins = platform.request("uart") + addr = self.get_probe("addr") + data = self.get_probe("data") + we = self.get_probe("we") + m.d.comb += [ - self.manta.mem_core.user_addr.eq(self.manta.io_core.addr), - self.manta.mem_core.user_data.eq(self.manta.io_core.data), - self.manta.mem_core.user_we.eq(self.manta.io_core.we), + self.manta.mem_core.user_addr.eq(addr), + self.manta.mem_core.user_data.eq(data), + self.manta.mem_core.user_we.eq(we), self.manta.interface.rx.eq(uart_pins.rx.i), uart_pins.tx.o.eq(self.manta.interface.tx), ] diff --git a/test/test_uart_rx_sim.py b/test/test_uart_rx_sim.py index 3604591..40111aa 100644 --- a/test/test_uart_rx_sim.py +++ b/test/test_uart_rx_sim.py @@ -14,8 +14,8 @@ def verify_receive(data): valid_asserted_before = False - for i in range(10 * uart_rx.clocks_per_baud): - bit_index = i // uart_rx.clocks_per_baud + for i in range(10 * uart_rx._clocks_per_baud): + bit_index = i // uart_rx._clocks_per_baud # Every cycle, run checks on uart_rx: if (yield uart_rx.valid_o): diff --git a/test/test_uart_tx_sim.py b/test/test_uart_tx_sim.py index c78d076..8b07aa4 100644 --- a/test/test_uart_tx_sim.py +++ b/test/test_uart_tx_sim.py @@ -26,8 +26,8 @@ def verify_bit_sequence(byte): data_bits = "0" + f"{byte:08b}"[::-1] + "1" data_bits = [int(bit) for bit in data_bits] - for i in range(10 * uart_tx.clocks_per_baud): - bit_index = i // uart_tx.clocks_per_baud + for i in range(10 * uart_tx._clocks_per_baud): + bit_index = i // uart_tx._clocks_per_baud if (yield uart_tx.tx) != data_bits[bit_index]: raise ValueError("Wrong bit in sequence!") From 7ee51158d2dea2be309cc67ae14094a6944ff93e Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 19 Feb 2024 11:23:11 -0800 Subject: [PATCH 54/89] enforce consistent docstrings and underscores in logic analyzer core --- .gitignore | 1 + src/manta/logic_analyzer/__init__.py | 288 ++++++++++++--------------- src/manta/logic_analyzer/playback.py | 9 +- test/test_logic_analyzer_hw.py | 11 +- 4 files changed, 138 insertions(+), 171 deletions(-) diff --git a/.gitignore b/.gitignore index 5dc2efa..48226f2 100644 --- a/.gitignore +++ b/.gitignore @@ -14,6 +14,7 @@ build/ *.sv *.vcd *.out +*.csv # Vivado files from the occasional debugging sesh *.log diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index d88cbef..20a8ef8 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -19,27 +19,27 @@ class LogicAnalyzerCore(Elaboratable): """ def __init__(self, config, base_addr, interface): - self.config = config - self.check_config(config) + self._config = config + self._check_config() # Bus Input/Output self.bus_i = Signal(InternalBus()) self.bus_o = Signal(InternalBus()) - self.probes = [ - Signal(width, name=name) for name, width in self.config["probes"].items() + self._probes = [ + Signal(width, name=name) for name, width in self._config["probes"].items() ] # Submodules - self.fsm = LogicAnalyzerFSM(self.config, base_addr, interface) - self.trig_blk = LogicAnalyzerTriggerBlock( - self.probes, self.fsm.get_max_addr() + 1, interface + self._fsm = LogicAnalyzerFSM(self._config, base_addr, interface) + self._trig_blk = LogicAnalyzerTriggerBlock( + self._probes, self._fsm.get_max_addr() + 1, interface ) - self.sample_mem = LogicAnalyzerSampleMemory( - self.config, self.trig_blk.get_max_addr() + 1, interface + self._sample_mem = LogicAnalyzerSampleMemory( + self._config, self._trig_blk.get_max_addr() + 1, interface ) - def check_config(self, config): + def _check_config(self): # Check for unrecognized options valid_options = [ "type", @@ -49,12 +49,12 @@ class LogicAnalyzerCore(Elaboratable): "trigger_location", "trigger_mode", ] - for option in config: + for option in self._config: if option not in valid_options: warn(f"Ignoring unrecognized option '{option}' in Logic Analyzer.") # Check sample depth is provided and positive - sample_depth = config.get("sample_depth") + sample_depth = self._config.get("sample_depth") if not sample_depth: raise ValueError("Logic Analyzer must have sample_depth specified.") @@ -62,35 +62,35 @@ class LogicAnalyzerCore(Elaboratable): raise ValueError("Logic Analyzer sample_depth must be a positive integer.") # Check probes - if "probes" not in config or len(config["probes"]) == 0: + if "probes" not in self._config or len(self._config["probes"]) == 0: raise ValueError("Logic Analyzer must have at least one probe specified.") - for name, width in config["probes"].items(): + for name, width in self._config["probes"].items(): if width < 0: raise ValueError(f"Width of probe {name} must be positive.") # Check trigger mode, if provided - trigger_mode = config.get("trigger_mode") + trigger_mode = self._config.get("trigger_mode") valid_modes = ["single_shot", "incremental", "immediate"] if trigger_mode and trigger_mode not in valid_modes: raise ValueError( - f"Unrecognized trigger mode {config['trigger_mode']} provided." + f"Unrecognized trigger mode {self._config['trigger_mode']} provided." ) # Check triggers if trigger_mode and trigger_mode != "immediate": - if "triggers" not in config or config["triggers"] == 0: + if "triggers" not in self._config or self._config["triggers"] == 0: raise ValueError( "Logic Analyzer must have at least one trigger specified if not running in immediate mode." ) # Check trigger location - trigger_location = config.get("trigger_location") + trigger_location = self._config.get("trigger_location") if trigger_location: if not isinstance(trigger_location, int) or trigger_location < 0: raise ValueError("Trigger location must be a positive integer.") - if trigger_location >= config["sample_depth"]: + if trigger_location >= self._config["sample_depth"]: raise ValueError("Trigger location must be less than sample depth.") if trigger_mode == "immediate": @@ -100,16 +100,16 @@ class LogicAnalyzerCore(Elaboratable): # Check triggers themselves if trigger_mode == "immediate": - if "triggers" in config: + if "triggers" in self._config: warn( "Ignoring triggers as 'trigger_mode' is set to immediate, and there are no triggers to specify." ) else: - if ("triggers" not in config) or (len(config["triggers"]) == 0): + if ("triggers" not in self._config) or (len(self._config["triggers"]) == 0): raise ValueError("At least one trigger must be specified.") - for trigger in config.get("triggers"): + for trigger in self._config.get("triggers"): if not isinstance(trigger, str): raise ValueError("Trigger must be specified with a string.") @@ -140,33 +140,33 @@ class LogicAnalyzerCore(Elaboratable): ) # Check probe names - if components[0] not in config["probes"]: + if components[0] not in self._config["probes"]: raise ValueError(f"Unknown probe name '{components[0]}' specified.") def elaborate(self, platform): m = Module() # Add submodules - m.submodules.fsm = fsm = self.fsm - m.submodules.sample_mem = sample_mem = self.sample_mem - m.submodules.trig_blk = trig_blk = self.trig_blk + m.submodules.fsm = self._fsm + m.submodules.sample_mem = self._sample_mem + m.submodules.trig_blk = self._trig_blk # Concat all the probes together, and feed to input of sample memory # (it is necessary to reverse the order such that first probe occupies # the lowest location in memory) - m.d.comb += sample_mem.user_data.eq(Cat(self.probes[::-1])) + m.d.comb += self._sample_mem.user_data.eq(Cat(self._probes[::-1])) # Wire bus connections between internal modules m.d.comb += [ # Bus Connections - fsm.bus_i.eq(self.bus_i), - trig_blk.bus_i.eq(self.fsm.bus_o), - sample_mem.bus_i.eq(trig_blk.bus_o), - self.bus_o.eq(sample_mem.bus_o), + self._fsm.bus_i.eq(self.bus_i), + self._trig_blk.bus_i.eq(self._fsm.bus_o), + self._sample_mem.bus_i.eq(self._trig_blk.bus_o), + self.bus_o.eq(self._sample_mem.bus_o), # Non-bus Connections - fsm.trigger.eq(trig_blk.trig), - sample_mem.user_addr.eq(fsm.write_pointer), - sample_mem.user_we.eq(fsm.write_enable), + self._fsm.trigger.eq(self._trig_blk.trig), + self._sample_mem.user_addr.eq(self._fsm.write_pointer), + self._sample_mem.user_we.eq(self._fsm.write_enable), ] return m @@ -176,14 +176,7 @@ class LogicAnalyzerCore(Elaboratable): Return the Amaranth signals that should be included as ports in the top-level Manta module. """ - return self.probes - - def get_probe(self, name): - for p in self.probes: - if p.name == name: - return p - - raise ValueError(f"Probe '{name}' not found in Logic Analyzer core.") + return self._probes def get_max_addr(self): """ @@ -191,167 +184,150 @@ class LogicAnalyzerCore(Elaboratable): space used by the core extends from `base_addr` to the number returned by this function. """ - return self.sample_mem.get_max_addr() + return self._sample_mem.get_max_addr() def capture(self, verbose=False): - """Perform a capture, recording the state of all input probes to the FPGA's memory, and - then reading that out on the host. - - Parameters: - ---------- - verbose : bool - Whether or not to print the status of the capture to stdout as it progresses. - Defaults to False. - - Returns: - ---------- - An instance of LogicAnalyzerCapture. + """ + Performs a capture, recording the state of all input probes to the + FPGA's memory, and then returns that as a LogicAnalyzerCapture class + on the host. """ print_if_verbose = lambda x: print(x) if verbose else None # If core is not in IDLE state, request that it return to IDLE print_if_verbose(" -> Resetting core...") - state = self.fsm.registers.get_probe("state") + state = self._fsm.registers.get_probe("state") if state != States.IDLE: - self.fsm.registers.set_probe("request_start", 0) - self.fsm.registers.set_probe("request_stop", 0) - self.fsm.registers.set_probe("request_stop", 1) - self.fsm.registers.set_probe("request_stop", 0) + self._fsm.registers.set_probe("request_start", 0) + self._fsm.registers.set_probe("request_stop", 0) + self._fsm.registers.set_probe("request_stop", 1) + self._fsm.registers.set_probe("request_stop", 0) - if self.fsm.registers.get_probe("state") != States.IDLE: + if self._fsm.registers.get_probe("state") != States.IDLE: raise ValueError("Logic analyzer did not reset to IDLE state.") # Set triggers print_if_verbose(" -> Setting triggers...") - self.trig_blk.clear_triggers() + self._trig_blk.clear_triggers() - if self.config.get("trigger_mode") != "immediate": - self.trig_blk.set_triggers(self.config) + if self._config.get("trigger_mode") != "immediate": + self._trig_blk.set_triggers(self._config) # Set trigger mode, default to single-shot if user didn't specify a mode print_if_verbose(" -> Setting trigger mode...") - if "trigger_mode" in self.config: - mode = self.config["trigger_mode"].upper() - self.fsm.registers.set_probe("trigger_mode", TriggerModes[mode]) + if "trigger_mode" in self._config: + mode = self._config["trigger_mode"].upper() + self._fsm.registers.set_probe("trigger_mode", TriggerModes[mode]) else: - self.fsm.registers.set_probe("trigger_mode", TriggerModes.SINGLE_SHOT) + self._fsm.registers.set_probe("trigger_mode", TriggerModes.SINGLE_SHOT) # Set trigger location print_if_verbose(" -> Setting trigger location...") - if "trigger_location" in self.config: - self.fsm.registers.set_probe( - "trigger_location", self.config["trigger_location"] + if "trigger_location" in self._config: + self._fsm.registers.set_probe( + "trigger_location", self._config["trigger_location"] ) else: - self.fsm.registers.set_probe( - "trigger_location", self.config["sample_depth"] // 2 + self._fsm.registers.set_probe( + "trigger_location", self._config["sample_depth"] // 2 ) # Send a start request to the state machine print_if_verbose(" -> Starting capture...") - self.fsm.registers.set_probe("request_start", 0) - self.fsm.registers.set_probe("request_start", 1) - self.fsm.registers.set_probe("request_start", 0) + self._fsm.registers.set_probe("request_start", 0) + self._fsm.registers.set_probe("request_start", 1) + self._fsm.registers.set_probe("request_start", 0) # Poll the state machine's state, and wait for the capture to complete print_if_verbose(" -> Waiting for capture to complete...") - while self.fsm.registers.get_probe("state") != States.CAPTURED: + while self._fsm.registers.get_probe("state") != States.CAPTURED: pass # Read out the entirety of the sample memory print_if_verbose(" -> Reading sample memory contents...") - addrs = list(range(self.config["sample_depth"])) - raw_capture = self.sample_mem.read_from_user_addr(addrs) + addrs = list(range(self._config["sample_depth"])) + raw_capture = self._sample_mem.read_from_user_addr(addrs) # Revolve the memory around the read_pointer, such that all the beginning # of the caputure is at the first element print_if_verbose(" -> Checking read pointer and revolving memory...") - read_pointer = self.fsm.registers.get_probe("read_pointer") + read_pointer = self._fsm.registers.get_probe("read_pointer") data = raw_capture[read_pointer:] + raw_capture[:read_pointer] - return LogicAnalyzerCapture(data, self.config) + return LogicAnalyzerCapture(data, self._config) class LogicAnalyzerCapture: - """A container for the data collected during a capture from a LogicAnalyzerCore. Contains - methods for exporting the data as a VCD waveform file, or as a Verilog module for playing - back captured data in simulation/synthesis. - - Parameters: - ---------- - data : list[int] - The raw captured data taken by the LogicAnalyzerCore. This consists of the values of - all the input probes concatenated together at every timestep. - - config : dict - The configuration of the LogicAnalyzerCore that took this capture. + """ + A container class for the data collected by a LogicAnalyzerCore. Contains + methods for exporting the data as a VCD waveform file, a Python list, a + CSV file, or a Verilog module. """ def __init__(self, data, config): - self.data = data - self.config = config + self._data = data + self._config = config def get_trigger_location(self): - """Gets the location of the trigger in the capture. This will match the value of - "trigger_location" provided in the configuration file at the time of capture. - - Parameters: - ---------- - None - - Returns: - ---------- - The trigger location as an `int`. """ - if "trigger_location" in self.config: - return self.config["trigger_location"] + Gets the location of the trigger in the capture. This will match the + value of "trigger_location" provided in the configuration file at the + time of capture. + """ + + if "trigger_location" in self._config: + return self._config["trigger_location"] else: - return self.config["sample_depth"] // 2 + return self._config["sample_depth"] // 2 def get_trace(self, probe_name): - """Gets the value of a single probe over the capture. - - Parameters: - ---------- - probe_name : int - The name of the probe in the LogicAnalyzer Core. This must match the name provided - in the configuration file. - - Returns: - ---------- - The value of the probe at every timestep in the capture, as a list of integers. + """ + Gets the value of a single probe over the capture. """ # sum up the widths of all the probes below this one lower = 0 - for name, width in self.config["probes"].items(): + for name, width in self._config["probes"].items(): if name == probe_name: break lower += width # add the width of the probe we'd like - upper = lower + self.config["probes"][probe_name] + upper = lower + self._config["probes"][probe_name] - total_probe_width = sum(self.config["probes"].values()) - binary = [f"{d:0{total_probe_width}b}" for d in self.data] + total_probe_width = sum(self._config["probes"].values()) + binary = [f"{d:0{total_probe_width}b}" for d in self._data] return [int(b[lower:upper], 2) for b in binary] + def export_csv(self, path): + """ + Export the capture to a CSV file, containing the data of all probes in + the core. + """ + + names = list(self._config["probes"].keys()) + values = [self.get_trace(n) for n in names] + + # Transpose list of lists so that data flows top-to-bottom instead of + # left-to-right + values_t = [list(x) for x in zip(*values)] + + import csv + with open(path, 'w') as f: + writer = csv.writer(f) + + writer.writerow(names) + writer.writerows(values_t) + + def export_vcd(self, path): - """Export the capture to a VCD file, containing the data of all probes in the core. - - Parameters: - ---------- - path : str - The path of the output file, including the ".vcd" file extension. - - Returns: - ---------- - None - + """ + Export the capture to a VCD file, containing the data of all probes in + the core. """ from vcd import VCDWriter @@ -364,7 +340,7 @@ class LogicAnalyzerCapture: with VCDWriter(vcd_file, "10 ns", timestamp, "manta") as writer: # each probe has a name, width, and writer associated with it signals = [] - for name, width in self.config["probes"].items(): + for name, width in self._config["probes"].items(): signal = { "name": name, "width": width, @@ -377,20 +353,20 @@ class LogicAnalyzerCapture: # include a trigger signal such would be meaningful (ie, we didn't trigger immediately) if ( - "trigger_mode" not in self.config - or self.config["trigger_mode"] == "single_shot" + "trigger_mode" not in self._config + or self._config["trigger_mode"] == "single_shot" ): trigger = writer.register_var("manta", "trigger", "wire", size=1) # add the data to each probe in the vcd file - for timestamp in range(0, 2 * len(self.data)): + for timestamp in range(0, 2 * len(self._data)): # run the clock writer.change(clock, timestamp, timestamp % 2 == 0) # set the trigger (if there is one) if ( - "trigger_mode" not in self.config - or self.config["trigger_mode"] == "single_shot" + "trigger_mode" not in self._config + or self._config["trigger_mode"] == "single_shot" ): triggered = (timestamp // 2) >= self.get_trigger_location() writer.change(trigger, timestamp, triggered) @@ -405,31 +381,19 @@ class LogicAnalyzerCapture: vcd_file.close() def get_playback_module(self): - """Gets an Amaranth module that will playback the captured data. This module is - synthesizable, so it may be used in either simulation or synthesis. - - Parameters: - ---------- - None - - Returns: - ---------- - An instance of LogicAnalyzerPlayback, which is a synthesizable Amaranth module. """ - return LogicAnalyzerPlayback(self.data, self.config) + Returns an Amaranth module that will playback the captured data. This + module is synthesizable, so it may be used in either simulation or + on the FPGA directly by including it your build process. + """ + + return LogicAnalyzerPlayback(self._data, self._config) def export_playback_verilog(self, path): - """Exports a Verilog module that will playback the captured data. This module is - synthesizable, so it may be used in either simulation or synthesis. - - Parameters: - ---------- - path : str - The path of the output file, including the ".v" file extension. - - Returns: - ---------- - None + """ + Exports a Verilog module that will playback the captured data. This + module is synthesizable, so it may be used in either simulation or + on the FPGA directly by including it your build process. """ lap = self.get_playback_module() diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index 3fc72e4..5ddb6d9 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -3,10 +3,9 @@ from amaranth import * class LogicAnalyzerPlayback(Elaboratable): """ - A synthesizable module that plays back data captured by a LogicAnalyzerCore. - - Takes a list of all the samples captured by a core, along with the config - of the core used to take it. + A synthesizable module that plays back data captured by a + LogicAnalyzerCore. Takes a list of all the samples captured by a core, + along with the config of the core used to take it. """ def __init__(self, data, config): @@ -73,7 +72,7 @@ class LogicAnalyzerPlayback(Elaboratable): def get_top_level_ports(self): """ - Return the Amaranth signals that should be included as ports in the + Returns the Amaranth signals that should be included as ports in the exported Verilog module. """ return [self.start, self.valid] + list(self.top_level_probes.values()) diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 12e8c41..d1dd695 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -36,9 +36,9 @@ class LogicAnalyzerCounterTest(Elaboratable): m.submodules.manta = self.manta uart_pins = platform.request("uart") - larry = self.manta.la.probes[0] - curly = self.manta.la.probes[1] - moe = self.manta.la.probes[2] + larry = self.manta.la._probes[0] + curly = self.manta.la._probes[1] + moe = self.manta.la._probes[2] m.d.sync += larry.eq(larry + 1) m.d.sync += curly.eq(curly + 1) @@ -61,11 +61,14 @@ class LogicAnalyzerCounterTest(Elaboratable): # check that VCD export works cap.export_vcd("out.vcd") + # check that CSV export works + cap.export_csv("out.csv") + # check that Verilog export works cap.export_playback_verilog("out.v") # verify that each signal is just a counter modulo the width of the signal - for name, width in self.manta.la.config["probes"].items(): + for name, width in self.manta.la._config["probes"].items(): trace = cap.get_trace(name) for i in range(len(trace) - 1): From b0dcd269bcb7e57cfadbec733acdf389276165b3 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 19 Feb 2024 11:42:28 -0800 Subject: [PATCH 55/89] add from_config to memory_core --- src/manta/logic_analyzer/__init__.py | 14 +++++--- src/manta/logic_analyzer/sample_mem.py | 16 --------- src/manta/manta.py | 2 +- src/manta/memory_core.py | 47 ++++++++++---------------- test/test_logic_analyzer_sim.py | 10 +++--- test/test_mem_core_sim.py | 3 +- 6 files changed, 33 insertions(+), 59 deletions(-) delete mode 100644 src/manta/logic_analyzer/sample_mem.py diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 20a8ef8..1ffe387 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -1,8 +1,8 @@ from amaranth import * from manta.utils import * +from manta.memory_core import ReadOnlyMemoryCore from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock from manta.logic_analyzer.fsm import LogicAnalyzerFSM, States, TriggerModes -from manta.logic_analyzer.sample_mem import LogicAnalyzerSampleMemory from manta.logic_analyzer.playback import LogicAnalyzerPlayback @@ -35,8 +35,12 @@ class LogicAnalyzerCore(Elaboratable): self._trig_blk = LogicAnalyzerTriggerBlock( self._probes, self._fsm.get_max_addr() + 1, interface ) - self._sample_mem = LogicAnalyzerSampleMemory( - self._config, self._trig_blk.get_max_addr() + 1, interface + + self._sample_mem = ReadOnlyMemoryCore( + width=sum(self._config["probes"].values()), + depth=self._config["sample_depth"], + base_addr=self._trig_blk.get_max_addr() + 1, + interface=interface, ) def _check_config(self): @@ -317,13 +321,13 @@ class LogicAnalyzerCapture: values_t = [list(x) for x in zip(*values)] import csv - with open(path, 'w') as f: + + with open(path, "w") as f: writer = csv.writer(f) writer.writerow(names) writer.writerows(values_t) - def export_vcd(self, path): """ Export the capture to a VCD file, containing the data of all probes in diff --git a/src/manta/logic_analyzer/sample_mem.py b/src/manta/logic_analyzer/sample_mem.py deleted file mode 100644 index 045fabb..0000000 --- a/src/manta/logic_analyzer/sample_mem.py +++ /dev/null @@ -1,16 +0,0 @@ -from amaranth import * -from manta.memory_core import ReadOnlyMemoryCore - - -class LogicAnalyzerSampleMemory(ReadOnlyMemoryCore): - """ - A module that wraps a ReadOnlyMemoryCore, using the config from a LogicAnalyzerCore - to determine the parameters with which to instantiate the core. - """ - - def __init__(self, config, base_addr, interface): - width = sum(config["probes"].values()) - depth = config["sample_depth"] - mem_config = {"width": width, "depth": depth} - - super().__init__(mem_config, base_addr, interface) diff --git a/src/manta/manta.py b/src/manta/manta.py index 9384957..5dca676 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -84,7 +84,7 @@ class Manta(Elaboratable): core = LogicAnalyzerCore(attrs, base_addr, self.interface) elif attrs["type"] == "memory_read_only": - core = ReadOnlyMemoryCore(attrs, base_addr, self.interface) + core = ReadOnlyMemoryCore.from_config(attrs, base_addr, self.interface) # make sure we're not out of address space if core.get_max_addr() > (2**16) - 1: diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 6d92ee4..6bc3681 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -15,14 +15,12 @@ class ReadOnlyMemoryCore(Elaboratable): https://fischermoseley.github.io/manta/memory_core/ """ - def __init__(self, config, base_addr, interface): - self._config = config + def __init__(self, width, depth, base_addr, interface): + self._width = width + self._depth = depth self._base_addr = base_addr self._interface = interface - self._check_config(config) - self._depth = self._config["depth"] - self._width = self._config["width"] self._max_addr = self._base_addr + (self._depth * ceil(self._width / 16)) # Bus Connections @@ -36,7 +34,8 @@ class ReadOnlyMemoryCore(Elaboratable): self._define_mems() - def _check_config(self, config): + @classmethod + def from_config(cls, config, base_addr, interface): # Check for unrecognized options valid_options = ["type", "depth", "width"] for option in config: @@ -44,25 +43,29 @@ class ReadOnlyMemoryCore(Elaboratable): warn(f"Ignoring unrecognized option '{option}' in memory core.") # Check depth is provided and positive - if "depth" not in config: + depth = config.get("depth") + if not depth: raise ValueError("Depth of memory core must be specified.") - if not isinstance(config["depth"], int): + if not isinstance(depth, int): raise ValueError("Depth of memory core must be an integer.") - if config["depth"] <= 0: + if not depth > 0: raise ValueError("Depth of memory core must be positive. ") # Check width is provided and positive - if "width" not in config: + width = config.get("width") + if not width: raise ValueError("Width of memory core must be specified.") - if not isinstance(config["width"], int): + if not isinstance(width, int): raise ValueError("Width of memory core must be an integer.") - if config["width"] <= 0: + if not width > 0: raise ValueError("Width of memory core must be positive. ") + cls(width, depth, base_addr, interface) + def _pipeline_bus(self, m): self._bus_pipe = [Signal(InternalBus()) for _ in range(3)] m.d.sync += self._bus_pipe[0].eq(self.bus_i) @@ -160,7 +163,8 @@ class ReadOnlyMemoryCore(Elaboratable): def read_from_user_addr(self, addrs): """ - Read the memory stored at the provided address, as seen from the user side. + Read the memory stored at the provided address, as seen from the user + side. """ # Convert user address space to bus address space @@ -180,20 +184,3 @@ class ReadOnlyMemoryCore(Elaboratable): datas = self._interface.read(bus_addrs) data_chunks = split_into_chunks(datas, len(self._mems)) return [words_to_value(chunk) for chunk in data_chunks] - - # def write_to_user_addr(self, addrs, datas): - # """ - # Read from the address - # """ - - # bus_addrs = [] - # for addr in addrs: - # bus_addrs += [ - # addr + self._base_addr + i * self._depth for i in range(len(self._mems)) - # ] - - # bus_datas = [] - # for data in datas: - # bus_datas += value_to_words(data) - - # self._interface.write(bus_addrs, bus_datas) diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index 0346bd6..f5c7ea2 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -33,8 +33,8 @@ def print_data_at_addr(addr): def set_fsm_register(name, data): - addr = la.fsm.registers._memory_map[name]["addrs"][0] - strobe_addr = la.fsm.registers._base_addr + addr = la._fsm.registers._memory_map[name]["addrs"][0] + strobe_addr = la._fsm.registers._base_addr yield from write_register(la, strobe_addr, 0) yield from write_register(la, addr, data) @@ -43,8 +43,8 @@ def set_fsm_register(name, data): def set_trig_blk_register(name, data): - addr = la.trig_blk.registers._memory_map[name]["addrs"][0] - strobe_addr = la.trig_blk.registers._base_addr + addr = la._trig_blk.registers._memory_map[name]["addrs"][0] + strobe_addr = la._trig_blk.registers._base_addr yield from write_register(la, strobe_addr, 0) yield from write_register(la, addr, data) @@ -54,7 +54,7 @@ def set_trig_blk_register(name, data): def set_probe(name, value): probe = None - for p in la.probes: + for p in la._probes: if p.name == name: probe = p diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 675991f..e793c4f 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -15,8 +15,7 @@ def fill_mem_from_user_port(mem_core, depth): def verify_mem_core(width, depth, base_addr): - config = {"type": "memory", "width": width, "depth": depth} - mem_core = ReadOnlyMemoryCore(config, base_addr, interface=None) + mem_core = ReadOnlyMemoryCore(width, depth, base_addr, interface=None) def testbench(): yield from fill_mem_from_user_port(mem_core, depth) From ca7d743bf45009d923e17ac2cdbc13a2d70a863f Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 19 Feb 2024 12:15:19 -0800 Subject: [PATCH 56/89] move to private methods in Manta class --- src/manta/cli.py | 2 +- src/manta/ethernet/source_bridge.py | 2 +- src/manta/io_core.py | 4 +- src/manta/logic_analyzer/__init__.py | 16 ++--- src/manta/logic_analyzer/trigger_block.py | 4 +- src/manta/manta.py | 82 ++++++++++++----------- src/manta/memory_core.py | 2 +- src/manta/utils.py | 10 +-- 8 files changed, 62 insertions(+), 60 deletions(-) diff --git a/src/manta/cli.py b/src/manta/cli.py index c65a167..2ae2f3a 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -113,7 +113,7 @@ def ports(): for port in serial.tools.list_ports.comports(): print(port) - # sometimes macOS will enumerate non-serial devices as serial ports, + # Sometimes macOS will enumerate non-serial devices as serial ports, # in which case the PID/VID/serial/location/etc are all None pid = f"0x{port.pid:04X}" if port.pid is not None else "None" vid = f"0x{port.vid:04X}" if port.vid is not None else "None" diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py index 91b7fbc..4ed8765 100644 --- a/src/manta/ethernet/source_bridge.py +++ b/src/manta/ethernet/source_bridge.py @@ -19,7 +19,7 @@ class UDPSourceBridge(Elaboratable): def elaborate(self, platform): m = Module() - state = Signal() # can either be 0, for read/write, or 1, for data + state = Signal() # Can either be 0, for read/write, or 1, for data rw_buf = Signal().like(self.bus_o.rw) # Can always take more data diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 61bc5be..ff633a6 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -84,13 +84,13 @@ class IOCore(Elaboratable): initial_value = 0 if isinstance(attrs, dict): - # check that each output probe has only recognized options + # Check that each output probe has only recognized options valid_options = ["width", "initial_value"] for option in attrs: if option not in valid_options: warn(f'Ignoring unrecognized option "{option}" in IO core.') - # check that widths are appropriate + # Check that widths are appropriate if "width" not in attrs: raise ValueError(f"No width specified for output probe {name}.") diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 1ffe387..62dc8c6 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -292,7 +292,7 @@ class LogicAnalyzerCapture: Gets the value of a single probe over the capture. """ - # sum up the widths of all the probes below this one + # Sum up the widths of all the probes below this one lower = 0 for name, width in self._config["probes"].items(): if name == probe_name: @@ -300,7 +300,7 @@ class LogicAnalyzerCapture: lower += width - # add the width of the probe we'd like + # Add the width of the probe we'd like upper = lower + self._config["probes"][probe_name] total_probe_width = sum(self._config["probes"].values()) @@ -342,7 +342,7 @@ class LogicAnalyzerCapture: vcd_file = open(path, "w") with VCDWriter(vcd_file, "10 ns", timestamp, "manta") as writer: - # each probe has a name, width, and writer associated with it + # Each probe has a name, width, and writer associated with it signals = [] for name, width in self._config["probes"].items(): signal = { @@ -355,19 +355,19 @@ class LogicAnalyzerCapture: clock = writer.register_var("manta", "clk", "wire", size=1) - # include a trigger signal such would be meaningful (ie, we didn't trigger immediately) + # Include a trigger signal such would be meaningful (ie, we didn't trigger immediately) if ( "trigger_mode" not in self._config or self._config["trigger_mode"] == "single_shot" ): trigger = writer.register_var("manta", "trigger", "wire", size=1) - # add the data to each probe in the vcd file + # Add the data to each probe in the vcd file for timestamp in range(0, 2 * len(self._data)): - # run the clock + # Run the clock writer.change(clock, timestamp, timestamp % 2 == 0) - # set the trigger (if there is one) + # Set the trigger (if there is one) if ( "trigger_mode" not in self._config or self._config["trigger_mode"] == "single_shot" @@ -375,7 +375,7 @@ class LogicAnalyzerCapture: triggered = (timestamp // 2) >= self.get_trigger_location() writer.change(trigger, timestamp, triggered) - # add other signals + # Add other signals for signal in signals: var = signal["var"] sample = signal["data"][timestamp // 2] diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 652f5be..1f16599 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -37,13 +37,13 @@ class LogicAnalyzerTriggerBlock(Elaboratable): return self.registers.get_max_addr() def clear_triggers(self): - # reset all triggers to disabled with no argument + # Reset all triggers to disabled with no argument for p in self._probes: self.registers.set_probe(p.name + "_op", Operations.DISABLE) self.registers.set_probe(p.name + "_arg", 0) def set_triggers(self, config): - # set triggers + # Set triggers for trigger in config["triggers"]: components = trigger.strip().split(" ") diff --git a/src/manta/manta.py b/src/manta/manta.py index 5dca676..0b89726 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -9,24 +9,26 @@ from manta.logic_analyzer import LogicAnalyzerCore class Manta(Elaboratable): def __init__(self, config): - # load config from either a configuration file or a dictionary. Users primarily use the - # config file, but the dictionary is included for internal tests. + # Load config from either a configuration file or a dictionary. + # Users primarily use the config file, but the dictionary is + # included for internal tests. if isinstance(config, str): - self.config = self.read_config_file(config) + self._config = self._read_config_file(config) if isinstance(config, dict): - self.config = config + self._config = config - self.check_config() + self._check_config() - self.interface = self.get_interface() - self.cores = self.get_cores() - self.add_friendly_core_names() + self._get_interface() + self._get_cores() + self._add_friendly_core_names() - def read_config_file(self, path): + def _read_config_file(self, path): """ - Take path to configuration file, and retun the configuration as a python list/dict object. + Takes a path to configuration file, and return the configuration as a + python dictionary. """ extension = path.split(".")[-1] @@ -46,37 +48,46 @@ class Manta(Elaboratable): else: raise ValueError("Unable to recognize configuration file extension.") - def check_config(self): - if "cores" not in self.config: + def _check_config(self): + if "cores" not in self._config: raise ValueError("No cores specified in configuration file.") - if not len(self.config["cores"]) > 0: + if not len(self._config["cores"]) > 0: raise ValueError("Must specify at least one core.") - for name, attrs in self.config["cores"].items(): - # make sure core type is specified + for name, attrs in self._config["cores"].items(): + # Make sure core type is specified if "type" not in attrs: raise ValueError(f"No type specified for core {name}.") if attrs["type"] not in ["logic_analyzer", "io", "memory_read_only"]: raise ValueError(f"Unrecognized core type specified for {name}.") - def get_interface(self): - if "uart" in self.config: - return UARTInterface.from_config(self.config["uart"]) + def _get_interface(self): + """ + Returns an instance of an interface object (UARTInterface or + EthernetInterface) configured with the parameters in the + config file. + """ + if "uart" in self._config: + self.interface = UARTInterface.from_config(self._config["uart"]) - elif "ethernet" in self.config: - return EthernetInterface(self.config["ethernet"]) + elif "ethernet" in self._config: + self.interface = EthernetInterface(self._config["ethernet"]) else: raise ValueError("No recognized interface specified.") - def get_cores(self): - """ """ + def _get_cores(self): + """ + Creates instances of the cores (IOCore, LogicAnalyzerCore, + ReadOnlyMemoryCore) specified in the user's configuration, and returns + them as a list. + """ - cores = {} + self._cores = {} base_addr = 0 - for name, attrs in self.config["cores"].items(): + for name, attrs in self._config["cores"].items(): if attrs["type"] == "io": core = IOCore.from_config(attrs, base_addr, self.interface) @@ -86,7 +97,7 @@ class Manta(Elaboratable): elif attrs["type"] == "memory_read_only": core = ReadOnlyMemoryCore.from_config(attrs, base_addr, self.interface) - # make sure we're not out of address space + # Make sure we're not out of address space if core.get_max_addr() > (2**16) - 1: raise ValueError( f"Ran out of address space to allocate to core {name}." @@ -94,18 +105,16 @@ class Manta(Elaboratable): # Make the next core's base address start one address after the previous one's base_addr = core.get_max_addr() + 1 - cores[name] = core + self._cores[name] = core - return cores - - def add_friendly_core_names(self): + def _add_friendly_core_names(self): """ Add cores to the instance under a friendly name - ie, a core named `my_core` belonging to a Manta instance `m` could be obtained with `m.cores["my_core"]`, but this allows it to be obtained with `m.my_core`. Which is way nicer. """ - for name, instance in self.cores.items(): + for name, instance in self._cores.items(): if not hasattr(self, name): setattr(self, name, instance) @@ -115,24 +124,17 @@ class Manta(Elaboratable): ) def elaborate(self, platform): - # make a module object - # add all the submodules - # connect them together, which consists of: - # connect interface to first core - # connect cores to each other - # connect interface to last core - m = Module() # Add interface as submodule m.submodules.interface = self.interface # Add all cores as submodules - for name, instance in self.cores.items(): + for name, instance in self._cores.items(): m.submodules[name] = instance # Connect first/last cores to interface output/input respectively - core_instances = list(self.cores.values()) + core_instances = list(self._cores.values()) first_core = core_instances[0] last_core = core_instances[-1] @@ -155,7 +157,7 @@ class Manta(Elaboratable): """ ports = self.interface.get_top_level_ports() - for name, instance in self.cores.items(): + for name, instance in self._cores.items(): ports += instance.get_top_level_ports() return ports diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 6bc3681..fa52411 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -64,7 +64,7 @@ class ReadOnlyMemoryCore(Elaboratable): if not width > 0: raise ValueError("Width of memory core must be positive. ") - cls(width, depth, base_addr, interface) + return cls(width, depth, base_addr, interface) def _pipeline_bus(self, m): self._bus_pipe = [Signal(InternalBus()) for _ in range(3)] diff --git a/src/manta/utils.py b/src/manta/utils.py index 7fe12f2..072ceb5 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -27,7 +27,7 @@ def warn(message): Prints a warning to the user's terminal. Originally the warn() method from the builtin warnings module was used for this, but I don't think the way it outputs on the command line is the most helpful for the users. - (They don't care about the stacktrace or the filename/line number, for example.) + (ie, Users don't care about the stacktrace or the filename/line number.) """ print("Warning: " + message) @@ -68,7 +68,7 @@ def value_to_words(data, n_words): if not isinstance(data, int) or data < 0: raise ValueError("Behavior is only defined for nonnegative integers.") - # convert to binary, split into 16-bit chunks, and then convert back to list of int + # Convert to binary, split into 16-bit chunks, and then convert back to list of int binary = f"{data:0b}".zfill(n_words * 16) return [int(binary[i : i + 16], 2) for i in range(0, 16 * n_words, 16)][::-1] @@ -113,7 +113,7 @@ def verify_register(module, addr, expected_data): possible to return a value from here, and compare it in the calling function. """ - # place read transaction on the bus + # Place read transaction on the bus yield module.bus_i.addr.eq(addr) yield module.bus_i.data.eq(0) yield module.bus_i.rw.eq(0) @@ -122,11 +122,11 @@ def verify_register(module, addr, expected_data): yield module.bus_i.addr.eq(0) yield module.bus_i.valid.eq(0) - # wait for output to be valid + # Wait for output to be valid while not (yield module.bus_o.valid): yield - # compare returned value with expected + # Compare returned value with expected data = yield (module.bus_o.data) if data != expected_data: raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") From 491db38def178109f7a6d22d222ff2c719c1adba Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 19 Feb 2024 13:53:04 -0800 Subject: [PATCH 57/89] tidy DHCP counter --- mkdocs.yml | 2 +- src/manta/ethernet/__init__.py | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/mkdocs.yml b/mkdocs.yml index 67f50e5..a82ea34 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -3,7 +3,7 @@ site_description: Manta Documentation site_author: Fischer Moseley repo_url: https://github.com/fischermoseley/manta/ - +repo_name: fischermoseley/manta docs_dir: 'doc' theme: diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index 1d779a9..a415420 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -22,6 +22,10 @@ class EthernetInterface(Elaboratable): self._fpga_ip_addr = config.get("fpga_ip_addr") self._host_ip_addr = config.get("host_ip_addr") self._udp_port = config.get("udp_port") + + # Convert to float first because Python considers scientific notation + # to only represent floats, not ints. + self._clk_freq = int(float(config.get("clk_freq"))) self._check_config() self.bus_i = Signal(InternalBus()) @@ -37,7 +41,7 @@ class EthernetInterface(Elaboratable): self.rmii_tx_en = Signal() self._dhcp_start = Signal() - self._dhcp_timer = Signal(range(int(100e6))) + self._dhcp_timer = Signal(range(self._clk_freq + 1), reset=self._clk_freq) self._source_data = Signal(32) self._source_last = Signal() @@ -109,11 +113,20 @@ class EthernetInterface(Elaboratable): def elaborate(self, platform): m = Module() - with m.If(self._dhcp_timer < int(50e6)): - m.d.sync += self._dhcp_timer.eq(self._dhcp_timer + 1) + # The DHCP engine in the LiteEth core will request a new IP address + # when the dhcp_start signal is pulsed. It doesn't want this signal + # immediately at power-on though, so a timer is used to request an IP + # one second after power on. The self._clk_freq attribute is used to + # figure out how many clock cycles that equates to. - m.d.sync += self._dhcp_start.eq(self._dhcp_timer == (int(50e6) - 2)) + # In my limited testing this seems to be enough time. + with m.If(self._dhcp_timer < 0): + m.d.sync += self._dhcp_timer.eq(self._dhcp_timer - 1) + + m.d.sync += self._dhcp_start.eq(self._dhcp_timer == 1) + + # Add the LiteEth core as a submodule m.submodules.liteeth = Instance( "liteeth_core", ("i", "sys_clock", ClockSignal()), From 8a2b9ced7665f3b05e41f3f625f202cbb0d28d0d Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 19 Feb 2024 17:19:23 -0800 Subject: [PATCH 58/89] add ethernet PHY IO autoassignment --- src/manta/ethernet/__init__.py | 129 +++++++++++++++++++++++++-------- 1 file changed, 99 insertions(+), 30 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index a415420..dc5ca69 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -22,6 +22,7 @@ class EthernetInterface(Elaboratable): self._fpga_ip_addr = config.get("fpga_ip_addr") self._host_ip_addr = config.get("host_ip_addr") self._udp_port = config.get("udp_port") + self._phy = config.get("phy") # Convert to float first because Python considers scientific notation # to only represent floats, not ints. @@ -31,14 +32,7 @@ class EthernetInterface(Elaboratable): self.bus_i = Signal(InternalBus()) self.bus_o = Signal(InternalBus()) - self.rmii_clocks_ref_clk = Signal() - self.rmii_crs_dv = Signal() - self.rmii_mdc = Signal() - self.rmii_mdio = Signal() - self.rmii_rst_n = Signal() - self.rmii_rx_data = Signal(2) - self.rmii_tx_data = Signal(2) - self.rmii_tx_en = Signal() + self._phy_io = self._define_phy_io() self._dhcp_start = Signal() self._dhcp_timer = Signal(range(self._clk_freq + 1), reset=self._clk_freq) @@ -94,22 +88,102 @@ class EthernetInterface(Elaboratable): Return the Amaranth signals that should be included as ports in the top-level Manta module. """ - ports = [ - self.rmii_clocks_ref_clk, - self.rmii_crs_dv, - self.rmii_mdc, - self.rmii_mdio, - self.rmii_rst_n, - self.rmii_rx_data, - self.rmii_tx_data, - self.rmii_tx_en, - ] - return ports + return [io[2] for io in self._phy_io] def _binarize_ip_addr(self, ip_addr): octets = [bin(int(o))[2:].zfill(8) for o in ip_addr.split(".")] return int("".join(octets), 2) + def _define_phy_io(self): + if self._phy in ["LiteEthPHYMII"]: + return [ + ("i", "mii_clocks_tx", mii_clocks_tx := Signal()), + ("i", "mii_clocks_rx", mii_clocks_rx := Signal()), + ("o", "mii_rst_n", mii_rst_n := Signal()), + ("io", "mii_mdio", mii_mdio := Signal()), + ("o", "mii_mdc", mii_mdc := Signal()), + ("i", "mii_rx_dv", mii_rx_dv := Signal()), + ("i", "mii_rx_er", mii_rx_er := Signal()), + ("i", "mii_rx_data", mii_rx_data := Signal(4)), + ("o", "mii_tx_en", mii_tx_en := Signal()), + ("o", "mii_tx_data", mii_tx_data := Signal(4)), + ("i", "mii_col", mii_col := Signal()), + ("i", "mii_crs", mii_crs := Signal()), + ] + + elif self._phy in ["LiteEthPHYRMII"]: + return [ + ("i", "rmii_clocks_ref_clk", rmii_clocks_ref_clk := Signal()), + ("o", "rmii_rst_n", rmii_rst_n := Signal()), + ("i", "rmii_rx_data", rmii_rx_data := Signal(2)), + ("i", "rmii_crs_dv", rmii_crs_dv := Signal()), + ("o", "rmii_tx_en", rmii_tx_en := Signal()), + ("o", "rmii_tx_data", rmii_tx_data := Signal(2)), + ("o", "rmii_mdc", rmii_mdc := Signal()), + ("io", "rmii_mdio", rmii_mdio := Signal()), + ] + + elif self._phy in [ + "LiteEthPHYGMII", + "LiteEthPHYGMIIMII", + ]: + return [ + ("i", "gmii_clocks_tx", gmii_clocks_tx := Signal()), + ("o", "gmii_clocks_gtx", gmii_clocks_gtx := Signal()), + ("i", "gmii_clocks_rx", gmii_clocks_rx := Signal()), + ("o", "gmii_rst_n", gmii_rst_n := Signal()), + ("i", "gmii_int_n", gmii_int_n := Signal()), + ("io", "gmii_mdio", gmii_mdio := Signal()), + ("o", "gmii_mdc", gmii_mdc := Signal()), + ("i", "gmii_rx_dv", gmii_rx_dv := Signal()), + ("i", "gmii_rx_er", gmii_rx_er := Signal()), + ("i", "gmii_rx_data", gmii_rx_data := Signal(8)), + ("o", "gmii_tx_en", gmii_tx_en := Signal()), + ("o", "gmii_tx_er", gmii_tx_er := Signal()), + ("o", "gmii_tx_data", gmii_tx_data := Signal(8)), + ("i", "gmii_col", gmii_col := Signal()), + ("i", "gmii_crs", gmii_crs := Signal()), + ] + + elif self._phy in [ + "LiteEthS7PHYRGMII", + "LiteEthECP5PHYRGMII", + ]: + return [ + ("o", "rgmii_clocks_tx", rgmii_clocks_tx := Signal()), + ("i", "rgmii_clocks_rx", rgmii_clocks_rx := Signal()), + ("o", "rgmii_rst_n", rgmii_rst_n := Signal()), + ("i", "rgmii_int_n", rgmii_int_n := Signal()), + ("io", "rgmii_mdio", rgmii_mdio := Signal()), + ("o", "rgmii_mdc", rgmii_mdc := Signal()), + ("i", "rgmii_rx_ctl", rgmii_rx_ctl := Signal()), + ("i", "rgmii_rx_data", rgmii_rx_data := Signal(4)), + ("o", "rgmii_tx_ctl", rgmii_tx_ctl := Signal()), + ("o", "rgmii_tx_data", rgmii_tx_data := Signal(4)), + ] + + elif self._phy in [ + "A7_1000BASEX", + "A7_2500BASEX", + "K7_1000BASEX", + "K7_2500BASEX", + "KU_1000BASEX", + "KU_2500BASEX", + "USP_GTH_1000BASEX", + "USP_GTH_2500BASEX", + "USP_GTY_1000BASEX", + "USP_GTY_2500BASEX", + ]: + return [ + ("i", "sgmii_refclk", sgmii_refclk := Signal()), + ("i", "sgmii_rst", sgmii_rst := Signal()), + ("o", "sgmii_txp", sgmii_txp := Signal()), + ("o", "sgmii_txn", sgmii_txn := Signal()), + ("i", "sgmii_rxp", sgmii_rxp := Signal()), + ("i", "sgmii_rxn", sgmii_rxn := Signal()), + ("o", "sgmii_link_up", sgmii_link_up := Signal()), + ] + def elaborate(self, platform): m = Module() @@ -132,14 +206,7 @@ class EthernetInterface(Elaboratable): ("i", "sys_clock", ClockSignal()), ("i", "sys_reset", ResetSignal()), # PHY connection - ("i", "rmii_clocks_ref_clk", self.rmii_clocks_ref_clk), - ("i", "rmii_crs_dv", self.rmii_crs_dv), - ("o", "rmii_mdc", self.rmii_mdc), - ("io", "rmii_mdio", self.rmii_mdio), - ("o", "rmii_rst_n", self.rmii_rst_n), - ("i", "rmii_rx_data", self.rmii_rx_data), - ("o", "rmii_tx_data", self.rmii_tx_data), - ("o", "rmii_tx_en", self.rmii_tx_en), + *self._phy_io, # DHCP # ("o", "dhcp_done", 1), # ("o", "dhcp_ip_address", 1), @@ -265,15 +332,17 @@ class EthernetInterface(Elaboratable): """ liteeth_config = self._config.copy() - # Randomly assign a MAC address if one is not specified in the configuration. - # This will choose a MAC address in the Locally Administered, Administratively Assigned group. - # For more information, see: + # Randomly assign a MAC address if one is not specified in the + # configuration. This will choose a MAC address in the Locally + # Administered, Administratively Assigned group. For more information, + # please reference: # https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses if "mac_address" not in liteeth_config: addr = list(f"{randint(0, (2**48) - 1):012x}") addr[1] = "2" liteeth_config["mac_address"] = int("".join(addr), 16) + print(liteeth_config["mac_address"]) # Force use of DHCP liteeth_config["dhcp"] = True From ab7d9105b1af99013b0ce515db410478ea71efc1 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 28 Feb 2024 10:36:27 -0800 Subject: [PATCH 59/89] add preliminary bidirectional memory core --- src/manta/logic_analyzer/__init__.py | 2 +- src/manta/manta.py | 2 +- src/manta/memory_core.py | 266 +++++++++++++++++---------- test/test_mem_core_sim.py | 10 +- 4 files changed, 178 insertions(+), 102 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 62dc8c6..c3f7c26 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -1,6 +1,6 @@ from amaranth import * from manta.utils import * -from manta.memory_core import ReadOnlyMemoryCore +from manta.memory_core import MemoryCore from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock from manta.logic_analyzer.fsm import LogicAnalyzerFSM, States, TriggerModes from manta.logic_analyzer.playback import LogicAnalyzerPlayback diff --git a/src/manta/manta.py b/src/manta/manta.py index 0b89726..424a40a 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -3,7 +3,7 @@ from manta.uart import UARTInterface from manta.ethernet import EthernetInterface from manta.io_core import IOCore -from manta.memory_core import ReadOnlyMemoryCore +from manta.memory_core import MemoryCore from manta.logic_analyzer import LogicAnalyzerCore diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index fa52411..f62af64 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -1,12 +1,13 @@ from amaranth import * +from amaranth.lib.memory import Memory from manta.utils import * from math import ceil -class ReadOnlyMemoryCore(Elaboratable): +class MemoryCore(Elaboratable): """ - A module for generating a memory on the FPGA, with a read port tied to - Manta's internal bus, and a write port provided to user logic. + A module for generating a memory on the FPGA, with a port tied to Manta's + internal bus, and a port provided to user logic. Provides methods for generating synthesizable logic for the FPGA, as well as methods for reading and writing the value of a register. @@ -15,24 +16,50 @@ class ReadOnlyMemoryCore(Elaboratable): https://fischermoseley.github.io/manta/memory_core/ """ - def __init__(self, width, depth, base_addr, interface): + def __init__(self, mode, width, depth, base_addr, interface): + self._mode = mode self._width = width self._depth = depth self._base_addr = base_addr self._interface = interface - self._max_addr = self._base_addr + (self._depth * ceil(self._width / 16)) + self._n_brams = ceil(self._width / 16) + self._max_addr = self._base_addr + (self._depth * self._n_brams) # Bus Connections self.bus_i = Signal(InternalBus()) self.bus_o = Signal(InternalBus()) - # User Port - self.user_addr = Signal(range(self._depth)) - self.user_data = Signal(self._width) - self.user_we = Signal(1) + # User Ports + if self._mode == "fpga_to_host": + self.user_addr = Signal(range(self._depth)) + self.user_data_in = Signal(self._width) + self.user_write_enable = Signal() + self._top_level_ports = [ + self.user_addr, + self.user_data_in, + self.user_write_enable, + ] - self._define_mems() + elif self._mode == "host_to_fpga": + self.user_addr = Signal(range(self._depth)) + self.user_data_out = Signal(self._width) + self._top_level_ports = [ + self.user_addr, + self.user_data_out, + ] + + elif self._mode == "bidirectional": + self.user_addr = Signal(range(self._depth)) + self.user_data_in = Signal(self._width) + self.user_data_out = Signal(self._width) + self.user_write_enable = Signal() + self._top_level_ports = [ + self.user_addr, + self.user_data_in, + self.user_data_out, + self.user_write_enable, + ] @classmethod def from_config(cls, config, base_addr, interface): @@ -64,9 +91,86 @@ class ReadOnlyMemoryCore(Elaboratable): if not width > 0: raise ValueError("Width of memory core must be positive. ") - return cls(width, depth, base_addr, interface) + # Check mode is provided and is recognized value + mode = config.get("mode") + if not mode: + raise ValueError("Mode of memory core must be specified.") - def _pipeline_bus(self, m): + if mode not in ["fpga_to_host", "host_to_fpga", "bidirectional"]: + raise ValueError("Unrecognized mode provided to memory core.") + + return cls(mode, width, depth, base_addr, interface) + + def _tie_mems_to_bus(self, m): + for i, mem in enumerate(self._mems): + # Compute address range corresponding to this chunk of memory + start_addr = self._base_addr + (i * self._depth) + stop_addr = start_addr + self._depth - 1 + + # Handle write ports + if self._mode in ["host_to_fpga", "bidirectional"]: + write_port = mem.write_port() + m.d.sync += write_port.data.eq(self.bus_i.data) + m.d.sync += write_port.en.eq(self.bus_i.rw) + m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr) + + # Handle read ports + if self._mode in ["fpga_to_host", "bidirectional"]: + read_port = mem.read_port() + m.d.comb += read_port.en.eq(1) + + # Throw BRAM operations into the front of the pipeline + with m.If( + (self.bus_i.valid) + & (self.bus_i.addr >= start_addr) + & (self.bus_i.addr <= stop_addr) + ): + m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) + + # Pull BRAM reads from the back of the pipeline + with m.If( + (self._bus_pipe[2].valid) + & (self._bus_pipe[2].addr >= start_addr) + & (self._bus_pipe[2].addr <= stop_addr) + ): + m.d.sync += self.bus_o.data.eq(read_port.data) + + def _tie_mems_to_user_logic(self, m): + # Handle write ports + if self._mode in ["fpga_to_host", "bidirectional"]: + for i, mem in enumerate(self._mems): + write_port = mem.write_port() + m.d.comb += write_port.addr.eq(self.user_addr) + m.d.comb += write_port.data.eq(self.user_data_in[16 * i : 16 * (i + 1)]) + m.d.comb += write_port.en.eq(self.user_write_enable) + + # Handle read ports + if self._mode in ["host_to_fpga", "bidirectional"]: + read_datas = [] + for i, mem in enumerate(self._mems): + read_port = mem.read_port() + m.d.comb += read_port.addr.eq(self.user_addr) + m.d.comb += read_port.en.eq(1) + read_datas.append(read_port.data) + + m.d.comb += self.user_data_out.eq(Cat(read_datas)) + + def elaborate(self, platform): + m = Module() + + # Define memories + n_full = self._width // 16 + n_partial = self._width % 16 + + self._mems = [Memory(shape=16, depth=self._depth, init=[0]*self._depth) for _ in range(n_full)] + if n_partial > 0: + self._mems += [Memory(shape=n_partial, depth=self._depth, init=[0]*self._depth)] + + # Add memories as submodules + for i, mem in enumerate(self._mems): + m.submodules[f"mem_{i}"] = mem + + # Pipeline the bus to accomodate the two clock-cycle delay in the memories self._bus_pipe = [Signal(InternalBus()) for _ in range(3)] m.d.sync += self._bus_pipe[0].eq(self.bus_i) @@ -75,75 +179,9 @@ class ReadOnlyMemoryCore(Elaboratable): m.d.sync += self.bus_o.eq(self._bus_pipe[2]) - def _define_mems(self): - # There's three cases that must be handled: - # 1. Integer number of 16 bit mems - # 2. Integer number of 16 bit mems + partial mem - # 3. Just the partial mem (width < 16) - - # Only one, partial-width memory is needed - if self._width < 16: - self._mems = [Memory(depth=self._depth, width=self._width)] - - # Only full-width memories are needed - elif self._width % 16 == 0: - self._mems = [ - Memory(depth=self._depth, width=16) for _ in range(self._width // 16) - ] - - # Both full-width and partial memories are needed - else: - self._mems = [ - Memory(depth=self._depth, width=16) for i in range(self._width // 16) - ] - self._mems += [Memory(depth=self._depth, width=self._width % 16)] - - def _handle_read_ports(self, m): - # These are tied to the bus - for i, mem in enumerate(self._mems): - read_port = mem.read_port() - m.d.comb += read_port.en.eq(1) - - start_addr = self._base_addr + (i * self._depth) - stop_addr = start_addr + self._depth - 1 - - # Throw BRAM operations into the front of the pipeline - with m.If( - (self.bus_i.valid) - & (~self.bus_i.rw) - & (self.bus_i.addr >= start_addr) - & (self.bus_i.addr <= stop_addr) - ): - m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) - - # Pull BRAM reads from the back of the pipeline - with m.If( - (self._bus_pipe[2].valid) - & (~self._bus_pipe[2].rw) - & (self._bus_pipe[2].addr >= start_addr) - & (self._bus_pipe[2].addr <= stop_addr) - ): - m.d.sync += self.bus_o.data.eq(read_port.data) - - def _handle_write_ports(self, m): - # These are given to the user - for i, mem in enumerate(self._mems): - write_port = mem.write_port() - - m.d.comb += write_port.addr.eq(self.user_addr) - m.d.comb += write_port.data.eq(self.user_data[16 * i : 16 * (i + 1)]) - m.d.comb += write_port.en.eq(self.user_we) - - def elaborate(self, platform): - m = Module() - - # Add memories as submodules - for i, mem in enumerate(self._mems): - m.submodules[f"mem_{i}"] = mem - - self._pipeline_bus(m) - self._handle_read_ports(m) - self._handle_write_ports(m) + # Tie memory ports to the internal bus and user logic + self._tie_mems_to_bus(m) + self._tie_mems_to_user_logic(m) return m def get_top_level_ports(self): @@ -151,7 +189,7 @@ class ReadOnlyMemoryCore(Elaboratable): Return the Amaranth signals that should be included as ports in the top-level Manta module. """ - return [self.user_addr, self.user_data, self.user_we] + return self._top_level_ports def get_max_addr(self): """ @@ -161,26 +199,64 @@ class ReadOnlyMemoryCore(Elaboratable): """ return self._max_addr - def read_from_user_addr(self, addrs): + def _convert_user_to_bus_addr(self, addrs): + """ + Convert user address space to bus address space. For instance, for a + core with base address 10 and width 33, reading from address 4 is + actually a read from address 14 and address 14 + depth, and address + 14 + (2 * depth). + """ + if isinstance(addrs, int): + return self._convert_user_to_bus_addr([addrs])[0] + + bus_addrs = [] + for addr in addrs: + for i in range(len(self._mems)): + bus_addrs.append(self._base_addr + addr + (i * self._depth)) + + return bus_addrs + + def read(self, addrs): """ Read the memory stored at the provided address, as seen from the user side. """ - # Convert user address space to bus address space - # (for instance, for a core with base address 10 and width 33, - # reading from address 4 is actually a read from address 14 - # and address 14 + depth, and address 14 + 2*depth) - + # Handle a single integer address if isinstance(addrs, int): - return self.read_from_user_addr([addrs])[0] + return self.read([addrs])[0] - bus_addrs = [] - for addr in addrs: - bus_addrs += [ - addr + self._base_addr + i * self._depth for i in range(len(self._mems)) - ] + # Make sure all list elements are integers + if not all(isinstance(a, int) for a in addrs): + raise TypeError("Read address must be an integer or list of integers.") + bus_addrs = self._convert_user_to_bus_addr(addrs) datas = self._interface.read(bus_addrs) - data_chunks = split_into_chunks(datas, len(self._mems)) + data_chunks = split_into_chunks(datas, self._n_brams) return [words_to_value(chunk) for chunk in data_chunks] + + def write(self, addrs, datas): + """ + Write to the memory stored at the provided address, as seen from the + user side. + """ + + # Handle a single integer address and data + if isinstance(addrs, int) and isinstance(datas, int): + return self.write([addrs], [datas]) + + # Make sure address and datas are all integers + if not isinstance(addrs, list) or not isinstance(datas, list): + raise TypeError( + "Write addresses and data must be an integer or list of integers." + ) + + if not all(isinstance(a, int) for a in addrs): + raise TypeError("Write addresses must be all be integers.") + + if not all(isinstance(d, int) for d in datas): + raise TypeError("Write data must all be integers.") + + bus_addrs = self._convert_user_to_bus_addr([addrs])[0] + bus_datas = [word for d in datas for word in value_to_words(d, self._n_brams)] + self._interface.write(bus_addrs, bus_datas) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index e793c4f..fce9800 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -1,4 +1,4 @@ -from manta.memory_core import ReadOnlyMemoryCore +from manta.memory_core import MemoryCore from manta.utils import * from random import randint, sample @@ -6,16 +6,16 @@ from random import randint, sample def fill_mem_from_user_port(mem_core, depth): for i in range(depth): yield mem_core.user_addr.eq(i) - yield mem_core.user_data.eq(i) - yield mem_core.user_we.eq(1) + yield mem_core.user_data_in.eq(i) + yield mem_core.user_write_enable.eq(1) yield - yield mem_core.user_we.eq(0) + yield mem_core.user_write_enable.eq(0) yield def verify_mem_core(width, depth, base_addr): - mem_core = ReadOnlyMemoryCore(width, depth, base_addr, interface=None) + mem_core = MemoryCore("fpga_to_host", width, depth, base_addr, interface=None) def testbench(): yield from fill_mem_from_user_port(mem_core, depth) From 6aea5cc6e1144e65b956d9368d062048928233c4 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 2 Mar 2024 12:52:04 -0800 Subject: [PATCH 60/89] update MemoryCore references --- doc/assets/memory_architecture.drawio.svg | 66 +++++++++++------------ src/manta/logic_analyzer/__init__.py | 7 +-- src/manta/manta.py | 7 ++- test/test_mem_core_hw.py | 4 +- 4 files changed, 41 insertions(+), 43 deletions(-) diff --git a/doc/assets/memory_architecture.drawio.svg b/doc/assets/memory_architecture.drawio.svg index ef58678..c929ee4 100644 --- a/doc/assets/memory_architecture.drawio.svg +++ b/doc/assets/memory_architecture.drawio.svg @@ -1,4 +1,4 @@ - + - + @@ -103,7 +101,7 @@ -
    +
    addr @@ -121,7 +119,7 @@ -
    +
    din @@ -129,7 +127,7 @@
    - + din @@ -139,7 +137,7 @@ -
    +
    dout @@ -157,7 +155,7 @@ -
    +
    we @@ -258,12 +256,12 @@ - + -
    +
    user_addr @@ -276,8 +274,8 @@ - - + + @@ -289,17 +287,17 @@
    - + user_din - - + + -
    +
    user_dout @@ -312,21 +310,21 @@ - - + + -
    +
    - user_we + user_write_enable
    - user_we + user_write_enable @@ -353,7 +351,7 @@ -
    +
    din @@ -361,7 +359,7 @@
    - + din @@ -476,7 +474,7 @@ -
    +
    din @@ -484,7 +482,7 @@
    - + din @@ -603,12 +601,12 @@ - - + + -
    +
    bus @@ -616,17 +614,17 @@
    - + bus - - + + -
    +
    bus @@ -634,7 +632,7 @@
    - + bus diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index c3f7c26..3f091f6 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -36,7 +36,8 @@ class LogicAnalyzerCore(Elaboratable): self._probes, self._fsm.get_max_addr() + 1, interface ) - self._sample_mem = ReadOnlyMemoryCore( + self._sample_mem = MemoryCore( + mode = "fpga_to_host", width=sum(self._config["probes"].values()), depth=self._config["sample_depth"], base_addr=self._trig_blk.get_max_addr() + 1, @@ -158,7 +159,7 @@ class LogicAnalyzerCore(Elaboratable): # Concat all the probes together, and feed to input of sample memory # (it is necessary to reverse the order such that first probe occupies # the lowest location in memory) - m.d.comb += self._sample_mem.user_data.eq(Cat(self._probes[::-1])) + m.d.comb += self._sample_mem.user_data_in.eq(Cat(self._probes[::-1])) # Wire bus connections between internal modules m.d.comb += [ @@ -170,7 +171,7 @@ class LogicAnalyzerCore(Elaboratable): # Non-bus Connections self._fsm.trigger.eq(self._trig_blk.trig), self._sample_mem.user_addr.eq(self._fsm.write_pointer), - self._sample_mem.user_we.eq(self._fsm.write_enable), + self._sample_mem.user_write_enable.eq(self._fsm.write_enable), ] return m diff --git a/src/manta/manta.py b/src/manta/manta.py index 424a40a..cf2bd09 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -80,9 +80,8 @@ class Manta(Elaboratable): def _get_cores(self): """ - Creates instances of the cores (IOCore, LogicAnalyzerCore, - ReadOnlyMemoryCore) specified in the user's configuration, and returns - them as a list. + Creates instances of the cores (IOCore, LogicAnalyzerCore, MemoryCore) + specified in the user's configuration, and returns them as a list. """ self._cores = {} @@ -95,7 +94,7 @@ class Manta(Elaboratable): core = LogicAnalyzerCore(attrs, base_addr, self.interface) elif attrs["type"] == "memory_read_only": - core = ReadOnlyMemoryCore.from_config(attrs, base_addr, self.interface) + core = MemoryCore.from_config(attrs, base_addr, self.interface) # Make sure we're not out of address space if core.get_max_addr() > (2**16) - 1: diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 78bd024..3a5d7b5 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -73,8 +73,8 @@ class MemoryCoreLoopbackTest(Elaboratable): m.d.comb += [ self.manta.mem_core.user_addr.eq(addr), - self.manta.mem_core.user_data.eq(data), - self.manta.mem_core.user_we.eq(we), + self.manta.mem_core.user_data_in.eq(data), + self.manta.mem_core.user_write_enable.eq(we), self.manta.interface.rx.eq(uart_pins.rx.i), uart_pins.tx.o.eq(self.manta.interface.tx), ] From 6438a55192b0a90c74091793d8a74212fcc20f00 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 2 Mar 2024 13:31:01 -0800 Subject: [PATCH 61/89] partially revert MemoryCore updates --- src/manta/io_core.py | 2 +- src/manta/logic_analyzer/__init__.py | 4 +- src/manta/logic_analyzer/fsm.py | 2 +- src/manta/logic_analyzer/trigger_block.py | 2 +- src/manta/memory_core.py | 158 ++++++++++------------ test/test_mem_core_hw.py | 2 +- 6 files changed, 80 insertions(+), 90 deletions(-) diff --git a/src/manta/io_core.py b/src/manta/io_core.py index ff633a6..63d6df5 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -184,7 +184,7 @@ class IOCore(Elaboratable): """ Return the maximum addresses in memory used by the core. The address space used by the core extends from `base_addr` to the number returned - by this function. + by this function (including the endpoints). """ return self._max_addr diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 3f091f6..c36d171 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -187,7 +187,7 @@ class LogicAnalyzerCore(Elaboratable): """ Return the maximum addresses in memory used by the core. The address space used by the core extends from `base_addr` to the number returned - by this function. + by this function (including the endpoints). """ return self._sample_mem.get_max_addr() @@ -253,7 +253,7 @@ class LogicAnalyzerCore(Elaboratable): # Read out the entirety of the sample memory print_if_verbose(" -> Reading sample memory contents...") addrs = list(range(self._config["sample_depth"])) - raw_capture = self._sample_mem.read_from_user_addr(addrs) + raw_capture = self._sample_mem.read(addrs) # Revolve the memory around the read_pointer, such that all the beginning # of the caputure is at the first element diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index cdf4b3c..bfe4183 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -64,7 +64,7 @@ class LogicAnalyzerFSM(Elaboratable): """ Return the maximum addresses in memory used by the core. The address space used by the core extends from `base_addr` to the number returned - by this function. + by this function (including the endpoints). """ return self.registers.get_max_addr() diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 1f16599..ff67b45 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -32,7 +32,7 @@ class LogicAnalyzerTriggerBlock(Elaboratable): """ Return the maximum addresses in memory used by the core. The address space used by the core extends from `base_addr` to the number returned - by this function. + by this function (including the endpoints). """ return self.registers.get_max_addr() diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index f62af64..367b519 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -1,5 +1,4 @@ from amaranth import * -from amaranth.lib.memory import Memory from manta.utils import * from math import ceil @@ -61,6 +60,8 @@ class MemoryCore(Elaboratable): self.user_write_enable, ] + self._define_mems() + @classmethod def from_config(cls, config, base_addr, interface): # Check for unrecognized options @@ -91,86 +92,9 @@ class MemoryCore(Elaboratable): if not width > 0: raise ValueError("Width of memory core must be positive. ") - # Check mode is provided and is recognized value - mode = config.get("mode") - if not mode: - raise ValueError("Mode of memory core must be specified.") + return cls(width, depth, base_addr, interface) - if mode not in ["fpga_to_host", "host_to_fpga", "bidirectional"]: - raise ValueError("Unrecognized mode provided to memory core.") - - return cls(mode, width, depth, base_addr, interface) - - def _tie_mems_to_bus(self, m): - for i, mem in enumerate(self._mems): - # Compute address range corresponding to this chunk of memory - start_addr = self._base_addr + (i * self._depth) - stop_addr = start_addr + self._depth - 1 - - # Handle write ports - if self._mode in ["host_to_fpga", "bidirectional"]: - write_port = mem.write_port() - m.d.sync += write_port.data.eq(self.bus_i.data) - m.d.sync += write_port.en.eq(self.bus_i.rw) - m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr) - - # Handle read ports - if self._mode in ["fpga_to_host", "bidirectional"]: - read_port = mem.read_port() - m.d.comb += read_port.en.eq(1) - - # Throw BRAM operations into the front of the pipeline - with m.If( - (self.bus_i.valid) - & (self.bus_i.addr >= start_addr) - & (self.bus_i.addr <= stop_addr) - ): - m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) - - # Pull BRAM reads from the back of the pipeline - with m.If( - (self._bus_pipe[2].valid) - & (self._bus_pipe[2].addr >= start_addr) - & (self._bus_pipe[2].addr <= stop_addr) - ): - m.d.sync += self.bus_o.data.eq(read_port.data) - - def _tie_mems_to_user_logic(self, m): - # Handle write ports - if self._mode in ["fpga_to_host", "bidirectional"]: - for i, mem in enumerate(self._mems): - write_port = mem.write_port() - m.d.comb += write_port.addr.eq(self.user_addr) - m.d.comb += write_port.data.eq(self.user_data_in[16 * i : 16 * (i + 1)]) - m.d.comb += write_port.en.eq(self.user_write_enable) - - # Handle read ports - if self._mode in ["host_to_fpga", "bidirectional"]: - read_datas = [] - for i, mem in enumerate(self._mems): - read_port = mem.read_port() - m.d.comb += read_port.addr.eq(self.user_addr) - m.d.comb += read_port.en.eq(1) - read_datas.append(read_port.data) - - m.d.comb += self.user_data_out.eq(Cat(read_datas)) - - def elaborate(self, platform): - m = Module() - - # Define memories - n_full = self._width // 16 - n_partial = self._width % 16 - - self._mems = [Memory(shape=16, depth=self._depth, init=[0]*self._depth) for _ in range(n_full)] - if n_partial > 0: - self._mems += [Memory(shape=n_partial, depth=self._depth, init=[0]*self._depth)] - - # Add memories as submodules - for i, mem in enumerate(self._mems): - m.submodules[f"mem_{i}"] = mem - - # Pipeline the bus to accomodate the two clock-cycle delay in the memories + def _pipeline_bus(self, m): self._bus_pipe = [Signal(InternalBus()) for _ in range(3)] m.d.sync += self._bus_pipe[0].eq(self.bus_i) @@ -179,9 +103,75 @@ class MemoryCore(Elaboratable): m.d.sync += self.bus_o.eq(self._bus_pipe[2]) - # Tie memory ports to the internal bus and user logic - self._tie_mems_to_bus(m) - self._tie_mems_to_user_logic(m) + def _define_mems(self): + # There's three cases that must be handled: + # 1. Integer number of 16 bit mems + # 2. Integer number of 16 bit mems + partial mem + # 3. Just the partial mem (width < 16) + + # Only one, partial-width memory is needed + if self._width < 16: + self._mems = [Memory(depth=self._depth, width=self._width)] + + # Only full-width memories are needed + elif self._width % 16 == 0: + self._mems = [ + Memory(depth=self._depth, width=16) for _ in range(self._width // 16) + ] + + # Both full-width and partial memories are needed + else: + self._mems = [ + Memory(depth=self._depth, width=16) for i in range(self._width // 16) + ] + self._mems += [Memory(depth=self._depth, width=self._width % 16)] + + def _handle_read_ports(self, m): + # These are tied to the bus + for i, mem in enumerate(self._mems): + read_port = mem.read_port() + m.d.comb += read_port.en.eq(1) + + start_addr = self._base_addr + (i * self._depth) + stop_addr = start_addr + self._depth - 1 + + # Throw BRAM operations into the front of the pipeline + with m.If( + (self.bus_i.valid) + & (~self.bus_i.rw) + & (self.bus_i.addr >= start_addr) + & (self.bus_i.addr <= stop_addr) + ): + m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) + + # Pull BRAM reads from the back of the pipeline + with m.If( + (self._bus_pipe[2].valid) + & (~self._bus_pipe[2].rw) + & (self._bus_pipe[2].addr >= start_addr) + & (self._bus_pipe[2].addr <= stop_addr) + ): + m.d.sync += self.bus_o.data.eq(read_port.data) + + def _handle_write_ports(self, m): + # These are given to the user + for i, mem in enumerate(self._mems): + write_port = mem.write_port() + + m.d.comb += write_port.addr.eq(self.user_addr) + m.d.comb += write_port.data.eq(self.user_data_in[16 * i : 16 * (i + 1)]) + m.d.comb += write_port.en.eq(self.user_write_enable) + + def elaborate(self, platform): + m = Module() + + # Add memories as submodules + for i, mem in enumerate(self._mems): + m.submodules[f"mem_{i}"] = mem + + self._pipeline_bus(m) + self._handle_read_ports(m) + self._handle_write_ports(m) return m def get_top_level_ports(self): @@ -195,7 +185,7 @@ class MemoryCore(Elaboratable): """ Return the maximum addresses in memory used by the core. The address space used by the core extends from `base_addr` to the number returned - by this function. + by this function (including the endpoints). """ return self._max_addr diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 3a5d7b5..6afdd4c 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -92,7 +92,7 @@ class MemoryCoreLoopbackTest(Elaboratable): self.manta.io_core.set_probe("we", 0) def verify_register(self, addr, expected_data): - data = self.manta.mem_core.read_from_user_addr(addr) + data = self.manta.mem_core.read(addr) if data != expected_data: raise ValueError( From 40a57651bb9540600e0494c0188db72f32fb297a Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 2 Mar 2024 13:44:08 -0800 Subject: [PATCH 62/89] shorten methods in MemoryCore --- src/manta/memory_core.py | 60 +++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 35 deletions(-) diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 367b519..48ae8c4 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -60,8 +60,6 @@ class MemoryCore(Elaboratable): self.user_write_enable, ] - self._define_mems() - @classmethod def from_config(cls, config, base_addr, interface): # Check for unrecognized options @@ -92,40 +90,16 @@ class MemoryCore(Elaboratable): if not width > 0: raise ValueError("Width of memory core must be positive. ") + # Check mode is provided and is recognized value + mode = config.get("mode") + if not mode: + raise ValueError("Mode of memory core must be specified.") + + if mode not in ["fpga_to_host", "host_to_fpga", "bidirectional"]: + raise ValueError("Unrecognized mode provided to memory core.") + return cls(width, depth, base_addr, interface) - def _pipeline_bus(self, m): - self._bus_pipe = [Signal(InternalBus()) for _ in range(3)] - m.d.sync += self._bus_pipe[0].eq(self.bus_i) - - for i in range(1, 3): - m.d.sync += self._bus_pipe[i].eq(self._bus_pipe[i - 1]) - - m.d.sync += self.bus_o.eq(self._bus_pipe[2]) - - def _define_mems(self): - # There's three cases that must be handled: - # 1. Integer number of 16 bit mems - # 2. Integer number of 16 bit mems + partial mem - # 3. Just the partial mem (width < 16) - - # Only one, partial-width memory is needed - if self._width < 16: - self._mems = [Memory(depth=self._depth, width=self._width)] - - # Only full-width memories are needed - elif self._width % 16 == 0: - self._mems = [ - Memory(depth=self._depth, width=16) for _ in range(self._width // 16) - ] - - # Both full-width and partial memories are needed - else: - self._mems = [ - Memory(depth=self._depth, width=16) for i in range(self._width // 16) - ] - self._mems += [Memory(depth=self._depth, width=self._width % 16)] - def _handle_read_ports(self, m): # These are tied to the bus for i, mem in enumerate(self._mems): @@ -165,11 +139,27 @@ class MemoryCore(Elaboratable): def elaborate(self, platform): m = Module() + # Define memories + n_full = self._width // 16 + n_partial = self._width % 16 + + self._mems = [Memory(width=16, depth=self._depth, init=[0]*self._depth) for _ in range(n_full)] + if n_partial > 0: + self._mems += [Memory(width=n_partial, depth=self._depth, init=[0]*self._depth)] + # Add memories as submodules for i, mem in enumerate(self._mems): m.submodules[f"mem_{i}"] = mem - self._pipeline_bus(m) + # Pipeline the bus to accomodate the two clock-cycle delay in the memories + self._bus_pipe = [Signal(InternalBus()) for _ in range(3)] + m.d.sync += self._bus_pipe[0].eq(self.bus_i) + + for i in range(1, 3): + m.d.sync += self._bus_pipe[i].eq(self._bus_pipe[i - 1]) + + m.d.sync += self.bus_o.eq(self._bus_pipe[2]) + self._handle_read_ports(m) self._handle_write_ports(m) return m From 2e2397013e8e022af45e0c6651ac0ef13d65df33 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sat, 2 Mar 2024 14:08:52 -0800 Subject: [PATCH 63/89] make mem_core_hw tests pass --- src/manta/logic_analyzer/__init__.py | 2 +- src/manta/manta.py | 4 +- src/manta/memory_core.py | 94 ++++++++++++++++++---------- test/test_mem_core_hw.py | 3 +- 4 files changed, 65 insertions(+), 38 deletions(-) diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index c36d171..19e3a04 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -37,7 +37,7 @@ class LogicAnalyzerCore(Elaboratable): ) self._sample_mem = MemoryCore( - mode = "fpga_to_host", + mode="fpga_to_host", width=sum(self._config["probes"].values()), depth=self._config["sample_depth"], base_addr=self._trig_blk.get_max_addr() + 1, diff --git a/src/manta/manta.py b/src/manta/manta.py index cf2bd09..1a3830b 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -60,7 +60,7 @@ class Manta(Elaboratable): if "type" not in attrs: raise ValueError(f"No type specified for core {name}.") - if attrs["type"] not in ["logic_analyzer", "io", "memory_read_only"]: + if attrs["type"] not in ["logic_analyzer", "io", "memory"]: raise ValueError(f"Unrecognized core type specified for {name}.") def _get_interface(self): @@ -93,7 +93,7 @@ class Manta(Elaboratable): elif attrs["type"] == "logic_analyzer": core = LogicAnalyzerCore(attrs, base_addr, self.interface) - elif attrs["type"] == "memory_read_only": + elif attrs["type"] == "memory": core = MemoryCore.from_config(attrs, base_addr, self.interface) # Make sure we're not out of address space diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 48ae8c4..e88a9ec 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -63,7 +63,7 @@ class MemoryCore(Elaboratable): @classmethod def from_config(cls, config, base_addr, interface): # Check for unrecognized options - valid_options = ["type", "depth", "width"] + valid_options = ["type", "depth", "width", "mode"] for option in config: if option not in valid_options: warn(f"Ignoring unrecognized option '{option}' in memory core.") @@ -98,43 +98,64 @@ class MemoryCore(Elaboratable): if mode not in ["fpga_to_host", "host_to_fpga", "bidirectional"]: raise ValueError("Unrecognized mode provided to memory core.") - return cls(width, depth, base_addr, interface) + return cls(mode, width, depth, base_addr, interface) - def _handle_read_ports(self, m): - # These are tied to the bus + def _tie_mems_to_bus(self, m): for i, mem in enumerate(self._mems): - read_port = mem.read_port() - m.d.comb += read_port.en.eq(1) - + # Compute address range corresponding to this chunk of memory start_addr = self._base_addr + (i * self._depth) stop_addr = start_addr + self._depth - 1 - # Throw BRAM operations into the front of the pipeline - with m.If( - (self.bus_i.valid) - & (~self.bus_i.rw) - & (self.bus_i.addr >= start_addr) - & (self.bus_i.addr <= stop_addr) - ): - m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) + # Handle write ports + if self._mode in ["host_to_fpga", "bidirectional"]: + pass + # write_port = mem.write_port() + # m.d.sync += write_port.data.eq(self.bus_i.data) + # m.d.sync += write_port.en.eq(self.bus_i.rw) + # m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr) - # Pull BRAM reads from the back of the pipeline - with m.If( - (self._bus_pipe[2].valid) - & (~self._bus_pipe[2].rw) - & (self._bus_pipe[2].addr >= start_addr) - & (self._bus_pipe[2].addr <= stop_addr) - ): - m.d.sync += self.bus_o.data.eq(read_port.data) + # Handle read ports + if self._mode in ["fpga_to_host", "bidirectional"]: + read_port = mem.read_port() + m.d.comb += read_port.en.eq(1) - def _handle_write_ports(self, m): - # These are given to the user - for i, mem in enumerate(self._mems): - write_port = mem.write_port() + # Throw BRAM operations into the front of the pipeline + with m.If( + (self.bus_i.valid) + & (~self.bus_i.rw) + & (self.bus_i.addr >= start_addr) + & (self.bus_i.addr <= stop_addr) + ): + m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) - m.d.comb += write_port.addr.eq(self.user_addr) - m.d.comb += write_port.data.eq(self.user_data_in[16 * i : 16 * (i + 1)]) - m.d.comb += write_port.en.eq(self.user_write_enable) + # Pull BRAM reads from the back of the pipeline + with m.If( + (self._bus_pipe[2].valid) + & (~self._bus_pipe[2].rw) + & (self._bus_pipe[2].addr >= start_addr) + & (self._bus_pipe[2].addr <= stop_addr) + ): + m.d.sync += self.bus_o.data.eq(read_port.data) + + def _tie_mems_to_user_logic(self, m): + # Handle write ports + if self._mode in ["fpga_to_host", "bidirectional"]: + for i, mem in enumerate(self._mems): + write_port = mem.write_port() + m.d.comb += write_port.addr.eq(self.user_addr) + m.d.comb += write_port.data.eq(self.user_data_in[16 * i : 16 * (i + 1)]) + m.d.comb += write_port.en.eq(self.user_write_enable) + + # Handle read ports + if self._mode in ["host_to_fpga", "bidirectional"]: + read_datas = [] + for i, mem in enumerate(self._mems): + read_port = mem.read_port() + m.d.comb += read_port.addr.eq(self.user_addr) + m.d.comb += read_port.en.eq(1) + read_datas.append(read_port.data) + + m.d.comb += self.user_data_out.eq(Cat(read_datas)) def elaborate(self, platform): m = Module() @@ -143,9 +164,14 @@ class MemoryCore(Elaboratable): n_full = self._width // 16 n_partial = self._width % 16 - self._mems = [Memory(width=16, depth=self._depth, init=[0]*self._depth) for _ in range(n_full)] + self._mems = [ + Memory(width=16, depth=self._depth, init=[0] * self._depth) + for _ in range(n_full) + ] if n_partial > 0: - self._mems += [Memory(width=n_partial, depth=self._depth, init=[0]*self._depth)] + self._mems += [ + Memory(width=n_partial, depth=self._depth, init=[0] * self._depth) + ] # Add memories as submodules for i, mem in enumerate(self._mems): @@ -160,8 +186,8 @@ class MemoryCore(Elaboratable): m.d.sync += self.bus_o.eq(self._bus_pipe[2]) - self._handle_read_ports(m) - self._handle_write_ports(m) + self._tie_mems_to_bus(m) + self._tie_mems_to_user_logic(m) return m def get_top_level_ports(self): diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 6afdd4c..02925c8 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -28,7 +28,8 @@ class MemoryCoreLoopbackTest(Elaboratable): return { "cores": { "mem_core": { - "type": "memory_read_only", + "type": "memory", + "mode": "fpga_to_host", "width": self.width, "depth": self.depth, }, From e2d52a6e2d2bafb3ce5b00ff112139b84a74cdf3 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 3 Mar 2024 02:14:12 -0800 Subject: [PATCH 64/89] add simulate decorator --- src/manta/memory_core.py | 89 +++++-- src/manta/utils.py | 46 +++- test/test_bridge_rx_sim.py | 44 ++-- test/test_bridge_tx_sim.py | 12 +- test/test_io_core_sim.py | 118 ++++----- test/test_logic_analyzer_fsm_sim.py | 370 +++++++++++++--------------- test/test_logic_analyzer_sim.py | 56 ++--- test/test_mem_core_sim.py | 176 ++++++++++--- test/test_source_bridge_sim.py | 54 ++-- test/test_uart_rx_sim.py | 24 +- test/test_uart_tx_sim.py | 16 +- 11 files changed, 579 insertions(+), 426 deletions(-) diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index e88a9ec..7e8e0a5 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -22,8 +22,8 @@ class MemoryCore(Elaboratable): self._base_addr = base_addr self._interface = interface - self._n_brams = ceil(self._width / 16) - self._max_addr = self._base_addr + (self._depth * self._n_brams) + self._n_mems = ceil(self._width / 16) + self._max_addr = self._base_addr + (self._depth * self._n_mems) # Bus Connections self.bus_i = Signal(InternalBus()) @@ -106,23 +106,43 @@ class MemoryCore(Elaboratable): start_addr = self._base_addr + (i * self._depth) stop_addr = start_addr + self._depth - 1 - # Handle write ports - if self._mode in ["host_to_fpga", "bidirectional"]: - pass - # write_port = mem.write_port() - # m.d.sync += write_port.data.eq(self.bus_i.data) - # m.d.sync += write_port.en.eq(self.bus_i.rw) - # m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr) + # # Handle write ports + # if self._mode in ["host_to_fpga", "bidirectional"]: + # write_port = mem.write_port() + # m.d.sync += write_port.data.eq(self.bus_i.data) + # m.d.sync += write_port.en.eq(self.bus_i.rw) + # m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr) - # Handle read ports - if self._mode in ["fpga_to_host", "bidirectional"]: + # # Handle read ports + # if self._mode in ["fpga_to_host", "bidirectional"]: + # read_port = mem.read_port() + # m.d.comb += read_port.en.eq(1) + + # # Throw BRAM operations into the front of the pipeline + # with m.If( + # (self.bus_i.valid) + # & (~self.bus_i.rw) + # & (self.bus_i.addr >= start_addr) + # & (self.bus_i.addr <= stop_addr) + # ): + # m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) + + # # Pull BRAM reads from the back of the pipeline + # with m.If( + # (self._bus_pipe[2].valid) + # & (~self._bus_pipe[2].rw) + # & (self._bus_pipe[2].addr >= start_addr) + # & (self._bus_pipe[2].addr <= stop_addr) + # ): + # m.d.sync += self.bus_o.data.eq(read_port.data) + + if self._mode == "fpga_to_host": read_port = mem.read_port() m.d.comb += read_port.en.eq(1) # Throw BRAM operations into the front of the pipeline with m.If( (self.bus_i.valid) - & (~self.bus_i.rw) & (self.bus_i.addr >= start_addr) & (self.bus_i.addr <= stop_addr) ): @@ -137,6 +157,47 @@ class MemoryCore(Elaboratable): ): m.d.sync += self.bus_o.data.eq(read_port.data) + elif self._mode == "host_to_fpga": + write_port = mem.write_port() + m.d.sync += write_port.en.eq(0) + + # Throw BRAM operations into the front of the pipeline + with m.If( + (self.bus_i.valid) + & (self.bus_i.addr >= start_addr) + & (self.bus_i.addr <= stop_addr) + ): + m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr) + m.d.sync += write_port.data.eq(self.bus_i.data) + m.d.sync += write_port.en.eq(self.bus_i.rw) + + elif self._mode == "bidirectional": + read_port = mem.read_port() + m.d.comb += read_port.en.eq(1) + + write_port = mem.write_port() + m.d.sync += write_port.en.eq(0) + + # Throw BRAM operations into the front of the pipeline + with m.If( + (self.bus_i.valid) + & (self.bus_i.addr >= start_addr) + & (self.bus_i.addr <= stop_addr) + ): + m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) + m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr) + m.d.sync += write_port.data.eq(self.bus_i.data) + m.d.sync += write_port.en.eq(self.bus_i.rw) + + # Pull BRAM reads from the back of the pipeline + with m.If( + (self._bus_pipe[2].valid) + & (~self._bus_pipe[2].rw) + & (self._bus_pipe[2].addr >= start_addr) + & (self._bus_pipe[2].addr <= stop_addr) + ): + m.d.sync += self.bus_o.data.eq(read_port.data) + def _tie_mems_to_user_logic(self, m): # Handle write ports if self._mode in ["fpga_to_host", "bidirectional"]: @@ -238,7 +299,7 @@ class MemoryCore(Elaboratable): bus_addrs = self._convert_user_to_bus_addr(addrs) datas = self._interface.read(bus_addrs) - data_chunks = split_into_chunks(datas, self._n_brams) + data_chunks = split_into_chunks(datas, self._n_mems) return [words_to_value(chunk) for chunk in data_chunks] def write(self, addrs, datas): @@ -264,5 +325,5 @@ class MemoryCore(Elaboratable): raise TypeError("Write data must all be integers.") bus_addrs = self._convert_user_to_bus_addr([addrs])[0] - bus_datas = [word for d in datas for word in value_to_words(d, self._n_brams)] + bus_datas = [word for d in datas for word in value_to_words(d, self._n_mems)] self._interface.write(bus_addrs, bus_datas) diff --git a/src/manta/utils.py b/src/manta/utils.py index 072ceb5..20dc6bc 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -83,22 +83,41 @@ def split_into_chunks(data, chunk_size): return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)] -def simulate(top, testbench, vcd_path=None): +def simulate(top): """ - Run a behavior simulation using Amaranth's built-in simulator `pysim`. Takes - the top-level module to simulate, the testbench process to run, and an optional - path to export a VCD file to. + A decorator for running behavioral simulation using Amaranth's built-in + simulator. Requires the top-level module in the simulation as an argument, + and automatically names VCD file containing the waveform dump with the name + of the function being decorated. """ - sim = Simulator(top) - sim.add_clock(1e-6) # 1 MHz - sim.add_sync_process(testbench) - if vcd_path is None: - sim.run() + def decorator(testbench): + def wrapper(*args, **kwargs): + sim = Simulator(top) + sim.add_clock(1e-6) # 1 MHz + sim.add_sync_process(testbench) - else: - with sim.write_vcd(vcd_path): - sim.run() + vcd_path = testbench.__name__ + ".vcd" + + with sim.write_vcd(vcd_path): + sim.run() + + return wrapper + + return decorator + + +# def simulate_decorator(testbench): +# def wrapper_accepting_arguments(top): +# sim = Simulator(top) +# sim.add_clock(1e-6) # 1 MHz +# sim.add_sync_process(testbench) + +# vcd_path = testbench.__name__ + ".vcd" +# with sim.write_vcd(vcd_path): +# sim.run() + +# return wrapper_accepting_arguments def verify_register(module, addr, expected_data): @@ -143,7 +162,10 @@ def write_register(module, addr, data): yield module.bus_i.rw.eq(1) yield module.bus_i.valid.eq(1) yield + yield module.bus_i.addr.eq(0) + yield module.bus_i.data.eq(0) yield module.bus_i.valid.eq(0) + yield module.bus_i.rw.eq(0) yield diff --git a/test/test_bridge_rx_sim.py b/test/test_bridge_rx_sim.py index c65a184..403f614 100644 --- a/test/test_bridge_rx_sim.py +++ b/test/test_bridge_rx_sim.py @@ -86,35 +86,29 @@ def verify_bad_bytes(bytes): yield bridge_rx.valid_i.eq(0) +@simulate(bridge_rx) def test_read_decode(): - def testbench(): - yield from verify_read_decoding(b"R0000\r\n", 0x0000) - yield from verify_read_decoding(b"R1234\r\n", 0x1234) - yield from verify_read_decoding(b"RBABE\r\n", 0xBABE) - yield from verify_read_decoding(b"R5678\n", 0x5678) - yield from verify_read_decoding(b"R9ABC\r", 0x9ABC) - - simulate(bridge_rx, testbench) + yield from verify_read_decoding(b"R0000\r\n", 0x0000) + yield from verify_read_decoding(b"R1234\r\n", 0x1234) + yield from verify_read_decoding(b"RBABE\r\n", 0xBABE) + yield from verify_read_decoding(b"R5678\n", 0x5678) + yield from verify_read_decoding(b"R9ABC\r", 0x9ABC) +@simulate(bridge_rx) def test_write_decode(): - def testbench(): - yield from verify_write_decoding(b"W12345678\r\n", 0x1234, 0x5678) - yield from verify_write_decoding(b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF) - yield from verify_write_decoding(b"WDEADBEEF\r", 0xDEAD, 0xBEEF) - yield from verify_write_decoding(b"WB0BACAFE\n", 0xB0BA, 0xCAFE) - - simulate(bridge_rx, testbench) + yield from verify_write_decoding(b"W12345678\r\n", 0x1234, 0x5678) + yield from verify_write_decoding(b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF) + yield from verify_write_decoding(b"WDEADBEEF\r", 0xDEAD, 0xBEEF) + yield from verify_write_decoding(b"WB0BACAFE\n", 0xB0BA, 0xCAFE) +@simulate(bridge_rx) def test_no_decode(): - def testbench(): - yield from verify_bad_bytes(b"RABC\r\n") - yield from verify_bad_bytes(b"R12345\r\n") - yield from verify_bad_bytes(b"M\r\n") - yield from verify_bad_bytes(b"W123456789101112131415161718191201222\r\n") - yield from verify_bad_bytes(b"RABCG\r\n") - yield from verify_bad_bytes(b"WABC[]()##*@\r\n") - yield from verify_bad_bytes(b"R\r\n") - - simulate(bridge_rx, testbench) + yield from verify_bad_bytes(b"RABC\r\n") + yield from verify_bad_bytes(b"R12345\r\n") + yield from verify_bad_bytes(b"M\r\n") + yield from verify_bad_bytes(b"W123456789101112131415161718191201222\r\n") + yield from verify_bad_bytes(b"RABCG\r\n") + yield from verify_bad_bytes(b"WABC[]()##*@\r\n") + yield from verify_bad_bytes(b"R\r\n") diff --git a/test/test_bridge_tx_sim.py b/test/test_bridge_tx_sim.py index 9a1568d..777c252 100644 --- a/test/test_bridge_tx_sim.py +++ b/test/test_bridge_tx_sim.py @@ -57,11 +57,9 @@ def verify_encoding(data, bytes): raise ValueError(f"Received {sent_bytes} instead of {bytes}.") +@simulate(bridge_tx) def test_some_random_values(): - def testbench(): - for i in sample(range(0xFFFF), k=5000): - expected = f"D{i:04X}\r\n".encode("ascii") - print(i) - yield from verify_encoding(i, expected) - - simulate(bridge_tx, testbench) + for i in sample(range(0xFFFF), k=5000): + expected = f"D{i:04X}\r\n".encode("ascii") + print(i) + yield from verify_encoding(i, expected) diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py index 3bda812..4edbd37 100644 --- a/test/test_io_core_sim.py +++ b/test/test_io_core_sim.py @@ -26,92 +26,82 @@ def pulse_strobe_register(): yield from write_register(io_core, strobe_addr, 0) +@simulate(io_core) def test_input_probe_buffer_initial_value(): - def testbench(): - # Verify all input probe buffers initialize to zero - for i in inputs: - addrs = io_core._memory_map[i.name]["addrs"] + # Verify all input probe buffers initialize to zero + for i in inputs: + addrs = io_core._memory_map[i.name]["addrs"] - for addr in addrs: - yield from verify_register(io_core, addr, 0) - - simulate(io_core, testbench) + for addr in addrs: + yield from verify_register(io_core, addr, 0) +@simulate(io_core) def test_output_probe_buffer_initial_value(): - def testbench(): - # Verify all output probe buffers initialize to the values in the config - for o in outputs: - addrs = io_core._memory_map[o.name]["addrs"] - datas = value_to_words(o.reset, len(addrs)) + # Verify all output probe buffers initialize to the values in the config + for o in outputs: + addrs = io_core._memory_map[o.name]["addrs"] + datas = value_to_words(o.reset, len(addrs)) - for addr, data in zip(addrs, datas): - yield from verify_register(io_core, addr, data) - - simulate(io_core, testbench) + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) +@simulate(io_core) def test_output_probes_are_writeable(): - def testbench(): - for o in outputs: - addrs = io_core._memory_map[o.name]["addrs"] - test_value = randint(0, (2**o.width) - 1) - datas = value_to_words(test_value, len(addrs)) + for o in outputs: + addrs = io_core._memory_map[o.name]["addrs"] + test_value = randint(0, (2**o.width) - 1) + datas = value_to_words(test_value, len(addrs)) - # write value to registers - for addr, data in zip(addrs, datas): - yield from write_register(io_core, addr, data) + # write value to registers + for addr, data in zip(addrs, datas): + yield from write_register(io_core, addr, data) - # read value back from registers - for addr, data in zip(addrs, datas): - yield from verify_register(io_core, addr, data) - - simulate(io_core, testbench) + # read value back from registers + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) +@simulate(io_core) def test_output_probes_update(): - def testbench(): - for o in outputs: - addrs = io_core._memory_map[o.name]["addrs"] - test_value = randint(0, (2**o.width) - 1) - datas = value_to_words(test_value, len(addrs)) + for o in outputs: + addrs = io_core._memory_map[o.name]["addrs"] + test_value = randint(0, (2**o.width) - 1) + datas = value_to_words(test_value, len(addrs)) - # write value to registers - for addr, data in zip(addrs, datas): - yield from write_register(io_core, addr, data) + # write value to registers + for addr, data in zip(addrs, datas): + yield from write_register(io_core, addr, data) - # pulse strobe register - yield from pulse_strobe_register() + # pulse strobe register + yield from pulse_strobe_register() - # check that outputs took updated value - value = yield (o) + # check that outputs took updated value + value = yield (o) - if value != test_value: - raise ValueError( - f"Output probe {o.name} took value {value} instead of {test_value} after pulsing strobe." - ) + if value != test_value: + raise ValueError( + f"Output probe {o.name} took value {value} instead of {test_value} after pulsing strobe." + ) - else: - print(f"Output probe {o.name} took value {value} after pulsing strobe.") - - simulate(io_core, testbench) + else: + print(f"Output probe {o.name} took value {value} after pulsing strobe.") +@simulate(io_core) def test_input_probes_update(): - def testbench(): - for i in inputs: - # set input probe value - test_value = randint(0, (2**i.width) - 1) - yield i.eq(test_value) + for i in inputs: + # set input probe value + test_value = randint(0, (2**i.width) - 1) + yield i.eq(test_value) - # pulse strobe register - yield from pulse_strobe_register() + # pulse strobe register + yield from pulse_strobe_register() - # check that values are as expected once read back - addrs = io_core._memory_map[i.name]["addrs"] - datas = value_to_words(test_value, len(addrs)) + # check that values are as expected once read back + addrs = io_core._memory_map[i.name]["addrs"] + datas = value_to_words(test_value, len(addrs)) - for addr, data in zip(addrs, datas): - yield from verify_register(io_core, addr, data) - - simulate(io_core, testbench) + for addr, data in zip(addrs, datas): + yield from verify_register(io_core, addr, data) diff --git a/test/test_logic_analyzer_fsm_sim.py b/test/test_logic_analyzer_fsm_sim.py index 7e7043c..fb04615 100644 --- a/test/test_logic_analyzer_fsm_sim.py +++ b/test/test_logic_analyzer_fsm_sim.py @@ -6,244 +6,230 @@ config = {"sample_depth": 8} fsm = LogicAnalyzerFSM(config, base_addr=0, interface=None) +@simulate(fsm) def test_signals_reset_correctly(): - def testbench(): - # Make sure pointers and write enable reset to zero - for sig in [fsm.write_pointer, fsm.read_pointer, fsm.write_enable]: - if (yield sig) != 0: - raise ValueError - - # Make sure state resets to IDLE - if (yield fsm.state != States.IDLE): + # Make sure pointers and write enable reset to zero + for sig in [fsm.write_pointer, fsm.read_pointer, fsm.write_enable]: + if (yield sig) != 0: raise ValueError - simulate(fsm, testbench) + # Make sure state resets to IDLE + if (yield fsm.state != States.IDLE): + raise ValueError +@simulate(fsm) def test_single_shot_no_wait_for_trigger(): - def testbench(): - # Configure and start FSM - yield fsm.trigger.eq(1) - yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) - yield fsm.trigger_location.eq(4) - yield fsm.request_start.eq(1) + # Configure and start FSM + yield fsm.trigger.eq(1) + yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.trigger_location.eq(4) + yield fsm.request_start.eq(1) - # Wait until write_enable is asserted - while not (yield fsm.write_enable): - yield - - # Wait 8 clock cycles for capture to complete - for i in range(8): - # Make sure that read_pointer does not increase - if (yield fsm.read_pointer) != 0: - raise ValueError - - # Make sure that write_pointer increases by one each cycle - if (yield fsm.write_pointer) != i: - raise ValueError - - yield - - # Wait one clock cycle (to let BRAM contents cycle in) + # Wait until write_enable is asserted + while not (yield fsm.write_enable): yield - # Check that write_pointer points to the end of memory - if (yield fsm.write_pointer) != 7: + # Wait 8 clock cycles for capture to complete + for i in range(8): + # Make sure that read_pointer does not increase + if (yield fsm.read_pointer) != 0: raise ValueError - # Check that state is CAPTURED - if (yield fsm.state) != States.CAPTURED: + # Make sure that write_pointer increases by one each cycle + if (yield fsm.write_pointer) != i: raise ValueError - simulate(fsm, testbench, "single_shot_no_wait_for_trigger.vcd") + yield + + # Wait one clock cycle (to let BRAM contents cycle in) + yield + + # Check that write_pointer points to the end of memory + if (yield fsm.write_pointer) != 7: + raise ValueError + + # Check that state is CAPTURED + if (yield fsm.state) != States.CAPTURED: + raise ValueError +@simulate(fsm) def test_single_shot_wait_for_trigger(): - def testbench(): - # Configure and start FSM - yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) - yield fsm.trigger_location.eq(4) - yield fsm.request_start.eq(1) - yield - yield + # Configure and start FSM + yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.trigger_location.eq(4) + yield fsm.request_start.eq(1) + yield + yield - # Check that write_enable is asserted a cycle after request_start - if not (yield fsm.write_enable): - raise ValueError + # Check that write_enable is asserted a cycle after request_start + if not (yield fsm.write_enable): + raise ValueError - # Wait 4 clock cycles to get to IN_POSITION - for i in range(4): - rp = yield fsm.read_pointer - wp = yield fsm.write_pointer - - # Make sure that read_pointer does not increase - if rp != 0: - raise ValueError - - # Make sure that write_pointer increases by one each cycle - if wp != i: - raise ValueError - - yield - - # Wait a few cycles before triggering - for _ in range(10): - yield - - # Provide the trigger, and check that the capture completes 4 cycles later - yield fsm.trigger.eq(1) - yield - - for i in range(4): - yield - - # Wait one clock cycle (to let BRAM contents cycle in) - yield - - # Check that write_pointer points to the end of memory + # Wait 4 clock cycles to get to IN_POSITION + for i in range(4): rp = yield fsm.read_pointer wp = yield fsm.write_pointer - if (wp + 1) % config["sample_depth"] != rp: - raise ValueError - # Check that state is CAPTURED - if (yield fsm.state) != States.CAPTURED: - raise ValueError - - simulate(fsm, testbench, "single_shot_wait_for_trigger.vcd") - - -def test_immediate(): - def testbench(): - # Configure and start FSM - yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE) - yield fsm.request_start.eq(1) - yield - yield - - # Check that write_enable is asserted a cycle after request_start - if not (yield fsm.write_enable): - raise ValueError - - for i in range(config["sample_depth"]): - rp = yield fsm.read_pointer - wp = yield fsm.write_pointer - - if rp != 0: - raise ValueError - - if wp != i: - raise ValueError - - yield - - # Wait one clock cycle (to let BRAM contents cycle in) - yield - - # Check that write_pointer points to the end of memory - rp = yield fsm.read_pointer - wp = yield fsm.write_pointer + # Make sure that read_pointer does not increase if rp != 0: raise ValueError - if wp != 7: + + # Make sure that write_pointer increases by one each cycle + if wp != i: raise ValueError - # Check that state is CAPTURED - if (yield fsm.state) != States.CAPTURED: + yield + + # Wait a few cycles before triggering + for _ in range(10): + yield + + # Provide the trigger, and check that the capture completes 4 cycles later + yield fsm.trigger.eq(1) + yield + + for i in range(4): + yield + + # Wait one clock cycle (to let BRAM contents cycle in) + yield + + # Check that write_pointer points to the end of memory + rp = yield fsm.read_pointer + wp = yield fsm.write_pointer + if (wp + 1) % config["sample_depth"] != rp: + raise ValueError + + # Check that state is CAPTURED + if (yield fsm.state) != States.CAPTURED: + raise ValueError + + +@simulate(fsm) +def test_immediate(): + # Configure and start FSM + yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE) + yield fsm.request_start.eq(1) + yield + yield + + # Check that write_enable is asserted a cycle after request_start + if not (yield fsm.write_enable): + raise ValueError + + for i in range(config["sample_depth"]): + rp = yield fsm.read_pointer + wp = yield fsm.write_pointer + + if rp != 0: raise ValueError - simulate(fsm, testbench, "immediate.vcd") + if wp != i: + raise ValueError + + yield + + # Wait one clock cycle (to let BRAM contents cycle in) + yield + + # Check that write_pointer points to the end of memory + rp = yield fsm.read_pointer + wp = yield fsm.write_pointer + if rp != 0: + raise ValueError + if wp != 7: + raise ValueError + + # Check that state is CAPTURED + if (yield fsm.state) != States.CAPTURED: + raise ValueError +@simulate(fsm) def test_incremental(): - def testbench(): - # Configure and start FSM - yield fsm.trigger_mode.eq(TriggerModes.INCREMENTAL) - yield fsm.request_start.eq(1) - yield - yield + # Configure and start FSM + yield fsm.trigger_mode.eq(TriggerModes.INCREMENTAL) + yield fsm.request_start.eq(1) + yield + yield - # Check that write_enable is asserted on the same edge as request_start - if not (yield fsm.write_enable): - raise ValueError - - for _ in range(10): - for _ in range(3): - yield - - yield fsm.trigger.eq(1) - yield - yield fsm.trigger.eq(0) - yield - - # Check that state is CAPTURED - if (yield fsm.state) != States.CAPTURED: - raise ValueError - - simulate(fsm, testbench, "incremental.vcd") - - -def test_single_shot_write_enable(): - def testbench(): - # Configure FSM - yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) - yield fsm.trigger_location.eq(4) - yield - - # Make sure write is not enabled before starting the FSM - if (yield fsm.write_enable): - raise ValueError - - # Start the FSM, ensure write enable is asserted throughout the capture - yield fsm.request_start.eq(1) - yield - yield - - for _ in range(config["sample_depth"]): - if not (yield fsm.write_enable): - raise ValueError + # Check that write_enable is asserted on the same edge as request_start + if not (yield fsm.write_enable): + raise ValueError + for _ in range(10): + for _ in range(3): yield yield fsm.trigger.eq(1) yield + yield fsm.trigger.eq(0) + yield - for _ in range(4): - if not (yield fsm.write_enable): - raise ValueError + # Check that state is CAPTURED + if (yield fsm.state) != States.CAPTURED: + raise ValueError - yield - # Make sure write_enable is deasserted after - if (yield fsm.write_enable): +@simulate(fsm) +def test_single_shot_write_enable(): + # Configure FSM + yield fsm.trigger_mode.eq(TriggerModes.SINGLE_SHOT) + yield fsm.trigger_location.eq(4) + yield + + # Make sure write is not enabled before starting the FSM + if (yield fsm.write_enable): + raise ValueError + + # Start the FSM, ensure write enable is asserted throughout the capture + yield fsm.request_start.eq(1) + yield + yield + + for _ in range(config["sample_depth"]): + if not (yield fsm.write_enable): raise ValueError - simulate(fsm, testbench, "single_shot_write_enable.vcd") + yield + + yield fsm.trigger.eq(1) + yield + + for _ in range(4): + if not (yield fsm.write_enable): + raise ValueError + + yield + + # Make sure write_enable is deasserted after + if (yield fsm.write_enable): + raise ValueError +@simulate(fsm) def test_immediate_write_enable(): - def testbench(): - # Configure FSM - yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE) - yield + # Configure FSM + yield fsm.trigger_mode.eq(TriggerModes.IMMEDIATE) + yield - # Make sure write is not enabled before starting the FSM - if (yield fsm.write_enable): + # Make sure write is not enabled before starting the FSM + if (yield fsm.write_enable): + raise ValueError + + # Start the FSM, ensure write enable is asserted throughout the capture + yield fsm.request_start.eq(1) + yield + yield + + for _ in range(config["sample_depth"]): + if not (yield fsm.write_enable): raise ValueError - # Start the FSM, ensure write enable is asserted throughout the capture - yield fsm.request_start.eq(1) - yield yield - for _ in range(config["sample_depth"]): - if not (yield fsm.write_enable): - raise ValueError - - yield - - # Make sure write_enable is deasserted after - if (yield fsm.write_enable): - raise ValueError - - simulate(fsm, testbench, "immediate_write_enable.vcd") + # Make sure write_enable is deasserted after + if (yield fsm.write_enable): + raise ValueError diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index f5c7ea2..eb240a5 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -61,42 +61,40 @@ def set_probe(name, value): yield probe.eq(value) +@simulate(la) def test_single_shot_capture(): - def testbench(): - # # ok nice what happens if we try to run the core, which includes: - yield from set_fsm_register("request_stop", 1) - yield from set_fsm_register("request_stop", 0) + # # ok nice what happens if we try to run the core, which includes: + yield from set_fsm_register("request_stop", 1) + yield from set_fsm_register("request_stop", 0) - # setting triggers - yield from set_trig_blk_register("curly_op", Operations.EQ) - yield from set_trig_blk_register("curly_arg", 4) + # setting triggers + yield from set_trig_blk_register("curly_op", Operations.EQ) + yield from set_trig_blk_register("curly_arg", 4) - # setting trigger mode - yield from set_fsm_register("trigger_mode", 0) + # setting trigger mode + yield from set_fsm_register("trigger_mode", 0) - # setting trigger location - yield from set_fsm_register("trigger_location", 511) + # setting trigger location + yield from set_fsm_register("trigger_location", 511) - # starting capture - yield from set_fsm_register("request_start", 1) - yield from set_fsm_register("request_start", 0) + # starting capture + yield from set_fsm_register("request_start", 1) + yield from set_fsm_register("request_start", 0) - # wait a few hundred clock cycles, see what happens - for _ in range(700): - yield + # wait a few hundred clock cycles, see what happens + for _ in range(700): + yield - # provide the trigger condition - yield from set_probe("curly", 4) + # provide the trigger condition + yield from set_probe("curly", 4) - for _ in range(700): - yield + for _ in range(700): + yield - # dump sample memory contents - yield from write_register(la, 0, 0) - yield from write_register(la, 0, 1) - yield from write_register(la, 0, 0) + # dump sample memory contents + yield from write_register(la, 0, 0) + yield from write_register(la, 0, 1) + yield from write_register(la, 0, 0) - for addr in range(la.get_max_addr()): - yield from print_data_at_addr(addr) - - simulate(la, testbench, "la_core.vcd") + for addr in range(la.get_max_addr()): + yield from print_data_at_addr(addr) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index fce9800..dd8d430 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -1,44 +1,158 @@ from manta.memory_core import MemoryCore from manta.utils import * -from random import randint, sample +from random import randint, sample, choice + +width = 18 +depth = 512 +base_addr = 0 +mem_core = MemoryCore( + mode="bidirectional", width=width, depth=depth, base_addr=base_addr, interface=None +) + +max_addr = mem_core.get_max_addr() +bus_addrs = list(range(base_addr, max_addr)) # include the endpoint! +user_addrs = list(range(depth)) -def fill_mem_from_user_port(mem_core, depth): - for i in range(depth): - yield mem_core.user_addr.eq(i) - yield mem_core.user_data_in.eq(i) - yield mem_core.user_write_enable.eq(1) +@simulate(mem_core) +def test_bidirectional(): + # make sure each address on the bus side contains zero + for addr in bus_addrs: + yield from verify_register(mem_core, addr, 0) + + # make sure each address on the user side contains zero + for addr in user_addrs: + yield from verify_user_side(mem_core, addr, 0) + + # write then immediately read + for addr in bus_addrs: + # this part is a little hard to check since we might have a + # memory at the end of the address space that's less than + # 16-bits wide. so we'll have to calculate how wide our + # memory is + + n_full = width // 16 + if addr < base_addr + (n_full * depth): + data_width = 16 + else: + data_width = width % 16 + + data = randint(0, (2**data_width) - 1) + yield from write_register(mem_core, addr, data) + yield + yield + yield + yield + yield from verify_register(mem_core, addr, data) + yield + yield + yield + yield yield + # write-write-write then read-read-read + model = {} + for addr in sample(bus_addrs, len(bus_addrs)): + n_full = width // 16 + if addr < base_addr + (n_full * depth): + data_width = 16 + else: + data_width = width % 16 + + data = randint(0, (2**data_width) - 1) + model[addr] = data + yield from write_register(mem_core, addr, data) + yield + yield + yield + yield + + for addr in sample(bus_addrs, len(bus_addrs)): + yield from verify_register(mem_core, addr, model[addr]) + yield + yield + yield + yield + + # random reads and writes in random orders + for _ in range(5): + for addr in sample(bus_addrs, len(bus_addrs)): + + operation = choice(["read", "write"]) + if operation == "read": + yield from verify_register(mem_core, addr, model[addr]) + yield + yield + yield + yield + yield + yield + + elif operation == "write": + n_full = width // 16 + + if addr < base_addr + (n_full * depth): + data_width = 16 + else: + data_width = width % 16 + + data = randint(0, (2**data_width) - 1) + model[addr] = data + + yield from write_register(mem_core, addr, data) + yield + yield + yield + yield + yield + yield + + +def verify_user_side(mem_core, addr, expected_data): + yield mem_core.user_addr.eq(addr) yield mem_core.user_write_enable.eq(0) yield - -def verify_mem_core(width, depth, base_addr): - mem_core = MemoryCore("fpga_to_host", width, depth, base_addr, interface=None) - - def testbench(): - yield from fill_mem_from_user_port(mem_core, depth) - - # Read from address sequentially - for i in range(depth): - yield from verify_register(mem_core, i + base_addr, i % (2**width)) - - # Read from addresses randomly - for i in sample(range(depth), k=depth): - yield from verify_register(mem_core, i + base_addr, i % (2**width)) - - simulate(mem_core, testbench) + data = yield (mem_core.user_data_out) + if data != expected_data: + raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") -def test_sweep_core_widths(): - for i in range(1, 64): - verify_mem_core(i, 128, 0) +# def fill_mem_from_user_port(mem_core, depth): +# for i in range(depth): +# yield mem_core.user_addr.eq(i) +# yield mem_core.user_data_in.eq(i) +# yield mem_core.user_write_enable.eq(1) +# yield + +# yield mem_core.user_write_enable.eq(0) +# yield -def test_random_cores(): - for _ in range(5): - width = randint(0, 512) - depth = randint(0, 1024) - base_addr = randint(0, 2**16 - 1 - depth) - verify_mem_core(width, depth, base_addr) +# def verify_mem_core(width, depth, base_addr): +# mem_core = MemoryCore("bidirectional", width, depth, base_addr, interface=None) + +# def testbench(): +# yield from fill_mem_from_user_port(mem_core, depth) + +# # Read from address sequentially +# for i in range(depth): +# yield from verify_register(mem_core, i + base_addr, i % (2**width)) + +# # Read from addresses randomly +# for i in sample(range(depth), k=depth): +# yield from verify_register(mem_core, i + base_addr, i % (2**width)) + +# simulate(mem_core, testbench) + +# def test_sweep_core_widths(): +# for i in range(1, 64): +# verify_mem_core(i, 128, 0) + + +# def test_random_cores(): +# for _ in range(5): +# width = randint(0, 512) +# depth = randint(0, 1024) +# base_addr = randint(0, 2**16 - 1 - depth) +# verify_mem_core(width, depth, base_addr) diff --git a/test/test_source_bridge_sim.py b/test/test_source_bridge_sim.py index 031dec8..b3b03ef 100644 --- a/test/test_source_bridge_sim.py +++ b/test/test_source_bridge_sim.py @@ -6,34 +6,32 @@ from manta.utils import * source_bridge = UDPSourceBridge() +@simulate(source_bridge) def test_normie_ops(): - def testbench(): - yield source_bridge.data_i.eq(0) - yield source_bridge.last_i.eq(0) - yield source_bridge.valid_i.eq(0) - yield - yield + yield source_bridge.data_i.eq(0) + yield source_bridge.last_i.eq(0) + yield source_bridge.valid_i.eq(0) + yield + yield - yield source_bridge.data_i.eq(0x0000_0001) - yield source_bridge.valid_i.eq(1) - yield - yield source_bridge.data_i.eq(0x1234_5678) - yield - yield source_bridge.valid_i.eq(0) - yield - yield + yield source_bridge.data_i.eq(0x0000_0001) + yield source_bridge.valid_i.eq(1) + yield + yield source_bridge.data_i.eq(0x1234_5678) + yield + yield source_bridge.valid_i.eq(0) + yield + yield - yield source_bridge.valid_i.eq(1) - yield source_bridge.data_i.eq(0x0000_0001) - yield - yield source_bridge.data_i.eq(0x90AB_CDEF) - yield - yield source_bridge.data_i.eq(0x0000_0000) - yield - yield source_bridge.data_i.eq(0x1234_5678) - yield - yield source_bridge.valid_i.eq(0) - yield - yield - - simulate(source_bridge, testbench, "source_bridge.vcd") + yield source_bridge.valid_i.eq(1) + yield source_bridge.data_i.eq(0x0000_0001) + yield + yield source_bridge.data_i.eq(0x90AB_CDEF) + yield + yield source_bridge.data_i.eq(0x0000_0000) + yield + yield source_bridge.data_i.eq(0x1234_5678) + yield + yield source_bridge.valid_i.eq(0) + yield + yield diff --git a/test/test_uart_rx_sim.py b/test/test_uart_rx_sim.py index 40111aa..23c9f43 100644 --- a/test/test_uart_rx_sim.py +++ b/test/test_uart_rx_sim.py @@ -43,23 +43,19 @@ def verify_receive(data): raise ValueError("Failed to assert valid!") +@simulate(uart_rx) def test_all_possible_bytes(): - def testbench(): - yield uart_rx.rx.eq(1) - yield + yield uart_rx.rx.eq(1) + yield - for i in range(0xFF): - yield from verify_receive(i) - - simulate(uart_rx, testbench) + for i in range(0xFF): + yield from verify_receive(i) +@simulate(uart_rx) def test_bytes_random_sample(): - def testbench(): - yield uart_rx.rx.eq(1) - yield + yield uart_rx.rx.eq(1) + yield - for i in sample(range(0xFF), k=0xFF): - yield from verify_receive(i) - - simulate(uart_rx, testbench) + for i in sample(range(0xFF), k=0xFF): + yield from verify_receive(i) diff --git a/test/test_uart_tx_sim.py b/test/test_uart_tx_sim.py index 8b07aa4..63bd373 100644 --- a/test/test_uart_tx_sim.py +++ b/test/test_uart_tx_sim.py @@ -41,17 +41,13 @@ def verify_bit_sequence(byte): raise ValueError("Done not asserted at end of transmission!") +@simulate(uart_tx) def test_all_possible_bytes(): - def testbench(): - for i in range(0xFF): - yield from verify_bit_sequence(i) - - simulate(uart_tx, testbench) + for i in range(0xFF): + yield from verify_bit_sequence(i) +@simulate(uart_tx) def test_bytes_random_sample(): - def testbench(): - for i in sample(range(0xFF), k=0xFF): - yield from verify_bit_sequence(i) - - simulate(uart_tx, testbench) + for i in sample(range(0xFF), k=0xFF): + yield from verify_bit_sequence(i) From 11022f474ddc71006513c8a88ccad7f3d63d5afa Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 3 Mar 2024 13:30:54 -0800 Subject: [PATCH 65/89] refactor Memory Core simulation into test class --- test/test_mem_core_sim.py | 235 ++++++++++++++++---------------------- 1 file changed, 98 insertions(+), 137 deletions(-) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index dd8d430..9618687 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -2,148 +2,109 @@ from manta.memory_core import MemoryCore from manta.utils import * from random import randint, sample, choice -width = 18 -depth = 512 -base_addr = 0 +class MemoryCoreTests(): + def __init__(self, mem_core): + self.mem_core = mem_core + self.base_addr = mem_core._base_addr + self.max_addr = mem_core.get_max_addr() + self.width = self.mem_core._width + self.depth = self.mem_core._depth + + self.bus_addrs = list(range(self.base_addr, self.max_addr)) # include the endpoint! + self.user_addrs = list(range(self.mem_core._depth)) + self.model = {} + + def check_each_address_on_bus_side_contains_zero(self): + for addr in self.bus_addrs: + yield from self.verify_bus_side(addr, 0) + + def check_each_address_on_user_side_contains_zero(self): + for addr in self.user_addrs: + yield from self.verify_user_side(addr, 0) + + def check_write_then_immediately_read_bus_side(self): + for addr in self.bus_addrs: + # this part is a little hard to check since we might have a + # memory at the end of the address space that's less than + # 16-bits wide. so we'll have to calculate how wide our + # memory is + + data_width = self.get_data_width(addr) + data = randint(0, (2**data_width) - 1) + + yield from self.write_bus_side(addr, data) + yield from self.verify_bus_side(addr, data) + + def check_multiple_writes_then_multiple_reads(self): + # write-write-write then read-read-read + for addr in sample(self.bus_addrs, len(self.bus_addrs)): + data_width = self.get_data_width(addr) + data = randint(0, (2**data_width) - 1) + + self.model[addr] = data + yield from self.write_bus_side(addr, data) + + for addr in sample(self.bus_addrs, len(self.bus_addrs)): + yield from self.verify_bus_side(addr, self.model[addr]) + + def check_random_reads_random_writes_random_orders(self): + # random reads and writes in random orders + for _ in range(5): + for addr in sample(self.bus_addrs, len(self.bus_addrs)): + + operation = choice(["read", "write"]) + if operation == "read": + yield from self.verify_bus_side(addr, self.model[addr]) + + elif operation == "write": + data_width = self.get_data_width(addr) + data = randint(0, (2**data_width) - 1) + self.model[addr] = data + yield from self.write_bus_side(addr, data) + + def get_data_width(self, addr): + n_full = self.width // 16 + if addr < self.base_addr + (n_full * self.depth): + return 16 + else: + return self.width % 16 + + def verify_bus_side(self, addr, expected_data): + yield from verify_register(self.mem_core, addr, expected_data) + for _ in range(4): + yield + + def write_bus_side(self, addr, data): + yield from write_register(self.mem_core, addr, data) + for _ in range(4): + yield + + def verify_user_side(self, addr, expected_data): + yield self.mem_core.user_addr.eq(addr) + yield self.mem_core.user_write_enable.eq(0) + yield + + data = yield (self.mem_core.user_data_out) + if data != expected_data: + raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") + mem_core = MemoryCore( - mode="bidirectional", width=width, depth=depth, base_addr=base_addr, interface=None + mode="bidirectional", + width=23, + depth=512, + base_addr=0, + interface=None, ) -max_addr = mem_core.get_max_addr() -bus_addrs = list(range(base_addr, max_addr)) # include the endpoint! -user_addrs = list(range(depth)) - +tests = MemoryCoreTests(mem_core) @simulate(mem_core) -def test_bidirectional(): - # make sure each address on the bus side contains zero - for addr in bus_addrs: - yield from verify_register(mem_core, addr, 0) - - # make sure each address on the user side contains zero - for addr in user_addrs: - yield from verify_user_side(mem_core, addr, 0) - - # write then immediately read - for addr in bus_addrs: - # this part is a little hard to check since we might have a - # memory at the end of the address space that's less than - # 16-bits wide. so we'll have to calculate how wide our - # memory is - - n_full = width // 16 - if addr < base_addr + (n_full * depth): - data_width = 16 - else: - data_width = width % 16 - - data = randint(0, (2**data_width) - 1) - yield from write_register(mem_core, addr, data) - yield - yield - yield - yield - yield from verify_register(mem_core, addr, data) - yield - yield - yield - yield - yield - - # write-write-write then read-read-read - model = {} - for addr in sample(bus_addrs, len(bus_addrs)): - n_full = width // 16 - if addr < base_addr + (n_full * depth): - data_width = 16 - else: - data_width = width % 16 - - data = randint(0, (2**data_width) - 1) - model[addr] = data - yield from write_register(mem_core, addr, data) - yield - yield - yield - yield - - for addr in sample(bus_addrs, len(bus_addrs)): - yield from verify_register(mem_core, addr, model[addr]) - yield - yield - yield - yield - - # random reads and writes in random orders - for _ in range(5): - for addr in sample(bus_addrs, len(bus_addrs)): - - operation = choice(["read", "write"]) - if operation == "read": - yield from verify_register(mem_core, addr, model[addr]) - yield - yield - yield - yield - yield - yield - - elif operation == "write": - n_full = width // 16 - - if addr < base_addr + (n_full * depth): - data_width = 16 - else: - data_width = width % 16 - - data = randint(0, (2**data_width) - 1) - model[addr] = data - - yield from write_register(mem_core, addr, data) - yield - yield - yield - yield - yield - yield - - -def verify_user_side(mem_core, addr, expected_data): - yield mem_core.user_addr.eq(addr) - yield mem_core.user_write_enable.eq(0) - yield - - data = yield (mem_core.user_data_out) - if data != expected_data: - raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") - - -# def fill_mem_from_user_port(mem_core, depth): -# for i in range(depth): -# yield mem_core.user_addr.eq(i) -# yield mem_core.user_data_in.eq(i) -# yield mem_core.user_write_enable.eq(1) -# yield - -# yield mem_core.user_write_enable.eq(0) -# yield - - -# def verify_mem_core(width, depth, base_addr): -# mem_core = MemoryCore("bidirectional", width, depth, base_addr, interface=None) - -# def testbench(): -# yield from fill_mem_from_user_port(mem_core, depth) - -# # Read from address sequentially -# for i in range(depth): -# yield from verify_register(mem_core, i + base_addr, i % (2**width)) - -# # Read from addresses randomly -# for i in sample(range(depth), k=depth): -# yield from verify_register(mem_core, i + base_addr, i % (2**width)) - -# simulate(mem_core, testbench) +def test_bidirectional_testbench(): + yield from tests.check_each_address_on_bus_side_contains_zero() + yield from tests.check_each_address_on_user_side_contains_zero() + yield from tests.check_write_then_immediately_read_bus_side() + yield from tests.check_multiple_writes_then_multiple_reads() + yield from tests.check_random_reads_random_writes_random_orders() # def test_sweep_core_widths(): # for i in range(1, 64): From 25ebae42e206c575a5e5e93dd2a126242117fb98 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 3 Mar 2024 13:57:52 -0800 Subject: [PATCH 66/89] add GateMate ILA to alternatives --- doc/alternatives.md | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/doc/alternatives.md b/doc/alternatives.md index 44f998d..8008edf 100644 --- a/doc/alternatives.md +++ b/doc/alternatives.md @@ -1,4 +1,4 @@ -There's quite a few FPGA debugging tools out there, and it may happen that your needs are better met by another tool. This section aims to provide a list of alternatives, in hopes that you're able to be confident in your debugging flow. +There's quite a few FPGA debugging tools out there, and it may happen that your needs are better met by another tool! This section aims to provide a list of alternatives, in hopes that you're able to be confident in your debugging flow. ## Open Source Tools @@ -9,6 +9,12 @@ An embedded logic analyzer written in Migen, primarily for use in LiteX SoC desi - [Source Code](https://github.com/enjoy-digital/litescope) - [Documentation](https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC) +### GateMate ILA + +An embedded logic analyzer written in Verilog, targeting the GateMate FPGA family from Colonge Chip and the Yosys/NextPNR toolchain. Communication between the host and FPGA is accomplished with SPI, via a FT232 or FT2232 used as a USB-SPI adapter. GateMate is inteneded to be used with GTKWave, so the tool generates `.gtkw` files in addition to VCD files. + +- [Source Code](https://github.com/colognechip/gatemate_ila) + ### ZipCPU Debugger A set of embedded debugging modules written by Dan Gisselquist of ZipCPU fame. Communication between the host and FPGA is accomplished with UART, and control of the debugger is performed with a C++ API on the host. A wishbone interface is provided on the FPGA side to connect to other Wishbone-based debugging tools that can provide control of user registers, block RAM, and an embedded logic analyzer. Supports dumping of signals to a VCD file. From b729deb144f1414f81e89fc8020bfc3dcf48cbf2 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 3 Mar 2024 18:31:11 -0800 Subject: [PATCH 67/89] hardcode device paths in hardware tests --- test/test_io_core_hw.py | 6 ++++-- test/test_logic_analyzer_hw.py | 6 ++++-- test/test_mem_core_hw.py | 5 +++-- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 13f29c6..6715728 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -143,9 +143,11 @@ class IOCoreLoopbackTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_output_probe_initial_values_xilinx(): - IOCoreLoopbackTest(Nexys4DDRPlatform(), "/dev/ttyUSB1").verify() + port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0" + IOCoreLoopbackTest(Nexys4DDRPlatform(), port).verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_output_probe_initial_values_ice40(): - IOCoreLoopbackTest(ICEStickPlatform(), "/dev/ttyUSB2").verify() + port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0" + IOCoreLoopbackTest(ICEStickPlatform(), port).verify() diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index d1dd695..8a25335 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -78,9 +78,11 @@ class LogicAnalyzerCounterTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_logic_analyzer_core_xilinx(): - LogicAnalyzerCounterTest(Nexys4DDRPlatform(), "/dev/ttyUSB1").verify() + port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0" + LogicAnalyzerCounterTest(Nexys4DDRPlatform(), port).verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_logic_analyzer_core_ice40(): - LogicAnalyzerCounterTest(ICEStickPlatform(), "/dev/ttyUSB2").verify() + port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0" + LogicAnalyzerCounterTest(ICEStickPlatform(), port).verify() diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 02925c8..18070ee 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -112,12 +112,13 @@ class MemoryCoreLoopbackTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_mem_core_xilinx(): - MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, "/dev/ttyUSB1").verify() + port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0" + MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, port).verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_mem_core_ice40(): - port = "/dev/ttyUSB2" + port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0" MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 2, port).verify() MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 512, port).verify() MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 1024, port).verify() From be79ba28b559b4b73d2eb43a89fcbcc85942f95a Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 3 Mar 2024 18:53:08 -0800 Subject: [PATCH 68/89] define ABC for cores to inherit from --- src/manta/io_core.py | 25 ++++++---------- src/manta/logic_analyzer/__init__.py | 25 ++++++---------- src/manta/logic_analyzer/fsm.py | 2 +- src/manta/logic_analyzer/trigger_block.py | 2 +- src/manta/manta.py | 4 +-- src/manta/memory_core.py | 25 ++++++---------- src/manta/utils.py | 35 +++++++++++++++++++++-- test/test_logic_analyzer_sim.py | 2 +- test/test_mem_core_sim.py | 16 ++++++++--- 9 files changed, 77 insertions(+), 59 deletions(-) diff --git a/src/manta/io_core.py b/src/manta/io_core.py index 63d6df5..d4b7add 100644 --- a/src/manta/io_core.py +++ b/src/manta/io_core.py @@ -3,7 +3,7 @@ from manta.utils import * from math import ceil -class IOCore(Elaboratable): +class IOCore(MantaCore): """ A module for setting and getting the values of registers of arbitrary size on a FPGA. @@ -34,6 +34,14 @@ class IOCore(Elaboratable): self._make_memory_map() + @property + def top_level_ports(self): + return self._inputs + self._outputs + + @property + def max_addr(self): + return self._max_addr + @classmethod def from_config(cls, config, base_addr, interface): inputs = config.get("inputs", {}) @@ -173,21 +181,6 @@ class IOCore(Elaboratable): return m - def get_top_level_ports(self): - """ - Return the Amaranth signals that should be included as ports in the - top-level Manta module. - """ - return self._inputs + self._outputs - - def get_max_addr(self): - """ - Return the maximum addresses in memory used by the core. The address - space used by the core extends from `base_addr` to the number returned - by this function (including the endpoints). - """ - return self._max_addr - def set_probe(self, name, value): """ Set the value of an output probe on the FPGA. The value may be either diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 19e3a04..2276a6a 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -6,7 +6,7 @@ from manta.logic_analyzer.fsm import LogicAnalyzerFSM, States, TriggerModes from manta.logic_analyzer.playback import LogicAnalyzerPlayback -class LogicAnalyzerCore(Elaboratable): +class LogicAnalyzerCore(MantaCore): """ A module for generating a logic analyzer on the FPGA, with configurable triggers, trigger position, and trigger modes. @@ -44,6 +44,14 @@ class LogicAnalyzerCore(Elaboratable): interface=interface, ) + @property + def max_addr(self): + return self._sample_mem.max_addr + + @property + def top_level_ports(self): + return self._probes + def _check_config(self): # Check for unrecognized options valid_options = [ @@ -176,21 +184,6 @@ class LogicAnalyzerCore(Elaboratable): return m - def get_top_level_ports(self): - """ - Return the Amaranth signals that should be included as ports in the - top-level Manta module. - """ - return self._probes - - def get_max_addr(self): - """ - Return the maximum addresses in memory used by the core. The address - space used by the core extends from `base_addr` to the number returned - by this function (including the endpoints). - """ - return self._sample_mem.get_max_addr() - def capture(self, verbose=False): """ Performs a capture, recording the state of all input probes to the diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index bfe4183..4853963 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -66,7 +66,7 @@ class LogicAnalyzerFSM(Elaboratable): space used by the core extends from `base_addr` to the number returned by this function (including the endpoints). """ - return self.registers.get_max_addr() + return self.registers.max_addr def elaborate(self, platform): m = Module() diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index ff67b45..9db01a2 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -34,7 +34,7 @@ class LogicAnalyzerTriggerBlock(Elaboratable): space used by the core extends from `base_addr` to the number returned by this function (including the endpoints). """ - return self.registers.get_max_addr() + return self.registers.max_addr def clear_triggers(self): # Reset all triggers to disabled with no argument diff --git a/src/manta/manta.py b/src/manta/manta.py index 1a3830b..b5ea59e 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -97,13 +97,13 @@ class Manta(Elaboratable): core = MemoryCore.from_config(attrs, base_addr, self.interface) # Make sure we're not out of address space - if core.get_max_addr() > (2**16) - 1: + if core.max_addr > (2**16) - 1: raise ValueError( f"Ran out of address space to allocate to core {name}." ) # Make the next core's base address start one address after the previous one's - base_addr = core.get_max_addr() + 1 + base_addr = core.max_addr + 1 self._cores[name] = core def _add_friendly_core_names(self): diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 7e8e0a5..edcbb74 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -3,7 +3,7 @@ from manta.utils import * from math import ceil -class MemoryCore(Elaboratable): +class MemoryCore(MantaCore): """ A module for generating a memory on the FPGA, with a port tied to Manta's internal bus, and a port provided to user logic. @@ -60,6 +60,14 @@ class MemoryCore(Elaboratable): self.user_write_enable, ] + @property + def top_level_ports(self): + return self._top_level_ports + + @property + def max_addr(self): + return self._max_addr + @classmethod def from_config(cls, config, base_addr, interface): # Check for unrecognized options @@ -251,21 +259,6 @@ class MemoryCore(Elaboratable): self._tie_mems_to_user_logic(m) return m - def get_top_level_ports(self): - """ - Return the Amaranth signals that should be included as ports in the - top-level Manta module. - """ - return self._top_level_ports - - def get_max_addr(self): - """ - Return the maximum addresses in memory used by the core. The address - space used by the core extends from `base_addr` to the number returned - by this function (including the endpoints). - """ - return self._max_addr - def _convert_user_to_bus_addr(self, addrs): """ Convert user address space to bus address space. For instance, for a diff --git a/src/manta/utils.py b/src/manta/utils.py index 20dc6bc..b9bfba8 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,9 +1,40 @@ +from amaranth import * from amaranth.sim import Simulator -from amaranth.lib import data, enum -from math import ceil +from amaranth.lib import data +from abc import ABC, abstractmethod import os +class MantaCore(ABC, Elaboratable): + + @property + @abstractmethod + def max_addr(self): + """ + Return the maximum addresses in memory used by the core. The address + space used by the core extends from `base_addr` to the number returned + by this function (including the endpoints). + """ + pass + + @property + @abstractmethod + def top_level_ports(self): + """ + Return the Amaranth signals that should be included as ports in the + top-level Manta module. + """ + pass + + @abstractmethod + def elaborate(self, platform): + pass + + # @abstractclassmethod + # def from_config(cls): + # pass + + class InternalBus(data.StructLayout): """ Describes the layout of Manta's internal bus, such that signals of diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index eb240a5..aeb9186 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -96,5 +96,5 @@ def test_single_shot_capture(): yield from write_register(la, 0, 1) yield from write_register(la, 0, 0) - for addr in range(la.get_max_addr()): + for addr in range(la.max_addr): yield from print_data_at_addr(addr) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 9618687..222827c 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -2,15 +2,18 @@ from manta.memory_core import MemoryCore from manta.utils import * from random import randint, sample, choice -class MemoryCoreTests(): + +class MemoryCoreTests: def __init__(self, mem_core): self.mem_core = mem_core self.base_addr = mem_core._base_addr - self.max_addr = mem_core.get_max_addr() + self.max_addr = mem_core.max_addr self.width = self.mem_core._width self.depth = self.mem_core._depth - self.bus_addrs = list(range(self.base_addr, self.max_addr)) # include the endpoint! + self.bus_addrs = list( + range(self.base_addr, self.max_addr) + ) # include the endpoint! self.user_addrs = list(range(self.mem_core._depth)) self.model = {} @@ -86,7 +89,10 @@ class MemoryCoreTests(): data = yield (self.mem_core.user_data_out) if data != expected_data: - raise ValueError(f"Read from {addr} yielded {data} instead of {expected_data}") + raise ValueError( + f"Read from {addr} yielded {data} instead of {expected_data}" + ) + mem_core = MemoryCore( mode="bidirectional", @@ -98,6 +104,7 @@ mem_core = MemoryCore( tests = MemoryCoreTests(mem_core) + @simulate(mem_core) def test_bidirectional_testbench(): yield from tests.check_each_address_on_bus_side_contains_zero() @@ -106,6 +113,7 @@ def test_bidirectional_testbench(): yield from tests.check_multiple_writes_then_multiple_reads() yield from tests.check_random_reads_random_writes_random_orders() + # def test_sweep_core_widths(): # for i in range(1, 64): # verify_mem_core(i, 128, 0) From 08adbd8ede8c89b2dd6e493d75d3ffd5de0e57a3 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Sun, 3 Mar 2024 19:10:06 -0800 Subject: [PATCH 69/89] switch to wiring.Component instead of Elaboratable --- src/manta/ethernet/__init__.py | 4 +++- src/manta/ethernet/sink_bridge.py | 4 +++- src/manta/ethernet/source_bridge.py | 4 +++- src/manta/logic_analyzer/__init__.py | 2 ++ src/manta/logic_analyzer/fsm.py | 5 +++-- src/manta/logic_analyzer/playback.py | 4 +++- src/manta/logic_analyzer/trigger_block.py | 6 ++++-- src/manta/manta.py | 7 ++++--- src/manta/memory_core.py | 2 ++ src/manta/uart/__init__.py | 4 +++- src/manta/uart/receive_bridge.py | 4 +++- src/manta/uart/receiver.py | 4 +++- src/manta/uart/transmit_bridge.py | 4 +++- src/manta/uart/transmitter.py | 4 +++- src/manta/utils.py | 6 ++++-- test/test_io_core_hw.py | 2 +- test/test_logic_analyzer_hw.py | 2 +- test/test_mem_core_hw.py | 2 +- 18 files changed, 49 insertions(+), 21 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index dc5ca69..cb79c4a 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -1,4 +1,6 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from manta.utils import * from manta.ethernet.source_bridge import UDPSourceBridge from manta.ethernet.sink_bridge import UDPSinkBridge @@ -6,7 +8,7 @@ from random import randint import socket -class EthernetInterface(Elaboratable): +class EthernetInterface(wiring.Component): """ A module for communicating with Manta over Ethernet, using UDP. diff --git a/src/manta/ethernet/sink_bridge.py b/src/manta/ethernet/sink_bridge.py index 621d8b9..bec5761 100644 --- a/src/manta/ethernet/sink_bridge.py +++ b/src/manta/ethernet/sink_bridge.py @@ -1,8 +1,10 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from manta.utils import * -class UDPSinkBridge(Elaboratable): +class UDPSinkBridge(wiring.Component): """ A module for bridging Manta's internal bus to an AXI stream of UDP packet data. Connects to the LiteEth core's "sink" port. diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py index 4ed8765..504ddb2 100644 --- a/src/manta/ethernet/source_bridge.py +++ b/src/manta/ethernet/source_bridge.py @@ -1,8 +1,10 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from manta.utils import * -class UDPSourceBridge(Elaboratable): +class UDPSourceBridge(wiring.Component): """ A module for bridging the AXI-stream of incoming UDP packet data to Manta's internal bus. Connects to the LiteEth core's "source" port. diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 2276a6a..11b9c95 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -1,4 +1,6 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from manta.utils import * from manta.memory_core import MemoryCore from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 4853963..26f9aa7 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -1,6 +1,7 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from amaranth.lib.enum import IntEnum -from math import ceil, log2 from manta.io_core import IOCore @@ -18,7 +19,7 @@ class TriggerModes(IntEnum): IMMEDIATE = 2 -class LogicAnalyzerFSM(Elaboratable): +class LogicAnalyzerFSM(wiring.Component): """ A module containing the state machine for a LogicAnalyzerCore. Primarily responsible for controlling the write port of the Logic Analyzer's sample diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index 5ddb6d9..b4b7175 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -1,7 +1,9 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out -class LogicAnalyzerPlayback(Elaboratable): +class LogicAnalyzerPlayback(wiring.Component): """ A synthesizable module that plays back data captured by a LogicAnalyzerCore. Takes a list of all the samples captured by a core, diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 9db01a2..626fc34 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -1,9 +1,11 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from amaranth.lib.enum import IntEnum from manta.io_core import IOCore -class LogicAnalyzerTriggerBlock(Elaboratable): +class LogicAnalyzerTriggerBlock(wiring.Component): """ A module containing an instance of a LogicAnalyzerTrigger for each input probe. The operations and arguments of these LogicAnalyzerTriggers are set @@ -86,7 +88,7 @@ class Operations(IntEnum): NEQ = 9 -class LogicAnalyzerTrigger(Elaboratable): +class LogicAnalyzerTrigger(wiring.Component): """ A module containing a programmable "trigger" for a given input signal, which asserts its output when the programmed "trigger condition" is met. diff --git a/src/manta/manta.py b/src/manta/manta.py index b5ea59e..b2aa899 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -1,13 +1,14 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from manta.uart import UARTInterface - from manta.ethernet import EthernetInterface from manta.io_core import IOCore from manta.memory_core import MemoryCore from manta.logic_analyzer import LogicAnalyzerCore -class Manta(Elaboratable): +class Manta(wiring.Component): def __init__(self, config): # Load config from either a configuration file or a dictionary. # Users primarily use the config file, but the dictionary is @@ -157,7 +158,7 @@ class Manta(Elaboratable): ports = self.interface.get_top_level_ports() for name, instance in self._cores.items(): - ports += instance.get_top_level_ports() + ports += instance.top_level_ports return ports diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index edcbb74..556d142 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -1,4 +1,6 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from manta.utils import * from math import ceil diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index 2e38cf4..cf88122 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -1,4 +1,6 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from manta.utils import * from manta.uart.receiver import UARTReceiver from manta.uart.receive_bridge import ReceiveBridge @@ -7,7 +9,7 @@ from manta.uart.transmit_bridge import TransmitBridge from serial import Serial -class UARTInterface(Elaboratable): +class UARTInterface(wiring.Component): """ A module for communicating with Manta over UART. diff --git a/src/manta/uart/receive_bridge.py b/src/manta/uart/receive_bridge.py index d78c4bd..5d75dfa 100644 --- a/src/manta/uart/receive_bridge.py +++ b/src/manta/uart/receive_bridge.py @@ -1,4 +1,6 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out from amaranth.lib.enum import IntEnum from amaranth.lib.data import ArrayLayout @@ -9,7 +11,7 @@ class States(IntEnum): WRITE = 2 -class ReceiveBridge(Elaboratable): +class ReceiveBridge(wiring.Component): """ A module for bridging the stream of bytes from the UARTReceiver module to Manta's internal bus. diff --git a/src/manta/uart/receiver.py b/src/manta/uart/receiver.py index 2fe65df..8c9f918 100644 --- a/src/manta/uart/receiver.py +++ b/src/manta/uart/receiver.py @@ -1,7 +1,9 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out -class UARTReceiver(Elaboratable): +class UARTReceiver(wiring.Component): """ A module for receiving bytes on a 8N1 UART at a configurable baudrate. Outputs bytes as a stream. diff --git a/src/manta/uart/transmit_bridge.py b/src/manta/uart/transmit_bridge.py index abb1c82..a288414 100644 --- a/src/manta/uart/transmit_bridge.py +++ b/src/manta/uart/transmit_bridge.py @@ -1,7 +1,9 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out -class TransmitBridge(Elaboratable): +class TransmitBridge(wiring.Component): """ A module for bridging Manta's internal bus to the stream of bytes expected by the UARTTransmitter module. diff --git a/src/manta/uart/transmitter.py b/src/manta/uart/transmitter.py index cea5764..c71fd8b 100644 --- a/src/manta/uart/transmitter.py +++ b/src/manta/uart/transmitter.py @@ -1,7 +1,9 @@ from amaranth import * +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out -class UARTTransmitter(Elaboratable): +class UARTTransmitter(wiring.Component): """ A module for transmitting bytes on a 8N1 UART at a configurable baudrate. Accepts bytes as a stream. diff --git a/src/manta/utils.py b/src/manta/utils.py index b9bfba8..7a75ac9 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,11 +1,13 @@ from amaranth import * -from amaranth.sim import Simulator from amaranth.lib import data +from amaranth.lib import wiring +from amaranth.lib.wiring import In, Out +from amaranth.sim import Simulator from abc import ABC, abstractmethod import os -class MantaCore(ABC, Elaboratable): +class MantaCore(ABC, wiring.Component): @property @abstractmethod diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 6715728..25edac1 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -7,7 +7,7 @@ import pytest from random import randint -class IOCoreLoopbackTest(Elaboratable): +class IOCoreLoopbackTest(wiring.Component): def __init__(self, platform, port): self.platform = platform self.port = port diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 8a25335..7521c0a 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -6,7 +6,7 @@ from manta.utils import * import pytest -class LogicAnalyzerCounterTest(Elaboratable): +class LogicAnalyzerCounterTest(wiring.Component): def __init__(self, platform, port): self.platform = platform self.port = port diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 18070ee..185eff1 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -14,7 +14,7 @@ configuration, or a standard one. """ -class MemoryCoreLoopbackTest(Elaboratable): +class MemoryCoreLoopbackTest(wiring.Component): def __init__(self, platform, width, depth, port): self.platform = platform self.width = width From f83dc59b4e7dc2db9be5342e9584d0f5596487e5 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 4 Mar 2024 00:17:36 -0800 Subject: [PATCH 70/89] add more MemoryCore tests --- src/manta/utils.py | 26 +++--- test/test_mem_core_hw.py | 2 +- test/test_mem_core_sim.py | 187 +++++++++++++++++++++++++++++++------- test/test_uart_rx_sim.py | 2 +- test/test_uart_tx_sim.py | 2 +- 5 files changed, 168 insertions(+), 51 deletions(-) diff --git a/src/manta/utils.py b/src/manta/utils.py index 7a75ac9..7e9ace4 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -4,6 +4,7 @@ from amaranth.lib import wiring from amaranth.lib.wiring import In, Out from amaranth.sim import Simulator from abc import ABC, abstractmethod +from random import sample import os @@ -140,29 +141,26 @@ def simulate(top): return decorator -# def simulate_decorator(testbench): -# def wrapper_accepting_arguments(top): -# sim = Simulator(top) -# sim.add_clock(1e-6) # 1 MHz -# sim.add_sync_process(testbench) - -# vcd_path = testbench.__name__ + ".vcd" -# with sim.write_vcd(vcd_path): -# sim.run() - -# return wrapper_accepting_arguments +def jumble(iterable): + """ + Returns the provided iterable, but with every element moved to a random + index. Very similar to random.shuffle, but returns an iteratable, instead + of modifying one in-place. + """ + return sample(iterable, len(iterable)) def verify_register(module, addr, expected_data): """ - Read the contents of a register out over a module's bus connection, and verify - that it contains the expected data. + Read the contents of a register out over a module's bus connection, and + verify that it contains the expected data. Unfortunately because Amaranth uses generator functions to define processes, this must be a generator function and thus cannot return a value - it must yield the next timestep. This means that the comparision with the expected value must occur inside this function and not somewhere else, it's not - possible to return a value from here, and compare it in the calling function. + possible to return a value from here, and compare it in the calling + function. """ # Place read transaction on the bus diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 185eff1..7e801ac 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -104,7 +104,7 @@ class MemoryCoreLoopbackTest(wiring.Component): self.build_and_program() # Read and write randomly from the bus side - for addr in sample(range(self.depth), k=self.depth): + for addr in jumble(range(self.depth)): data = randint(0, 2**self.width - 1) self.write_user_side(addr, data) self.verify_register(addr, data) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 222827c..0a362fd 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -1,6 +1,7 @@ from manta.memory_core import MemoryCore from manta.utils import * -from random import randint, sample, choice +from random import randint, choice +from math import ceil class MemoryCoreTests: @@ -10,6 +11,8 @@ class MemoryCoreTests: self.max_addr = mem_core.max_addr self.width = self.mem_core._width self.depth = self.mem_core._depth + self.n_full = self.width // 16 + self.n_mems = ceil(self.width / 16) self.bus_addrs = list( range(self.base_addr, self.max_addr) @@ -17,43 +20,38 @@ class MemoryCoreTests: self.user_addrs = list(range(self.mem_core._depth)) self.model = {} - def check_each_address_on_bus_side_contains_zero(self): + def bus_addrs_all_zero(self): for addr in self.bus_addrs: yield from self.verify_bus_side(addr, 0) - def check_each_address_on_user_side_contains_zero(self): + def user_addrs_all_zero(self): for addr in self.user_addrs: yield from self.verify_user_side(addr, 0) - def check_write_then_immediately_read_bus_side(self): + def one_bus_write_then_one_bus_read(self): for addr in self.bus_addrs: - # this part is a little hard to check since we might have a - # memory at the end of the address space that's less than - # 16-bits wide. so we'll have to calculate how wide our - # memory is - data_width = self.get_data_width(addr) data = randint(0, (2**data_width) - 1) yield from self.write_bus_side(addr, data) yield from self.verify_bus_side(addr, data) - def check_multiple_writes_then_multiple_reads(self): + def multi_bus_writes_then_multi_bus_reads(self): # write-write-write then read-read-read - for addr in sample(self.bus_addrs, len(self.bus_addrs)): + for addr in jumble(self.bus_addrs): data_width = self.get_data_width(addr) data = randint(0, (2**data_width) - 1) self.model[addr] = data yield from self.write_bus_side(addr, data) - for addr in sample(self.bus_addrs, len(self.bus_addrs)): + for addr in jumble(self.bus_addrs): yield from self.verify_bus_side(addr, self.model[addr]) - def check_random_reads_random_writes_random_orders(self): + def rand_bus_reads_writes(self): # random reads and writes in random orders for _ in range(5): - for addr in sample(self.bus_addrs, len(self.bus_addrs)): + for addr in jumble(self.bus_addrs): operation = choice(["read", "write"]) if operation == "read": @@ -65,9 +63,69 @@ class MemoryCoreTests: self.model[addr] = data yield from self.write_bus_side(addr, data) + def one_user_write_then_one_bus_read(self): + for user_addr in self.user_addrs: + # write to user side + data = randint(0, (2**self.width) - 1) + yield from self.write_user_side(user_addr, data) + + # verify contents when read out from the bus + words = value_to_words(data, self.n_mems) + for i, word in enumerate(words): + bus_addr = self.base_addr + user_addr + (i * self.depth) + yield from self.verify_bus_side(bus_addr, word) + + def multi_user_write_then_multi_bus_reads(self): + # write-write-write then read-read-read + for user_addr in jumble(self.user_addrs): + + # write a random number to the user side + data = randint(0, (2**self.width) - 1) + yield from self.write_user_side(user_addr, data) + + # convert value to words, and save to self.model + words = value_to_words(data, self.n_mems) + for i, word in enumerate(words): + bus_addr = self.base_addr + user_addr + (i * self.depth) + self.model[bus_addr] = word + + # read out every bus_addr in random order + for bus_addr in jumble(self.bus_addrs): + yield from self.verify_bus_side(bus_addr, self.model[bus_addr]) + + def rand_bus_reads_rand_user_writes(self): + # random reads and writes in random orders + for _ in range(5): + for user_addr in jumble(self.user_addrs): + bus_addrs = [ + self.base_addr + user_addr + (i * self.depth) + for i in range(self.n_mems) + ] + + operation = choice(["read", "write"]) + + # read from bus side + if operation == "read": + for bus_addr in bus_addrs: + yield from self.verify_bus_side(bus_addr, self.model[bus_addr]) + + # write to user side + elif operation == "write": + data = randint(0, (2**self.width) - 1) + yield from self.write_user_side(user_addr, data) + + # save words just written to self.model + words = value_to_words(data, self.n_mems) + for addr, word in zip(bus_addrs, words): + self.model[addr] = word + def get_data_width(self, addr): - n_full = self.width // 16 - if addr < self.base_addr + (n_full * self.depth): + # this part is a little hard to check since we might have a + # memory at the end of the address space that's less than + # 16-bits wide. so we'll have to calculate how wide our + # memory is + + if addr < self.base_addr + (self.n_full * self.depth): return 16 else: return self.width % 16 @@ -84,7 +142,6 @@ class MemoryCoreTests: def verify_user_side(self, addr, expected_data): yield self.mem_core.user_addr.eq(addr) - yield self.mem_core.user_write_enable.eq(0) yield data = yield (self.mem_core.user_data_out) @@ -93,25 +150,87 @@ class MemoryCoreTests: f"Read from {addr} yielded {data} instead of {expected_data}" ) - -mem_core = MemoryCore( - mode="bidirectional", - width=23, - depth=512, - base_addr=0, - interface=None, -) - -tests = MemoryCoreTests(mem_core) + def write_user_side(self, addr, data): + yield self.mem_core.user_addr.eq(addr) + yield self.mem_core.user_data_in.eq(data) + yield self.mem_core.user_write_enable.eq(1) + yield + yield self.mem_core.user_addr.eq(0) + yield self.mem_core.user_data_in.eq(0) + yield self.mem_core.user_write_enable.eq(0) -@simulate(mem_core) -def test_bidirectional_testbench(): - yield from tests.check_each_address_on_bus_side_contains_zero() - yield from tests.check_each_address_on_user_side_contains_zero() - yield from tests.check_write_then_immediately_read_bus_side() - yield from tests.check_multiple_writes_then_multiple_reads() - yield from tests.check_random_reads_random_writes_random_orders() +def test_bidirectional(): + mem_core = MemoryCore( + mode="bidirectional", + width=23, + depth=512, + base_addr=0, + interface=None, + ) + + tests = MemoryCoreTests(mem_core) + + @simulate(mem_core) + def test_bidirectional_testbench(): + yield from tests.bus_addrs_all_zero() + + # Test Bus -> Bus functionality + yield from tests.user_addrs_all_zero() + yield from tests.one_bus_write_then_one_bus_read() + yield from tests.multi_bus_writes_then_multi_bus_reads() + yield from tests.rand_bus_reads_writes() + + # Test User -> Bus functionality + yield from tests.one_user_write_then_one_bus_read() + yield from tests.multi_user_write_then_multi_bus_reads() + yield from tests.rand_bus_reads_rand_user_writes() + + test_bidirectional_testbench() + + +def test_fpga_to_host(): + mem_core = MemoryCore( + mode="fpga_to_host", + width=23, + depth=512, + base_addr=0, + interface=None, + ) + + tests = MemoryCoreTests(mem_core) + + @simulate(mem_core) + def test_fpga_to_host_testbench(): + yield from tests.bus_addrs_all_zero() + + # Test User -> Bus functionality + yield from tests.one_user_write_then_one_bus_read() + yield from tests.multi_user_write_then_multi_bus_reads() + yield from tests.rand_bus_reads_rand_user_writes() + + test_fpga_to_host_testbench() + + +def test_host_to_fpga(): + mem_core = MemoryCore( + mode="host_to_fpga", + width=23, + depth=512, + base_addr=0, + interface=None, + ) + + tests = MemoryCoreTests(mem_core) + + @simulate(mem_core) + def test_host_to_fpga_testbench(): + yield from tests.user_addrs_all_zero() + # yield from tests.one_user_write_then_one_bus_read() + # yield from tests.multi_user_write_then_multi_bus_reads() + # yield from tests.rand_bus_reads_rand_user_writes() + + test_host_to_fpga_testbench() # def test_sweep_core_widths(): diff --git a/test/test_uart_rx_sim.py b/test/test_uart_rx_sim.py index 23c9f43..111ce09 100644 --- a/test/test_uart_rx_sim.py +++ b/test/test_uart_rx_sim.py @@ -57,5 +57,5 @@ def test_bytes_random_sample(): yield uart_rx.rx.eq(1) yield - for i in sample(range(0xFF), k=0xFF): + for i in jumble(range(0xFF)): yield from verify_receive(i) diff --git a/test/test_uart_tx_sim.py b/test/test_uart_tx_sim.py index 63bd373..1176cfc 100644 --- a/test/test_uart_tx_sim.py +++ b/test/test_uart_tx_sim.py @@ -49,5 +49,5 @@ def test_all_possible_bytes(): @simulate(uart_tx) def test_bytes_random_sample(): - for i in sample(range(0xFF), k=0xFF): + for i in jumble(range(0xFF)): yield from verify_bit_sequence(i) From 5531277c996d68874c49a34285459ed9e9f646bd Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 4 Mar 2024 00:43:54 -0800 Subject: [PATCH 71/89] even more MemoryCore tests --- test/test_mem_core_sim.py | 56 ++++++++++++++++++++++++++++++++------- 1 file changed, 47 insertions(+), 9 deletions(-) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 0a362fd..5e52131 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -28,6 +28,7 @@ class MemoryCoreTests: for addr in self.user_addrs: yield from self.verify_user_side(addr, 0) + def one_bus_write_then_one_bus_read(self): for addr in self.bus_addrs: data_width = self.get_data_width(addr) @@ -48,7 +49,7 @@ class MemoryCoreTests: for addr in jumble(self.bus_addrs): yield from self.verify_bus_side(addr, self.model[addr]) - def rand_bus_reads_writes(self): + def rand_bus_writes_rand_bus_reads(self): # random reads and writes in random orders for _ in range(5): for addr in jumble(self.bus_addrs): @@ -63,6 +64,7 @@ class MemoryCoreTests: self.model[addr] = data yield from self.write_bus_side(addr, data) + def one_user_write_then_one_bus_read(self): for user_addr in self.user_addrs: # write to user side @@ -93,7 +95,7 @@ class MemoryCoreTests: for bus_addr in jumble(self.bus_addrs): yield from self.verify_bus_side(bus_addr, self.model[bus_addr]) - def rand_bus_reads_rand_user_writes(self): + def rand_user_writes_rand_bus_reads(self): # random reads and writes in random orders for _ in range(5): for user_addr in jumble(self.user_addrs): @@ -119,6 +121,30 @@ class MemoryCoreTests: for addr, word in zip(bus_addrs, words): self.model[addr] = word + + def one_bus_write_then_one_user_read(self): + yield + + def multi_bus_write_then_multi_user_reads(self): + yield + + def rand_bus_writes_rand_user_reads(self): + yield + + + def one_user_write_then_one_user_read(self): + for addr in self.user_addrs: + data = randint(0, (2**self.width) - 1) + + yield from self.write_user_side(addr, data) + yield from self.verify_user_side(addr, data) + + def multi_user_write_then_multi_user_read(self): + yield + + def rand_user_write_rand_user_read(self): + yield + def get_data_width(self, addr): # this part is a little hard to check since we might have a # memory at the end of the address space that's less than @@ -174,17 +200,27 @@ def test_bidirectional(): @simulate(mem_core) def test_bidirectional_testbench(): yield from tests.bus_addrs_all_zero() + yield from tests.user_addrs_all_zero() # Test Bus -> Bus functionality - yield from tests.user_addrs_all_zero() yield from tests.one_bus_write_then_one_bus_read() yield from tests.multi_bus_writes_then_multi_bus_reads() - yield from tests.rand_bus_reads_writes() + yield from tests.rand_bus_writes_rand_bus_reads() # Test User -> Bus functionality yield from tests.one_user_write_then_one_bus_read() yield from tests.multi_user_write_then_multi_bus_reads() - yield from tests.rand_bus_reads_rand_user_writes() + yield from tests.rand_user_writes_rand_bus_reads() + + # Test Bus -> User functionality + yield from tests.one_bus_write_then_one_user_read() + yield from tests.multi_bus_write_then_multi_user_reads() + yield from tests.rand_bus_writes_rand_user_reads() + + # Test User -> User functionality + yield from tests.one_user_write_then_one_user_read() + yield from tests.multi_user_write_then_multi_user_read() + yield from tests.rand_user_write_rand_user_read() test_bidirectional_testbench() @@ -207,7 +243,7 @@ def test_fpga_to_host(): # Test User -> Bus functionality yield from tests.one_user_write_then_one_bus_read() yield from tests.multi_user_write_then_multi_bus_reads() - yield from tests.rand_bus_reads_rand_user_writes() + yield from tests.rand_user_writes_rand_bus_reads() test_fpga_to_host_testbench() @@ -226,9 +262,11 @@ def test_host_to_fpga(): @simulate(mem_core) def test_host_to_fpga_testbench(): yield from tests.user_addrs_all_zero() - # yield from tests.one_user_write_then_one_bus_read() - # yield from tests.multi_user_write_then_multi_bus_reads() - # yield from tests.rand_bus_reads_rand_user_writes() + + # Test Bus -> User functionality + yield from tests.one_bus_write_then_one_user_read() + yield from tests.multi_bus_write_then_multi_user_reads() + yield from tests.rand_bus_writes_rand_user_reads() test_host_to_fpga_testbench() From b00e4d0e60b5ff63f282da811a2546df14c0badb Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 4 Mar 2024 01:18:31 -0800 Subject: [PATCH 72/89] revert wiring.Component instead of Elaboratable --- src/manta/ethernet/__init__.py | 4 +--- src/manta/ethernet/sink_bridge.py | 4 +--- src/manta/ethernet/source_bridge.py | 4 +--- src/manta/logic_analyzer/__init__.py | 2 -- src/manta/logic_analyzer/fsm.py | 4 +--- src/manta/logic_analyzer/playback.py | 4 +--- src/manta/logic_analyzer/trigger_block.py | 6 ++---- src/manta/manta.py | 4 +--- src/manta/memory_core.py | 2 -- src/manta/uart/__init__.py | 4 +--- src/manta/uart/receive_bridge.py | 4 +--- src/manta/uart/receiver.py | 4 +--- src/manta/uart/transmit_bridge.py | 4 +--- src/manta/uart/transmitter.py | 4 +--- src/manta/utils.py | 4 +--- test/test_io_core_hw.py | 2 +- test/test_logic_analyzer_hw.py | 2 +- test/test_mem_core_hw.py | 2 +- test/test_mem_core_sim.py | 4 ---- 19 files changed, 17 insertions(+), 51 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index cb79c4a..dc5ca69 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -1,6 +1,4 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from manta.utils import * from manta.ethernet.source_bridge import UDPSourceBridge from manta.ethernet.sink_bridge import UDPSinkBridge @@ -8,7 +6,7 @@ from random import randint import socket -class EthernetInterface(wiring.Component): +class EthernetInterface(Elaboratable): """ A module for communicating with Manta over Ethernet, using UDP. diff --git a/src/manta/ethernet/sink_bridge.py b/src/manta/ethernet/sink_bridge.py index bec5761..621d8b9 100644 --- a/src/manta/ethernet/sink_bridge.py +++ b/src/manta/ethernet/sink_bridge.py @@ -1,10 +1,8 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from manta.utils import * -class UDPSinkBridge(wiring.Component): +class UDPSinkBridge(Elaboratable): """ A module for bridging Manta's internal bus to an AXI stream of UDP packet data. Connects to the LiteEth core's "sink" port. diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py index 504ddb2..4ed8765 100644 --- a/src/manta/ethernet/source_bridge.py +++ b/src/manta/ethernet/source_bridge.py @@ -1,10 +1,8 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from manta.utils import * -class UDPSourceBridge(wiring.Component): +class UDPSourceBridge(Elaboratable): """ A module for bridging the AXI-stream of incoming UDP packet data to Manta's internal bus. Connects to the LiteEth core's "source" port. diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py index 11b9c95..2276a6a 100644 --- a/src/manta/logic_analyzer/__init__.py +++ b/src/manta/logic_analyzer/__init__.py @@ -1,6 +1,4 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from manta.utils import * from manta.memory_core import MemoryCore from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 26f9aa7..5eebb31 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -1,6 +1,4 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from amaranth.lib.enum import IntEnum from manta.io_core import IOCore @@ -19,7 +17,7 @@ class TriggerModes(IntEnum): IMMEDIATE = 2 -class LogicAnalyzerFSM(wiring.Component): +class LogicAnalyzerFSM(Elaboratable): """ A module containing the state machine for a LogicAnalyzerCore. Primarily responsible for controlling the write port of the Logic Analyzer's sample diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index b4b7175..5ddb6d9 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -1,9 +1,7 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out -class LogicAnalyzerPlayback(wiring.Component): +class LogicAnalyzerPlayback(Elaboratable): """ A synthesizable module that plays back data captured by a LogicAnalyzerCore. Takes a list of all the samples captured by a core, diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py index 626fc34..9db01a2 100644 --- a/src/manta/logic_analyzer/trigger_block.py +++ b/src/manta/logic_analyzer/trigger_block.py @@ -1,11 +1,9 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from amaranth.lib.enum import IntEnum from manta.io_core import IOCore -class LogicAnalyzerTriggerBlock(wiring.Component): +class LogicAnalyzerTriggerBlock(Elaboratable): """ A module containing an instance of a LogicAnalyzerTrigger for each input probe. The operations and arguments of these LogicAnalyzerTriggers are set @@ -88,7 +86,7 @@ class Operations(IntEnum): NEQ = 9 -class LogicAnalyzerTrigger(wiring.Component): +class LogicAnalyzerTrigger(Elaboratable): """ A module containing a programmable "trigger" for a given input signal, which asserts its output when the programmed "trigger condition" is met. diff --git a/src/manta/manta.py b/src/manta/manta.py index b2aa899..2cd4868 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -1,6 +1,4 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from manta.uart import UARTInterface from manta.ethernet import EthernetInterface from manta.io_core import IOCore @@ -8,7 +6,7 @@ from manta.memory_core import MemoryCore from manta.logic_analyzer import LogicAnalyzerCore -class Manta(wiring.Component): +class Manta(Elaboratable): def __init__(self, config): # Load config from either a configuration file or a dictionary. # Users primarily use the config file, but the dictionary is diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 556d142..edcbb74 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -1,6 +1,4 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from manta.utils import * from math import ceil diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py index cf88122..2e38cf4 100644 --- a/src/manta/uart/__init__.py +++ b/src/manta/uart/__init__.py @@ -1,6 +1,4 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from manta.utils import * from manta.uart.receiver import UARTReceiver from manta.uart.receive_bridge import ReceiveBridge @@ -9,7 +7,7 @@ from manta.uart.transmit_bridge import TransmitBridge from serial import Serial -class UARTInterface(wiring.Component): +class UARTInterface(Elaboratable): """ A module for communicating with Manta over UART. diff --git a/src/manta/uart/receive_bridge.py b/src/manta/uart/receive_bridge.py index 5d75dfa..d78c4bd 100644 --- a/src/manta/uart/receive_bridge.py +++ b/src/manta/uart/receive_bridge.py @@ -1,6 +1,4 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from amaranth.lib.enum import IntEnum from amaranth.lib.data import ArrayLayout @@ -11,7 +9,7 @@ class States(IntEnum): WRITE = 2 -class ReceiveBridge(wiring.Component): +class ReceiveBridge(Elaboratable): """ A module for bridging the stream of bytes from the UARTReceiver module to Manta's internal bus. diff --git a/src/manta/uart/receiver.py b/src/manta/uart/receiver.py index 8c9f918..2fe65df 100644 --- a/src/manta/uart/receiver.py +++ b/src/manta/uart/receiver.py @@ -1,9 +1,7 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out -class UARTReceiver(wiring.Component): +class UARTReceiver(Elaboratable): """ A module for receiving bytes on a 8N1 UART at a configurable baudrate. Outputs bytes as a stream. diff --git a/src/manta/uart/transmit_bridge.py b/src/manta/uart/transmit_bridge.py index a288414..abb1c82 100644 --- a/src/manta/uart/transmit_bridge.py +++ b/src/manta/uart/transmit_bridge.py @@ -1,9 +1,7 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out -class TransmitBridge(wiring.Component): +class TransmitBridge(Elaboratable): """ A module for bridging Manta's internal bus to the stream of bytes expected by the UARTTransmitter module. diff --git a/src/manta/uart/transmitter.py b/src/manta/uart/transmitter.py index c71fd8b..cea5764 100644 --- a/src/manta/uart/transmitter.py +++ b/src/manta/uart/transmitter.py @@ -1,9 +1,7 @@ from amaranth import * -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out -class UARTTransmitter(wiring.Component): +class UARTTransmitter(Elaboratable): """ A module for transmitting bytes on a 8N1 UART at a configurable baudrate. Accepts bytes as a stream. diff --git a/src/manta/utils.py b/src/manta/utils.py index 7e9ace4..fdee740 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -1,14 +1,12 @@ from amaranth import * from amaranth.lib import data -from amaranth.lib import wiring -from amaranth.lib.wiring import In, Out from amaranth.sim import Simulator from abc import ABC, abstractmethod from random import sample import os -class MantaCore(ABC, wiring.Component): +class MantaCore(ABC, Elaboratable): @property @abstractmethod diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 25edac1..6715728 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -7,7 +7,7 @@ import pytest from random import randint -class IOCoreLoopbackTest(wiring.Component): +class IOCoreLoopbackTest(Elaboratable): def __init__(self, platform, port): self.platform = platform self.port = port diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 7521c0a..8a25335 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -6,7 +6,7 @@ from manta.utils import * import pytest -class LogicAnalyzerCounterTest(wiring.Component): +class LogicAnalyzerCounterTest(Elaboratable): def __init__(self, platform, port): self.platform = platform self.port = port diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 7e801ac..27c1208 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -14,7 +14,7 @@ configuration, or a standard one. """ -class MemoryCoreLoopbackTest(wiring.Component): +class MemoryCoreLoopbackTest(Elaboratable): def __init__(self, platform, width, depth, port): self.platform = platform self.width = width diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 5e52131..659eef3 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -28,7 +28,6 @@ class MemoryCoreTests: for addr in self.user_addrs: yield from self.verify_user_side(addr, 0) - def one_bus_write_then_one_bus_read(self): for addr in self.bus_addrs: data_width = self.get_data_width(addr) @@ -64,7 +63,6 @@ class MemoryCoreTests: self.model[addr] = data yield from self.write_bus_side(addr, data) - def one_user_write_then_one_bus_read(self): for user_addr in self.user_addrs: # write to user side @@ -121,7 +119,6 @@ class MemoryCoreTests: for addr, word in zip(bus_addrs, words): self.model[addr] = word - def one_bus_write_then_one_user_read(self): yield @@ -131,7 +128,6 @@ class MemoryCoreTests: def rand_bus_writes_rand_user_reads(self): yield - def one_user_write_then_one_user_read(self): for addr in self.user_addrs: data = randint(0, (2**self.width) - 1) From fd22c9a9f4d74964afaab36cfad52ac8d65cfe6a Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Tue, 5 Mar 2024 22:44:36 -0800 Subject: [PATCH 73/89] finish memory core test class --- test/test_mem_core_sim.py | 107 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 102 insertions(+), 5 deletions(-) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 659eef3..da97fcd 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -120,13 +120,61 @@ class MemoryCoreTests: self.model[addr] = word def one_bus_write_then_one_user_read(self): - yield + for user_addr in self.user_addrs: + # Try and set the value at the user address to a given value, + # by writing to the appropriate memory locaitons on the bus side + data = randint(0, (2**self.width) - 1) + + words = value_to_words(data, self.n_mems) + + for i, word in enumerate(words): + bus_addr = self.base_addr + user_addr + (i * self.depth) + yield from self.write_bus_side(bus_addr, word) + + yield from self.verify_user_side(user_addr, data) def multi_bus_write_then_multi_user_reads(self): - yield + # write-write-write then read-read-read + for bus_addr in jumble(self.bus_addrs): + data_width = self.get_data_width(bus_addr) + data = randint(0, (2**data_width) - 1) + + self.model[bus_addr] = data + yield from self.write_bus_side(bus_addr, data) + + for user_addr in jumble(self.user_addrs): + bus_addrs = [ + self.base_addr + user_addr + (i * self.depth) + for i in range(self.n_mems) + ] + + value = words_to_value([self.model[addr] for addr in bus_addrs]) + yield from self.verify_user_side(user_addr, value) def rand_bus_writes_rand_user_reads(self): - yield + for _ in range(5 * self.depth): + operation = choice(["read", "write"]) + + # write random data to random bus address + if operation == "write": + bus_addr = randint(self.base_addr, self.max_addr - 1) + data_width = self.get_data_width(bus_addr) + data = randint(0, (2**data_width) - 1) + self.model[bus_addr] = data + + yield from self.write_bus_side(bus_addr, data) + + # read from random user_addr + if operation == "read": + user_addr = randint(0, self.depth - 1) + bus_addrs = [ + self.base_addr + user_addr + (i * self.depth) + for i in range(self.n_mems) + ] + + value = words_to_value([self.model[addr] for addr in bus_addrs]) + + yield from self.verify_user_side(user_addr, value) def one_user_write_then_one_user_read(self): for addr in self.user_addrs: @@ -136,10 +184,58 @@ class MemoryCoreTests: yield from self.verify_user_side(addr, data) def multi_user_write_then_multi_user_read(self): - yield + # write-write-write then read-read-read + for user_addr in jumble(self.user_addrs): + data = randint(0, (2**self.width) - 1) + + bus_addrs = [ + self.base_addr + user_addr + (i * self.depth) + for i in range(self.n_mems) + ] + + words = value_to_words(data, self.n_mems) + for addr, word in zip(bus_addrs, words): + self.model[addr] = word + + yield from self.write_user_side(addr, data) + + for user_addr in jumble(self.user_addrs): + bus_addrs = [ + self.base_addr + user_addr + (i * self.depth) + for i in range(self.n_mems) + ] + + value = words_to_value([self.model[addr] for addr in bus_addrs]) + + yield from self.verify_user_side(user_addr, value) def rand_user_write_rand_user_read(self): - yield + # random reads and writes in random orders + for _ in range(5): + for user_addr in jumble(self.user_addrs): + + operation = choice(["read", "write"]) + if operation == "read": + bus_addrs = [ + self.base_addr + user_addr + (i * self.depth) + for i in range(self.n_mems) + ] + + value = words_to_value([self.model[addr] for addr in bus_addrs]) + + yield from self.verify_user_side(user_addr, value) + + elif operation == "write": + data = randint(0, (2**self.width) - 1) + yield from self.write_user_side(user_addr, data) + + words = value_to_words(data, self.n_mems) + bus_addrs = [ + self.base_addr + user_addr + (i * self.depth) + for i in range(self.n_mems) + ] + for addr, word in zip(bus_addrs, words): + self.model[addr] = word def get_data_width(self, addr): # this part is a little hard to check since we might have a @@ -165,6 +261,7 @@ class MemoryCoreTests: def verify_user_side(self, addr, expected_data): yield self.mem_core.user_addr.eq(addr) yield + yield data = yield (self.mem_core.user_data_out) if data != expected_data: From c1935bcb11ef4f5fc812ccb53e03bf5be9dcee3e Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Tue, 5 Mar 2024 23:59:42 -0800 Subject: [PATCH 74/89] add random memory core tests --- test/test_mem_core_sim.py | 173 +++++++++++++++++++++----------------- 1 file changed, 94 insertions(+), 79 deletions(-) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index da97fcd..29bd73d 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -20,6 +20,7 @@ class MemoryCoreTests: self.user_addrs = list(range(self.mem_core._depth)) self.model = {} + def bus_addrs_all_zero(self): for addr in self.bus_addrs: yield from self.verify_bus_side(addr, 0) @@ -28,9 +29,29 @@ class MemoryCoreTests: for addr in self.user_addrs: yield from self.verify_user_side(addr, 0) + def bus_to_bus_functionality(self): + yield from self.one_bus_write_then_one_bus_read() + yield from self.multi_bus_writes_then_multi_bus_reads() + yield from self.rand_bus_writes_rand_bus_reads() + + def user_to_bus_functionality(self): + yield from self.one_user_write_then_one_bus_read() + yield from self.multi_user_write_then_multi_bus_reads() + yield from self.rand_user_writes_rand_bus_reads() + + def bus_to_user_functionality(self): + yield from self.one_bus_write_then_one_user_read() + yield from self.multi_bus_write_then_multi_user_reads() + yield from self.rand_bus_writes_rand_user_reads() + + def user_to_user_functionality(self): + yield from self.one_user_write_then_one_user_read() + yield from self.multi_user_write_then_multi_user_read() + yield from self.rand_user_write_rand_user_read() + def one_bus_write_then_one_bus_read(self): for addr in self.bus_addrs: - data_width = self.get_data_width(addr) + data_width = self._get_data_width(addr) data = randint(0, (2**data_width) - 1) yield from self.write_bus_side(addr, data) @@ -39,7 +60,7 @@ class MemoryCoreTests: def multi_bus_writes_then_multi_bus_reads(self): # write-write-write then read-read-read for addr in jumble(self.bus_addrs): - data_width = self.get_data_width(addr) + data_width = self._get_data_width(addr) data = randint(0, (2**data_width) - 1) self.model[addr] = data @@ -58,7 +79,7 @@ class MemoryCoreTests: yield from self.verify_bus_side(addr, self.model[addr]) elif operation == "write": - data_width = self.get_data_width(addr) + data_width = self._get_data_width(addr) data = randint(0, (2**data_width) - 1) self.model[addr] = data yield from self.write_bus_side(addr, data) @@ -136,7 +157,7 @@ class MemoryCoreTests: def multi_bus_write_then_multi_user_reads(self): # write-write-write then read-read-read for bus_addr in jumble(self.bus_addrs): - data_width = self.get_data_width(bus_addr) + data_width = self._get_data_width(bus_addr) data = randint(0, (2**data_width) - 1) self.model[bus_addr] = data @@ -158,7 +179,7 @@ class MemoryCoreTests: # write random data to random bus address if operation == "write": bus_addr = randint(self.base_addr, self.max_addr - 1) - data_width = self.get_data_width(bus_addr) + data_width = self._get_data_width(bus_addr) data = randint(0, (2**data_width) - 1) self.model[bus_addr] = data @@ -185,29 +206,14 @@ class MemoryCoreTests: def multi_user_write_then_multi_user_read(self): # write-write-write then read-read-read + self.foo = {} for user_addr in jumble(self.user_addrs): data = randint(0, (2**self.width) - 1) - - bus_addrs = [ - self.base_addr + user_addr + (i * self.depth) - for i in range(self.n_mems) - ] - - words = value_to_words(data, self.n_mems) - for addr, word in zip(bus_addrs, words): - self.model[addr] = word - - yield from self.write_user_side(addr, data) + self.foo[user_addr] = data + yield from self.write_user_side(user_addr, data) for user_addr in jumble(self.user_addrs): - bus_addrs = [ - self.base_addr + user_addr + (i * self.depth) - for i in range(self.n_mems) - ] - - value = words_to_value([self.model[addr] for addr in bus_addrs]) - - yield from self.verify_user_side(user_addr, value) + yield from self.verify_user_side(user_addr, self.foo[user_addr]) def rand_user_write_rand_user_read(self): # random reads and writes in random orders @@ -216,28 +222,14 @@ class MemoryCoreTests: operation = choice(["read", "write"]) if operation == "read": - bus_addrs = [ - self.base_addr + user_addr + (i * self.depth) - for i in range(self.n_mems) - ] - - value = words_to_value([self.model[addr] for addr in bus_addrs]) - - yield from self.verify_user_side(user_addr, value) + yield from self.verify_user_side(user_addr, self.foo[user_addr]) elif operation == "write": data = randint(0, (2**self.width) - 1) + self.foo[user_addr] = data yield from self.write_user_side(user_addr, data) - words = value_to_words(data, self.n_mems) - bus_addrs = [ - self.base_addr + user_addr + (i * self.depth) - for i in range(self.n_mems) - ] - for addr, word in zip(bus_addrs, words): - self.model[addr] = word - - def get_data_width(self, addr): + def _get_data_width(self, addr): # this part is a little hard to check since we might have a # memory at the end of the address space that's less than # 16-bits wide. so we'll have to calculate how wide our @@ -295,28 +287,36 @@ def test_bidirectional(): yield from tests.bus_addrs_all_zero() yield from tests.user_addrs_all_zero() - # Test Bus -> Bus functionality - yield from tests.one_bus_write_then_one_bus_read() - yield from tests.multi_bus_writes_then_multi_bus_reads() - yield from tests.rand_bus_writes_rand_bus_reads() - - # Test User -> Bus functionality - yield from tests.one_user_write_then_one_bus_read() - yield from tests.multi_user_write_then_multi_bus_reads() - yield from tests.rand_user_writes_rand_bus_reads() - - # Test Bus -> User functionality - yield from tests.one_bus_write_then_one_user_read() - yield from tests.multi_bus_write_then_multi_user_reads() - yield from tests.rand_bus_writes_rand_user_reads() - - # Test User -> User functionality - yield from tests.one_user_write_then_one_user_read() - yield from tests.multi_user_write_then_multi_user_read() - yield from tests.rand_user_write_rand_user_read() + yield from tests.bus_to_bus_functionality() + yield from tests.user_to_bus_functionality() + yield from tests.bus_to_user_functionality() + yield from tests.user_to_user_functionality() test_bidirectional_testbench() +def test_bidirectional_random(): + mem_core = MemoryCore( + mode="bidirectional", + width=randint(0, 128), + depth=randint(0, 2048), + base_addr=randint(0, 32678), + interface=None, + ) + + tests = MemoryCoreTests(mem_core) + + @simulate(mem_core) + def test_bidirectional_random_testbench(): + yield from tests.bus_addrs_all_zero() + yield from tests.user_addrs_all_zero() + + yield from tests.bus_to_bus_functionality() + yield from tests.user_to_bus_functionality() + yield from tests.bus_to_user_functionality() + yield from tests.user_to_user_functionality() + + test_bidirectional_random_testbench() + def test_fpga_to_host(): mem_core = MemoryCore( @@ -332,14 +332,28 @@ def test_fpga_to_host(): @simulate(mem_core) def test_fpga_to_host_testbench(): yield from tests.bus_addrs_all_zero() - - # Test User -> Bus functionality - yield from tests.one_user_write_then_one_bus_read() - yield from tests.multi_user_write_then_multi_bus_reads() - yield from tests.rand_user_writes_rand_bus_reads() + yield from tests.user_to_bus_functionality() test_fpga_to_host_testbench() +def test_fpga_to_host_random(): + mem_core = MemoryCore( + mode="fpga_to_host", + width=randint(0, 128), + depth=randint(0, 2048), + base_addr=randint(0, 32678), + interface=None, + ) + + tests = MemoryCoreTests(mem_core) + + @simulate(mem_core) + def test_fpga_to_host_random_testbench(): + yield from tests.bus_addrs_all_zero() + yield from tests.user_to_bus_functionality() + + test_fpga_to_host_random_testbench() + def test_host_to_fpga(): mem_core = MemoryCore( @@ -355,23 +369,24 @@ def test_host_to_fpga(): @simulate(mem_core) def test_host_to_fpga_testbench(): yield from tests.user_addrs_all_zero() - - # Test Bus -> User functionality - yield from tests.one_bus_write_then_one_user_read() - yield from tests.multi_bus_write_then_multi_user_reads() - yield from tests.rand_bus_writes_rand_user_reads() + yield from tests.bus_to_user_functionality() test_host_to_fpga_testbench() +def test_host_to_fpga_random(): + mem_core = MemoryCore( + mode="host_to_fpga", + width=randint(0, 128), + depth=randint(0, 2048), + base_addr=randint(0, 32678), + interface=None, + ) -# def test_sweep_core_widths(): -# for i in range(1, 64): -# verify_mem_core(i, 128, 0) + tests = MemoryCoreTests(mem_core) + @simulate(mem_core) + def test_host_to_fpga_random_testbench(): + yield from tests.user_addrs_all_zero() + yield from tests.bus_to_user_functionality() -# def test_random_cores(): -# for _ in range(5): -# width = randint(0, 512) -# depth = randint(0, 1024) -# base_addr = randint(0, 2**16 - 1 - depth) -# verify_mem_core(width, depth, base_addr) + test_host_to_fpga_random_testbench() From 5d5a50042f0da70ad93b7a446c4a296ae766b745 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 01:12:36 -0800 Subject: [PATCH 75/89] make model tracking automatic in memory core tests --- src/manta/ethernet/__init__.py | 4 +- src/manta/utils.py | 30 +++---- test/test_io_core_hw.py | 4 +- test/test_io_core_sim.py | 8 +- test/test_mem_core_hw.py | 4 +- test/test_mem_core_sim.py | 152 +++++++++++++++------------------ 6 files changed, 96 insertions(+), 106 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index dc5ca69..4b8bbb8 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -2,7 +2,7 @@ from amaranth import * from manta.utils import * from manta.ethernet.source_bridge import UDPSourceBridge from manta.ethernet.sink_bridge import UDPSinkBridge -from random import randint +from random import getrandbits import socket @@ -339,7 +339,7 @@ class EthernetInterface(Elaboratable): # https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses if "mac_address" not in liteeth_config: - addr = list(f"{randint(0, (2**48) - 1):012x}") + addr = list(f"{getrandbits(48):012x}") addr[1] = "2" liteeth_config["mac_address"] = int("".join(addr), 16) print(liteeth_config["mac_address"]) diff --git a/src/manta/utils.py b/src/manta/utils.py index fdee740..a10af95 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -2,7 +2,7 @@ from amaranth import * from amaranth.lib import data from amaranth.sim import Simulator from abc import ABC, abstractmethod -from random import sample +from random import sample, randint import os @@ -75,6 +75,20 @@ def words_to_value(data): return int("".join([f"{i:016b}" for i in data[::-1]]), 2) +def value_to_words(data, n_words): + """ + Takes a integer, interprets it as a set of 16-bit integers + concatenated together, and splits it into a list of 16-bit numbers. + """ + + if not isinstance(data, int) or data < 0: + raise ValueError("Behavior is only defined for nonnegative integers.") + + # Convert to binary, split into 16-bit chunks, and then convert back to list of int + binary = f"{data:0b}".zfill(n_words * 16) + return [int(binary[i : i + 16], 2) for i in range(0, 16 * n_words, 16)][::-1] + + def check_value_fits_in_bits(value, n_bits): """ Rasies an exception if the provided value isn't an integer that cannot @@ -91,20 +105,6 @@ def check_value_fits_in_bits(value, n_bits): raise ValueError("Signed integer too large.") -def value_to_words(data, n_words): - """ - Takes a integer, interprets it as a set of 16-bit integers - concatenated together, and splits it into a list of 16-bit numbers. - """ - - if not isinstance(data, int) or data < 0: - raise ValueError("Behavior is only defined for nonnegative integers.") - - # Convert to binary, split into 16-bit chunks, and then convert back to list of int - binary = f"{data:0b}".zfill(n_words * 16) - return [int(binary[i : i + 16], 2) for i in range(0, 16 * n_words, 16)][::-1] - - def split_into_chunks(data, chunk_size): """ Split a list into a list of lists, where each sublist has length `chunk_size`. diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index 6715728..d40aada 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -4,7 +4,7 @@ from amaranth_boards.icestick import ICEStickPlatform from manta import Manta from manta.utils import * import pytest -from random import randint +from random import getrandbits class IOCoreLoopbackTest(Elaboratable): @@ -120,7 +120,7 @@ class IOCoreLoopbackTest(Elaboratable): # to the second input, and so on... for input, output in zip(inputs, outputs): width = self.config["cores"]["io_core"]["inputs"][input] - value = randint(0, 2**width - 1) + value = getrandbits(width) self.manta.io_core.set_probe(output, value) readback = self.manta.io_core.get_probe(input) diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py index 4edbd37..d99a72a 100644 --- a/test/test_io_core_sim.py +++ b/test/test_io_core_sim.py @@ -2,7 +2,7 @@ from amaranth import * from amaranth.sim import Simulator from manta.io_core import IOCore from manta.utils import * -from random import randint +from random import getrandbits probe0 = Signal(1) probe1 = Signal(2) @@ -51,7 +51,7 @@ def test_output_probe_buffer_initial_value(): def test_output_probes_are_writeable(): for o in outputs: addrs = io_core._memory_map[o.name]["addrs"] - test_value = randint(0, (2**o.width) - 1) + test_value = getrandbits(o.width) datas = value_to_words(test_value, len(addrs)) # write value to registers @@ -67,7 +67,7 @@ def test_output_probes_are_writeable(): def test_output_probes_update(): for o in outputs: addrs = io_core._memory_map[o.name]["addrs"] - test_value = randint(0, (2**o.width) - 1) + test_value = getrandbits(o.width) datas = value_to_words(test_value, len(addrs)) # write value to registers @@ -93,7 +93,7 @@ def test_output_probes_update(): def test_input_probes_update(): for i in inputs: # set input probe value - test_value = randint(0, (2**i.width) - 1) + test_value = getrandbits(i.width) yield i.eq(test_value) # pulse strobe register diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 27c1208..9cb73f3 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -4,7 +4,7 @@ from amaranth_boards.icestick import ICEStickPlatform from manta import Manta from manta.utils import * import pytest -from random import randint, sample +from random import randint, getrandbits from math import ceil, log2 """ @@ -105,7 +105,7 @@ class MemoryCoreLoopbackTest(Elaboratable): # Read and write randomly from the bus side for addr in jumble(range(self.depth)): - data = randint(0, 2**self.width - 1) + data = getrandbits(self.width) self.write_user_side(addr, data) self.verify_register(addr, data) diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 29bd73d..0c4fc32 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -1,6 +1,6 @@ from manta.memory_core import MemoryCore from manta.utils import * -from random import randint, choice +from random import randint, choice, getrandbits from math import ceil @@ -18,56 +18,56 @@ class MemoryCoreTests: range(self.base_addr, self.max_addr) ) # include the endpoint! self.user_addrs = list(range(self.mem_core._depth)) - self.model = {} + # A model of what each bus address contains + self.model = {i: 0 for i in self.bus_addrs} def bus_addrs_all_zero(self): for addr in self.bus_addrs: - yield from self.verify_bus_side(addr, 0) + yield from self.verify_bus_side(addr) def user_addrs_all_zero(self): for addr in self.user_addrs: - yield from self.verify_user_side(addr, 0) + yield from self.verify_user_side(addr) def bus_to_bus_functionality(self): - yield from self.one_bus_write_then_one_bus_read() - yield from self.multi_bus_writes_then_multi_bus_reads() + # yield from self.one_bus_write_then_one_bus_read() + # yield from self.multi_bus_writes_then_multi_bus_reads() yield from self.rand_bus_writes_rand_bus_reads() def user_to_bus_functionality(self): - yield from self.one_user_write_then_one_bus_read() - yield from self.multi_user_write_then_multi_bus_reads() + # yield from self.one_user_write_then_one_bus_read() + # yield from self.multi_user_write_then_multi_bus_reads() yield from self.rand_user_writes_rand_bus_reads() def bus_to_user_functionality(self): - yield from self.one_bus_write_then_one_user_read() - yield from self.multi_bus_write_then_multi_user_reads() + # yield from self.one_bus_write_then_one_user_read() + # yield from self.multi_bus_write_then_multi_user_reads() yield from self.rand_bus_writes_rand_user_reads() def user_to_user_functionality(self): - yield from self.one_user_write_then_one_user_read() - yield from self.multi_user_write_then_multi_user_read() + # yield from self.one_user_write_then_one_user_read() + # yield from self.multi_user_write_then_multi_user_read() yield from self.rand_user_write_rand_user_read() def one_bus_write_then_one_bus_read(self): for addr in self.bus_addrs: - data_width = self._get_data_width(addr) - data = randint(0, (2**data_width) - 1) + data_width = self.get_data_width(addr) + data = getrandbits(data_width) yield from self.write_bus_side(addr, data) - yield from self.verify_bus_side(addr, data) + yield from self.verify_bus_side(addr) def multi_bus_writes_then_multi_bus_reads(self): # write-write-write then read-read-read for addr in jumble(self.bus_addrs): - data_width = self._get_data_width(addr) - data = randint(0, (2**data_width) - 1) + data_width = self.get_data_width(addr) + data = getrandbits(data_width) - self.model[addr] = data yield from self.write_bus_side(addr, data) for addr in jumble(self.bus_addrs): - yield from self.verify_bus_side(addr, self.model[addr]) + yield from self.verify_bus_side(addr) def rand_bus_writes_rand_bus_reads(self): # random reads and writes in random orders @@ -76,43 +76,35 @@ class MemoryCoreTests: operation = choice(["read", "write"]) if operation == "read": - yield from self.verify_bus_side(addr, self.model[addr]) + yield from self.verify_bus_side(addr) elif operation == "write": - data_width = self._get_data_width(addr) - data = randint(0, (2**data_width) - 1) - self.model[addr] = data + data_width = self.get_data_width(addr) + data = getrandbits(data_width) yield from self.write_bus_side(addr, data) def one_user_write_then_one_bus_read(self): for user_addr in self.user_addrs: # write to user side - data = randint(0, (2**self.width) - 1) + data = getrandbits(self.width) yield from self.write_user_side(user_addr, data) # verify contents when read out from the bus - words = value_to_words(data, self.n_mems) - for i, word in enumerate(words): + for i in range(self.n_mems): bus_addr = self.base_addr + user_addr + (i * self.depth) - yield from self.verify_bus_side(bus_addr, word) + yield from self.verify_bus_side(bus_addr) def multi_user_write_then_multi_bus_reads(self): # write-write-write then read-read-read for user_addr in jumble(self.user_addrs): # write a random number to the user side - data = randint(0, (2**self.width) - 1) + data = getrandbits(self.width) yield from self.write_user_side(user_addr, data) - # convert value to words, and save to self.model - words = value_to_words(data, self.n_mems) - for i, word in enumerate(words): - bus_addr = self.base_addr + user_addr + (i * self.depth) - self.model[bus_addr] = word - # read out every bus_addr in random order for bus_addr in jumble(self.bus_addrs): - yield from self.verify_bus_side(bus_addr, self.model[bus_addr]) + yield from self.verify_bus_side(bus_addr) def rand_user_writes_rand_bus_reads(self): # random reads and writes in random orders @@ -128,23 +120,18 @@ class MemoryCoreTests: # read from bus side if operation == "read": for bus_addr in bus_addrs: - yield from self.verify_bus_side(bus_addr, self.model[bus_addr]) + yield from self.verify_bus_side(bus_addr) # write to user side elif operation == "write": - data = randint(0, (2**self.width) - 1) + data = getrandbits(self.width) yield from self.write_user_side(user_addr, data) - # save words just written to self.model - words = value_to_words(data, self.n_mems) - for addr, word in zip(bus_addrs, words): - self.model[addr] = word - def one_bus_write_then_one_user_read(self): for user_addr in self.user_addrs: # Try and set the value at the user address to a given value, # by writing to the appropriate memory locaitons on the bus side - data = randint(0, (2**self.width) - 1) + data = getrandbits(self.width) words = value_to_words(data, self.n_mems) @@ -152,25 +139,18 @@ class MemoryCoreTests: bus_addr = self.base_addr + user_addr + (i * self.depth) yield from self.write_bus_side(bus_addr, word) - yield from self.verify_user_side(user_addr, data) + yield from self.verify_user_side(user_addr) def multi_bus_write_then_multi_user_reads(self): # write-write-write then read-read-read for bus_addr in jumble(self.bus_addrs): - data_width = self._get_data_width(bus_addr) - data = randint(0, (2**data_width) - 1) + data_width = self.get_data_width(bus_addr) + data = getrandbits(data_width) - self.model[bus_addr] = data yield from self.write_bus_side(bus_addr, data) for user_addr in jumble(self.user_addrs): - bus_addrs = [ - self.base_addr + user_addr + (i * self.depth) - for i in range(self.n_mems) - ] - - value = words_to_value([self.model[addr] for addr in bus_addrs]) - yield from self.verify_user_side(user_addr, value) + yield from self.verify_user_side(user_addr) def rand_bus_writes_rand_user_reads(self): for _ in range(5 * self.depth): @@ -179,41 +159,31 @@ class MemoryCoreTests: # write random data to random bus address if operation == "write": bus_addr = randint(self.base_addr, self.max_addr - 1) - data_width = self._get_data_width(bus_addr) - data = randint(0, (2**data_width) - 1) - self.model[bus_addr] = data + data_width = self.get_data_width(bus_addr) + data = getrandbits(data_width) yield from self.write_bus_side(bus_addr, data) # read from random user_addr if operation == "read": user_addr = randint(0, self.depth - 1) - bus_addrs = [ - self.base_addr + user_addr + (i * self.depth) - for i in range(self.n_mems) - ] - - value = words_to_value([self.model[addr] for addr in bus_addrs]) - - yield from self.verify_user_side(user_addr, value) + yield from self.verify_user_side(user_addr) def one_user_write_then_one_user_read(self): for addr in self.user_addrs: - data = randint(0, (2**self.width) - 1) + data = getrandbits(self.width) yield from self.write_user_side(addr, data) - yield from self.verify_user_side(addr, data) + yield from self.verify_user_side(addr) def multi_user_write_then_multi_user_read(self): # write-write-write then read-read-read - self.foo = {} for user_addr in jumble(self.user_addrs): - data = randint(0, (2**self.width) - 1) - self.foo[user_addr] = data + data = getrandbits(self.width) yield from self.write_user_side(user_addr, data) for user_addr in jumble(self.user_addrs): - yield from self.verify_user_side(user_addr, self.foo[user_addr]) + yield from self.verify_user_side(user_addr) def rand_user_write_rand_user_read(self): # random reads and writes in random orders @@ -222,14 +192,13 @@ class MemoryCoreTests: operation = choice(["read", "write"]) if operation == "read": - yield from self.verify_user_side(user_addr, self.foo[user_addr]) + yield from self.verify_user_side(user_addr) elif operation == "write": - data = randint(0, (2**self.width) - 1) - self.foo[user_addr] = data + data = getrandbits(self.width) yield from self.write_user_side(user_addr, data) - def _get_data_width(self, addr): + def get_data_width(self, addr): # this part is a little hard to check since we might have a # memory at the end of the address space that's less than # 16-bits wide. so we'll have to calculate how wide our @@ -240,17 +209,29 @@ class MemoryCoreTests: else: return self.width % 16 - def verify_bus_side(self, addr, expected_data): - yield from verify_register(self.mem_core, addr, expected_data) + def verify_bus_side(self, addr): + yield from verify_register(self.mem_core, addr, self.model[addr]) for _ in range(4): yield def write_bus_side(self, addr, data): + self.model[addr] = data yield from write_register(self.mem_core, addr, data) for _ in range(4): yield - def verify_user_side(self, addr, expected_data): + def verify_user_side(self, addr): + # Determine the expected value on the user side by looking + # up the appropriate bus addresses in the model + + # Convert to bus addresses: + bus_words = [] + for i in range(self.n_mems): + bus_addr = self.base_addr + addr + (i * self.depth) + bus_words.append(self.model[bus_addr]) + + expected_data = words_to_value(bus_words) + yield self.mem_core.user_addr.eq(addr) yield yield @@ -262,6 +243,12 @@ class MemoryCoreTests: ) def write_user_side(self, addr, data): + # convert value to words, and save to self.model + words = value_to_words(data, self.n_mems) + for i, word in enumerate(words): + bus_addr = self.base_addr + addr + (i * self.depth) + self.model[bus_addr] = word + yield self.mem_core.user_addr.eq(addr) yield self.mem_core.user_data_in.eq(data) yield self.mem_core.user_write_enable.eq(1) @@ -294,11 +281,12 @@ def test_bidirectional(): test_bidirectional_testbench() + def test_bidirectional_random(): mem_core = MemoryCore( mode="bidirectional", width=randint(0, 128), - depth=randint(0, 2048), + depth=randint(0, 1024), base_addr=randint(0, 32678), interface=None, ) @@ -336,11 +324,12 @@ def test_fpga_to_host(): test_fpga_to_host_testbench() + def test_fpga_to_host_random(): mem_core = MemoryCore( mode="fpga_to_host", width=randint(0, 128), - depth=randint(0, 2048), + depth=randint(0, 1024), base_addr=randint(0, 32678), interface=None, ) @@ -373,11 +362,12 @@ def test_host_to_fpga(): test_host_to_fpga_testbench() + def test_host_to_fpga_random(): mem_core = MemoryCore( mode="host_to_fpga", width=randint(0, 128), - depth=randint(0, 2048), + depth=randint(0, 1024), base_addr=randint(0, 32678), interface=None, ) From d1a772784a54656f2dc5505c4b758d25b248ada6 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 11:26:31 -0800 Subject: [PATCH 76/89] add environment.sh for tool paths and serial ports --- environment.sh | 11 +++++++++++ test/test_io_core_hw.py | 5 +++-- test/test_logic_analyzer_hw.py | 5 +++-- test/test_mem_core_hw.py | 7 ++++--- 4 files changed, 21 insertions(+), 7 deletions(-) create mode 100644 environment.sh diff --git a/environment.sh b/environment.sh new file mode 100644 index 0000000..1c622d0 --- /dev/null +++ b/environment.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash + +export VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado + +export YOSYS=/tools/oss-cad-suite/bin/yosys +export NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr-ice40 +export ICEPACK=/tools/oss-cad-suite/bin/icepack +export ICEPROG=/tools/oss-cad-suite/bin/iceprog + +export NEXYS4DDR_PORT=/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0 +export ICESTICK_PORT=/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0 diff --git a/test/test_io_core_hw.py b/test/test_io_core_hw.py index d40aada..c5ab941 100644 --- a/test/test_io_core_hw.py +++ b/test/test_io_core_hw.py @@ -5,6 +5,7 @@ from manta import Manta from manta.utils import * import pytest from random import getrandbits +import os class IOCoreLoopbackTest(Elaboratable): @@ -143,11 +144,11 @@ class IOCoreLoopbackTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_output_probe_initial_values_xilinx(): - port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0" + port = os.environ["NEXYS4DDR_PORT"] IOCoreLoopbackTest(Nexys4DDRPlatform(), port).verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_output_probe_initial_values_ice40(): - port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0" + port = os.environ["ICESTICK_PORT"] IOCoreLoopbackTest(ICEStickPlatform(), port).verify() diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index 8a25335..f82bec2 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -4,6 +4,7 @@ from amaranth_boards.icestick import ICEStickPlatform from manta import Manta from manta.utils import * import pytest +import os class LogicAnalyzerCounterTest(Elaboratable): @@ -78,11 +79,11 @@ class LogicAnalyzerCounterTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_logic_analyzer_core_xilinx(): - port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0" + port = os.environ["NEXYS4DDR_PORT"] LogicAnalyzerCounterTest(Nexys4DDRPlatform(), port).verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_logic_analyzer_core_ice40(): - port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0" + port = os.environ["ICESTICK_PORT"] LogicAnalyzerCounterTest(ICEStickPlatform(), port).verify() diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 9cb73f3..242e4c6 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -4,8 +4,9 @@ from amaranth_boards.icestick import ICEStickPlatform from manta import Manta from manta.utils import * import pytest -from random import randint, getrandbits +from random import getrandbits from math import ceil, log2 +import os """ Fundamentally we want a function to generate a configuration (as a dictionary) @@ -112,13 +113,13 @@ class MemoryCoreLoopbackTest(Elaboratable): @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") def test_mem_core_xilinx(): - port = "/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_210292696307-if01-port0" + port = os.environ["NEXYS4DDR_PORT"] MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, port).verify() @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") def test_mem_core_ice40(): - port = "/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0" + port = os.environ["ICESTICK_PORT"] MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 2, port).verify() MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 512, port).verify() MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 1024, port).verify() From 71ec1174d1d9fe5c69f0d7a1f0bb29334ebd168d Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 14:53:27 -0800 Subject: [PATCH 77/89] add parameterized HW tests for all memory core modes --- src/manta/memory_core.py | 2 +- test/test_mem_core_hw.py | 145 +++++++++++++++++++++++--------------- test/test_mem_core_sim.py | 143 ++++++++----------------------------- 3 files changed, 117 insertions(+), 173 deletions(-) diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index edcbb74..f8c11b4 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -317,6 +317,6 @@ class MemoryCore(MantaCore): if not all(isinstance(d, int) for d in datas): raise TypeError("Write data must all be integers.") - bus_addrs = self._convert_user_to_bus_addr([addrs])[0] + bus_addrs = self._convert_user_to_bus_addr(addrs) bus_datas = [word for d in datas for word in value_to_words(d, self._n_mems)] self._interface.write(bus_addrs, bus_datas) diff --git a/test/test_mem_core_hw.py b/test/test_mem_core_hw.py index 242e4c6..fb8f853 100644 --- a/test/test_mem_core_hw.py +++ b/test/test_mem_core_hw.py @@ -8,16 +8,11 @@ from random import getrandbits from math import ceil, log2 import os -""" -Fundamentally we want a function to generate a configuration (as a dictionary) -for a memory core given the width, depth, and platform. This could be a random -configuration, or a standard one. -""" - class MemoryCoreLoopbackTest(Elaboratable): - def __init__(self, platform, width, depth, port): + def __init__(self, platform, mode, width, depth, port): self.platform = platform + self.mode = mode self.width = width self.depth = depth self.port = port @@ -28,19 +23,22 @@ class MemoryCoreLoopbackTest(Elaboratable): def platform_specific_config(self): return { "cores": { - "mem_core": { - "type": "memory", - "mode": "fpga_to_host", - "width": self.width, - "depth": self.depth, - }, "io_core": { "type": "io", "outputs": { - "addr": ceil(log2(self.depth)), - "data": self.width, - "we": 1, + "user_addr": ceil(log2(self.depth)), + "user_data_in": self.width, + "user_write_enable": 1, }, + "inputs": { + "user_data_out": self.width, + }, + }, + "mem_core": { + "type": "memory", + "mode": self.mode, + "width": self.width, + "depth": self.depth, }, }, "uart": { @@ -69,17 +67,21 @@ class MemoryCoreLoopbackTest(Elaboratable): uart_pins = platform.request("uart") - addr = self.get_probe("addr") - data = self.get_probe("data") - we = self.get_probe("we") + user_addr = self.get_probe("user_addr") + user_data_in = self.get_probe("user_data_in") + user_data_out = self.get_probe("user_data_out") + user_write_enable = self.get_probe("user_write_enable") - m.d.comb += [ - self.manta.mem_core.user_addr.eq(addr), - self.manta.mem_core.user_data_in.eq(data), - self.manta.mem_core.user_write_enable.eq(we), - self.manta.interface.rx.eq(uart_pins.rx.i), - uart_pins.tx.o.eq(self.manta.interface.tx), - ] + m.d.comb += self.manta.interface.rx.eq(uart_pins.rx.i) + m.d.comb += uart_pins.tx.o.eq(self.manta.interface.tx) + m.d.comb += self.manta.mem_core.user_addr.eq(user_addr) + + if self.mode in ["bidirectional", "fpga_to_host"]: + m.d.comb += self.manta.mem_core.user_data_in.eq(user_data_in) + m.d.comb += self.manta.mem_core.user_write_enable.eq(user_write_enable) + + if self.mode in ["bidirectional", "host_to_fpga"]: + m.d.comb += user_data_out.eq(self.manta.mem_core.user_data_out) return m @@ -87,48 +89,75 @@ class MemoryCoreLoopbackTest(Elaboratable): self.platform.build(self, do_program=True) def write_user_side(self, addr, data): - self.manta.io_core.set_probe("we", 0) - self.manta.io_core.set_probe("addr", addr) - self.manta.io_core.set_probe("data", data) - self.manta.io_core.set_probe("we", 1) - self.manta.io_core.set_probe("we", 0) + self.manta.io_core.set_probe("user_write_enable", 0) + self.manta.io_core.set_probe("user_addr", addr) + self.manta.io_core.set_probe("user_data_in", data) + self.manta.io_core.set_probe("user_write_enable", 1) + self.manta.io_core.set_probe("user_write_enable", 0) - def verify_register(self, addr, expected_data): - data = self.manta.mem_core.read(addr) - - if data != expected_data: - raise ValueError( - f"Memory read from {hex(addr)} returned {hex(data)} instead of {hex(expected_data)}." - ) + def read_user_side(self, addr): + self.manta.io_core.set_probe("user_write_enable", 0) + self.manta.io_core.set_probe("user_addr", addr) + return self.manta.io_core.get_probe("user_data_out") def verify(self): self.build_and_program() - # Read and write randomly from the bus side - for addr in jumble(range(self.depth)): - data = getrandbits(self.width) - self.write_user_side(addr, data) - self.verify_register(addr, data) + if self.mode in ["bidirectional", "host_to_fpga"]: + for addr in jumble(range(self.depth)): + + # Write a random balue to a random bus address + data = getrandbits(self.width) + self.manta.mem_core.write(addr, data) + + # Verify the same number is returned when reading on the user side + readback = self.read_user_side(addr) + if readback != data: + raise ValueError( + f"Memory read from {hex(addr)} returned {hex(data)} instead of {hex(readback)}." + ) + + if self.mode in ["bidirectional", "fpga_to_host"]: + for addr in jumble(range(self.depth)): + + # Write a random value to a random user address + data = getrandbits(self.width) + self.write_user_side(addr, data) + + # Verify the same number is returned when reading on the bus side + readback = self.manta.mem_core.read(addr) + if readback != data: + raise ValueError( + f"Memory read from {hex(addr)} returned {hex(data)} instead of {hex(readback)}." + ) + + +# Nexys4DDR Tests + +# Omit the bidirectional mode for now, pending completion of: +# https://github.com/amaranth-lang/amaranth/issues/1011 +modes = ["fpga_to_host", "host_to_fpga"] +widths = [1, 8, 14, 16, 33] +depths = [2, 512, 1024] +nexys4ddr_cases = [(m, w, d) for m in modes for w in widths for d in depths] @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed") -def test_mem_core_xilinx(): +@pytest.mark.parametrize("mode, width, depth", nexys4ddr_cases) +def test_mem_core_xilinx(mode, width, depth): port = os.environ["NEXYS4DDR_PORT"] - MemoryCoreLoopbackTest(Nexys4DDRPlatform(), 33, 1024, port).verify() + MemoryCoreLoopbackTest(Nexys4DDRPlatform(), mode, width, depth, port).verify() + + +# IceStick Tests +modes = ["fpga_to_host", "host_to_fpga"] +widths = [1, 8, 14, 16, 33] +depths = [2, 512, 1024] +ice40_cases = [(m, w, d) for m in modes for w in widths for d in depths] @pytest.mark.skipif(not ice40_tools_installed(), reason="no toolchain installed") -def test_mem_core_ice40(): +@pytest.mark.parametrize("mode, width, depth", ice40_cases) +def test_mem_core_ice40(mode, width, depth): port = os.environ["ICESTICK_PORT"] - MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 2, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 512, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 1, 1024, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 2, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 512, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 8, 1024, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 14, 512, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 14, 1024, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 16, 512, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 16, 1024, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 33, 512, port).verify() - MemoryCoreLoopbackTest(ICEStickPlatform(), 33, 1024, port).verify() + MemoryCoreLoopbackTest(ICEStickPlatform(), mode, width, depth, port).verify() diff --git a/test/test_mem_core_sim.py b/test/test_mem_core_sim.py index 0c4fc32..7fe2bae 100644 --- a/test/test_mem_core_sim.py +++ b/test/test_mem_core_sim.py @@ -2,6 +2,7 @@ from manta.memory_core import MemoryCore from manta.utils import * from random import randint, choice, getrandbits from math import ceil +import pytest class MemoryCoreTests: @@ -258,125 +259,39 @@ class MemoryCoreTests: yield self.mem_core.user_write_enable.eq(0) -def test_bidirectional(): - mem_core = MemoryCore( - mode="bidirectional", - width=23, - depth=512, - base_addr=0, - interface=None, - ) +modes = ["bidirectional", "fpga_to_host", "host_to_fpga"] +widths = [23, randint(0, 128)] +depths = [512, randint(0, 1024)] +base_addrs = [0, randint(0, 32678)] + +cases = [ + (m, w, d, ba) for m in modes for w in widths for d in depths for ba in base_addrs +] + + +@pytest.mark.parametrize("mode, width, depth, base_addr", cases) +def test_mem_core(mode, width, depth, base_addr): + mem_core = MemoryCore(mode, width, depth, base_addr, interface=None) tests = MemoryCoreTests(mem_core) @simulate(mem_core) - def test_bidirectional_testbench(): - yield from tests.bus_addrs_all_zero() - yield from tests.user_addrs_all_zero() + def testbench(): + if mode == "bidirectional": + yield from tests.bus_addrs_all_zero() + yield from tests.user_addrs_all_zero() - yield from tests.bus_to_bus_functionality() - yield from tests.user_to_bus_functionality() - yield from tests.bus_to_user_functionality() - yield from tests.user_to_user_functionality() + yield from tests.bus_to_bus_functionality() + yield from tests.user_to_bus_functionality() + yield from tests.bus_to_user_functionality() + yield from tests.user_to_user_functionality() - test_bidirectional_testbench() + if mode == "fpga_to_host": + yield from tests.bus_addrs_all_zero() + yield from tests.user_to_bus_functionality() + if mode == "host_to_fpga": + yield from tests.user_addrs_all_zero() + yield from tests.bus_to_user_functionality() -def test_bidirectional_random(): - mem_core = MemoryCore( - mode="bidirectional", - width=randint(0, 128), - depth=randint(0, 1024), - base_addr=randint(0, 32678), - interface=None, - ) - - tests = MemoryCoreTests(mem_core) - - @simulate(mem_core) - def test_bidirectional_random_testbench(): - yield from tests.bus_addrs_all_zero() - yield from tests.user_addrs_all_zero() - - yield from tests.bus_to_bus_functionality() - yield from tests.user_to_bus_functionality() - yield from tests.bus_to_user_functionality() - yield from tests.user_to_user_functionality() - - test_bidirectional_random_testbench() - - -def test_fpga_to_host(): - mem_core = MemoryCore( - mode="fpga_to_host", - width=23, - depth=512, - base_addr=0, - interface=None, - ) - - tests = MemoryCoreTests(mem_core) - - @simulate(mem_core) - def test_fpga_to_host_testbench(): - yield from tests.bus_addrs_all_zero() - yield from tests.user_to_bus_functionality() - - test_fpga_to_host_testbench() - - -def test_fpga_to_host_random(): - mem_core = MemoryCore( - mode="fpga_to_host", - width=randint(0, 128), - depth=randint(0, 1024), - base_addr=randint(0, 32678), - interface=None, - ) - - tests = MemoryCoreTests(mem_core) - - @simulate(mem_core) - def test_fpga_to_host_random_testbench(): - yield from tests.bus_addrs_all_zero() - yield from tests.user_to_bus_functionality() - - test_fpga_to_host_random_testbench() - - -def test_host_to_fpga(): - mem_core = MemoryCore( - mode="host_to_fpga", - width=23, - depth=512, - base_addr=0, - interface=None, - ) - - tests = MemoryCoreTests(mem_core) - - @simulate(mem_core) - def test_host_to_fpga_testbench(): - yield from tests.user_addrs_all_zero() - yield from tests.bus_to_user_functionality() - - test_host_to_fpga_testbench() - - -def test_host_to_fpga_random(): - mem_core = MemoryCore( - mode="host_to_fpga", - width=randint(0, 128), - depth=randint(0, 1024), - base_addr=randint(0, 32678), - interface=None, - ) - - tests = MemoryCoreTests(mem_core) - - @simulate(mem_core) - def test_host_to_fpga_random_testbench(): - yield from tests.user_addrs_all_zero() - yield from tests.bus_to_user_functionality() - - test_host_to_fpga_random_testbench() + testbench() From 69000872376dc0ccddfb91d5d7c700c830f70777 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 15:08:11 -0800 Subject: [PATCH 78/89] delete dead code from memory core --- src/manta/memory_core.py | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index f8c11b4..32237ab 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -114,36 +114,6 @@ class MemoryCore(MantaCore): start_addr = self._base_addr + (i * self._depth) stop_addr = start_addr + self._depth - 1 - # # Handle write ports - # if self._mode in ["host_to_fpga", "bidirectional"]: - # write_port = mem.write_port() - # m.d.sync += write_port.data.eq(self.bus_i.data) - # m.d.sync += write_port.en.eq(self.bus_i.rw) - # m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr) - - # # Handle read ports - # if self._mode in ["fpga_to_host", "bidirectional"]: - # read_port = mem.read_port() - # m.d.comb += read_port.en.eq(1) - - # # Throw BRAM operations into the front of the pipeline - # with m.If( - # (self.bus_i.valid) - # & (~self.bus_i.rw) - # & (self.bus_i.addr >= start_addr) - # & (self.bus_i.addr <= stop_addr) - # ): - # m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr) - - # # Pull BRAM reads from the back of the pipeline - # with m.If( - # (self._bus_pipe[2].valid) - # & (~self._bus_pipe[2].rw) - # & (self._bus_pipe[2].addr >= start_addr) - # & (self._bus_pipe[2].addr <= stop_addr) - # ): - # m.d.sync += self.bus_o.data.eq(read_port.data) - if self._mode == "fpga_to_host": read_port = mem.read_port() m.d.comb += read_port.en.eq(1) From bd452d94a476b8fd27fe003eb02dd5c8a3bb423c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 16:40:54 -0800 Subject: [PATCH 79/89] put test outputs in build/ --- src/manta/utils.py | 17 +++++++++++++---- test/test_logic_analyzer_hw.py | 8 +++++--- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/manta/utils.py b/src/manta/utils.py index a10af95..e2fa22c 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -2,7 +2,8 @@ from amaranth import * from amaranth.lib import data from amaranth.sim import Simulator from abc import ABC, abstractmethod -from random import sample, randint +from random import sample +from pathlib import Path import os @@ -114,22 +115,30 @@ def split_into_chunks(data, chunk_size): return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)] +def make_build_dir_if_it_does_not_exist_already(): + """ + Make build/ if it doesn't exist already. + """ + + Path("build").mkdir(parents=True, exist_ok=True) + def simulate(top): """ A decorator for running behavioral simulation using Amaranth's built-in simulator. Requires the top-level module in the simulation as an argument, - and automatically names VCD file containing the waveform dump with the name - of the function being decorated. + and automatically names VCD file containing the waveform dump in build/ + with the name of the function being decorated. """ def decorator(testbench): + make_build_dir_if_it_does_not_exist_already() def wrapper(*args, **kwargs): sim = Simulator(top) sim.add_clock(1e-6) # 1 MHz sim.add_sync_process(testbench) - vcd_path = testbench.__name__ + ".vcd" + vcd_path = "build/" + testbench.__name__ + ".vcd" with sim.write_vcd(vcd_path): sim.run() diff --git a/test/test_logic_analyzer_hw.py b/test/test_logic_analyzer_hw.py index f82bec2..e199db6 100644 --- a/test/test_logic_analyzer_hw.py +++ b/test/test_logic_analyzer_hw.py @@ -59,14 +59,16 @@ class LogicAnalyzerCounterTest(Elaboratable): self.build_and_program() cap = self.manta.la.capture() + make_build_dir_if_it_does_not_exist_already() + # check that VCD export works - cap.export_vcd("out.vcd") + cap.export_vcd("build/logic_analyzer_capture.vcd") # check that CSV export works - cap.export_csv("out.csv") + cap.export_csv("build/logic_analyzer_capture.csv") # check that Verilog export works - cap.export_playback_verilog("out.v") + cap.export_playback_verilog("build/logic_analzyer_capture_playback.v") # verify that each signal is just a counter modulo the width of the signal for name, width in self.manta.la._config["probes"].items(): From 21afbad7c4f958ae09c9450578dfd0f60bd704ac Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 21:47:03 -0800 Subject: [PATCH 80/89] add icestick IO core example --- examples/icestick/io_core/.gitignore | 1 + examples/icestick/io_core/build.sh | 4 ++ examples/icestick/io_core/manta.yaml | 16 ++++++ examples/icestick/io_core/run_io_core.py | 16 ++++++ examples/icestick/io_core/top_level.pcf | 67 ++++++++++++++++++++++++ examples/icestick/io_core/top_level.sv | 33 ++++++++++++ 6 files changed, 137 insertions(+) create mode 100644 examples/icestick/io_core/.gitignore create mode 100755 examples/icestick/io_core/build.sh create mode 100644 examples/icestick/io_core/manta.yaml create mode 100644 examples/icestick/io_core/run_io_core.py create mode 100644 examples/icestick/io_core/top_level.pcf create mode 100644 examples/icestick/io_core/top_level.sv diff --git a/examples/icestick/io_core/.gitignore b/examples/icestick/io_core/.gitignore new file mode 100644 index 0000000..a670a87 --- /dev/null +++ b/examples/icestick/io_core/.gitignore @@ -0,0 +1 @@ +!top_level.sv \ No newline at end of file diff --git a/examples/icestick/io_core/build.sh b/examples/icestick/io_core/build.sh new file mode 100755 index 0000000..a300d28 --- /dev/null +++ b/examples/icestick/io_core/build.sh @@ -0,0 +1,4 @@ +python3 -m manta gen manta.yaml manta.v +$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv +$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc +$ICEPACK top_level.asc top_level.bin \ No newline at end of file diff --git a/examples/icestick/io_core/manta.yaml b/examples/icestick/io_core/manta.yaml new file mode 100644 index 0000000..162311e --- /dev/null +++ b/examples/icestick/io_core/manta.yaml @@ -0,0 +1,16 @@ +--- +cores: + my_io_core: + type: io + + outputs: + LED0: 1 + LED1: 1 + LED2: 1 + LED3: 1 + LED4: 1 + +uart: + port: "/dev/ttyUSB3" + baudrate: 115200 + clock_freq: 12000000 \ No newline at end of file diff --git a/examples/icestick/io_core/run_io_core.py b/examples/icestick/io_core/run_io_core.py new file mode 100644 index 0000000..b1fd3d1 --- /dev/null +++ b/examples/icestick/io_core/run_io_core.py @@ -0,0 +1,16 @@ +from manta import Manta +from time import sleep + +manta = Manta('manta.yaml') + +i = 0 +while True: + # Turn each LED off + for j in range(5): + manta.my_io_core.set_probe(f"LED{j}", 0) + + # Turn one LED back on + manta.my_io_core.set_probe(f"LED{i}", 1) + + i = (i+1) % 5 + sleep(0.1) \ No newline at end of file diff --git a/examples/icestick/io_core/top_level.pcf b/examples/icestick/io_core/top_level.pcf new file mode 100644 index 0000000..d042aa0 --- /dev/null +++ b/examples/icestick/io_core/top_level.pcf @@ -0,0 +1,67 @@ +# Generic iCEstick placement constraints file + +# Red LEDs +set_io LED0 99 +set_io LED1 98 +set_io LED2 97 +set_io LED3 96 + +# Green LED +set_io LED4 95 + +# IrDA port +#set_io RXD 106 +#set_io TXD 105 +#set_io SD 107 + +# Pmod connector +#set_io PIO1_02 78 # Pin 1 +#set_io PIO1_03 79 # Pin 2 +#set_io PIO1_04 80 # Pin 3 +#set_io PIO1_05 81 # Pin 4 +#set_io PIO1_06 87 # Pin 7 +#set_io PIO1_07 88 # Pin 8 +#set_io PIO1_08 90 # Pin 9 +#set_io PIO1_09 91 # Pin 10 + +# Connector J1 +#set_io PIO0_02 112 # Pin 3 +#set_io PIO0_03 113 # Pin 4 +#set_io PIO0_04 114 # Pin 5 +#set_io PIO0_05 115 # Pin 6 +#set_io PIO0_06 116 # Pin 7 +#set_io PIO0_07 117 # Pin 8 +#set_io PIO0_08 118 # Pin 9 +#set_io PIO0_09 119 # Pin 10 + +# Connector J3 +#set_io PIO2_17 62 # Pin 3 +#set_io PIO2_16 61 # Pin 4 +#set_io PIO2_15 60 # Pin 5 +#set_io PIO2_14 56 # Pin 6 +#set_io PIO2_13 48 # Pin 7 +#set_io PIO2_12 47 # Pin 8 +#set_io PIO2_11 45 # Pin 9 +#set_io PIO2_10 44 # Pin 10 + +# FTDI Port B UART +#set_io DCDn 1 +#set_io DSRn 2 +#set_io DTRn 3 +#set_io CTSn 4 +#set_io RTSn 7 +set_io rs232_tx_ttl 8 +set_io rs232_rx_ttl 9 + +# SPI +#set_io SPI_SCK 70 +#set_io SPI_SI 68 +#set_io SPI_SO 67 +#set_io SPI_SS_B 71 + +# Configuration pins +#set_io CDONE 65 +#set_io CRESET_B 66 + +# 12 MHz clock +set_io clk 21 diff --git a/examples/icestick/io_core/top_level.sv b/examples/icestick/io_core/top_level.sv new file mode 100644 index 0000000..f0740f1 --- /dev/null +++ b/examples/icestick/io_core/top_level.sv @@ -0,0 +1,33 @@ +`default_nettype none +`timescale 1ns / 1ps + +`include "manta.v" + +module top_level ( + input wire clk, + + output logic LED0, + output logic LED1, + output logic LED2, + output logic LED3, + output logic LED4, + + input wire rs232_rx_ttl, + output logic rs232_tx_ttl + ); + + manta manta_inst ( + .clk(clk), + .rst(0), + + .rx(rs232_rx_ttl), + .tx(rs232_tx_ttl), + + .LED0(LED0), + .LED1(LED1), + .LED2(LED2), + .LED3(LED3), + .LED4(LED4)); +endmodule + +`default_nettype wire \ No newline at end of file From 05b9b450e848f2cf9c74619d84b0f8fe5aeddf61 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 22:05:24 -0800 Subject: [PATCH 81/89] add logic analyzer icestick example --- .../io_core/{run_io_core.py => blinky.py} | 0 .../verilog/icestick/io_core_uart/.gitignore | 1 + .../verilog/icestick/io_core_uart/blinky.py | 16 +++++ .../verilog/icestick/io_core_uart/build.sh | 4 ++ .../verilog/icestick/io_core_uart/manta.yaml | 16 +++++ .../icestick/io_core_uart/top_level.pcf | 67 +++++++++++++++++++ .../icestick/io_core_uart/top_level.sv | 33 +++++++++ .../icestick/logic_analyzer_uart/.gitignore | 1 + .../icestick/logic_analyzer_uart/build.sh | 4 ++ .../icestick/logic_analyzer_uart/manta.yaml | 19 ++++++ .../logic_analyzer_uart/top_level.pcf | 67 +++++++++++++++++++ .../icestick/logic_analyzer_uart/top_level.sv | 38 +++++++++++ 12 files changed, 266 insertions(+) rename examples/icestick/io_core/{run_io_core.py => blinky.py} (100%) create mode 100644 examples/verilog/icestick/io_core_uart/.gitignore create mode 100644 examples/verilog/icestick/io_core_uart/blinky.py create mode 100755 examples/verilog/icestick/io_core_uart/build.sh create mode 100644 examples/verilog/icestick/io_core_uart/manta.yaml create mode 100644 examples/verilog/icestick/io_core_uart/top_level.pcf create mode 100644 examples/verilog/icestick/io_core_uart/top_level.sv create mode 100644 examples/verilog/icestick/logic_analyzer_uart/.gitignore create mode 100755 examples/verilog/icestick/logic_analyzer_uart/build.sh create mode 100644 examples/verilog/icestick/logic_analyzer_uart/manta.yaml create mode 100644 examples/verilog/icestick/logic_analyzer_uart/top_level.pcf create mode 100644 examples/verilog/icestick/logic_analyzer_uart/top_level.sv diff --git a/examples/icestick/io_core/run_io_core.py b/examples/icestick/io_core/blinky.py similarity index 100% rename from examples/icestick/io_core/run_io_core.py rename to examples/icestick/io_core/blinky.py diff --git a/examples/verilog/icestick/io_core_uart/.gitignore b/examples/verilog/icestick/io_core_uart/.gitignore new file mode 100644 index 0000000..a670a87 --- /dev/null +++ b/examples/verilog/icestick/io_core_uart/.gitignore @@ -0,0 +1 @@ +!top_level.sv \ No newline at end of file diff --git a/examples/verilog/icestick/io_core_uart/blinky.py b/examples/verilog/icestick/io_core_uart/blinky.py new file mode 100644 index 0000000..b1fd3d1 --- /dev/null +++ b/examples/verilog/icestick/io_core_uart/blinky.py @@ -0,0 +1,16 @@ +from manta import Manta +from time import sleep + +manta = Manta('manta.yaml') + +i = 0 +while True: + # Turn each LED off + for j in range(5): + manta.my_io_core.set_probe(f"LED{j}", 0) + + # Turn one LED back on + manta.my_io_core.set_probe(f"LED{i}", 1) + + i = (i+1) % 5 + sleep(0.1) \ No newline at end of file diff --git a/examples/verilog/icestick/io_core_uart/build.sh b/examples/verilog/icestick/io_core_uart/build.sh new file mode 100755 index 0000000..a300d28 --- /dev/null +++ b/examples/verilog/icestick/io_core_uart/build.sh @@ -0,0 +1,4 @@ +python3 -m manta gen manta.yaml manta.v +$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv +$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc +$ICEPACK top_level.asc top_level.bin \ No newline at end of file diff --git a/examples/verilog/icestick/io_core_uart/manta.yaml b/examples/verilog/icestick/io_core_uart/manta.yaml new file mode 100644 index 0000000..162311e --- /dev/null +++ b/examples/verilog/icestick/io_core_uart/manta.yaml @@ -0,0 +1,16 @@ +--- +cores: + my_io_core: + type: io + + outputs: + LED0: 1 + LED1: 1 + LED2: 1 + LED3: 1 + LED4: 1 + +uart: + port: "/dev/ttyUSB3" + baudrate: 115200 + clock_freq: 12000000 \ No newline at end of file diff --git a/examples/verilog/icestick/io_core_uart/top_level.pcf b/examples/verilog/icestick/io_core_uart/top_level.pcf new file mode 100644 index 0000000..d042aa0 --- /dev/null +++ b/examples/verilog/icestick/io_core_uart/top_level.pcf @@ -0,0 +1,67 @@ +# Generic iCEstick placement constraints file + +# Red LEDs +set_io LED0 99 +set_io LED1 98 +set_io LED2 97 +set_io LED3 96 + +# Green LED +set_io LED4 95 + +# IrDA port +#set_io RXD 106 +#set_io TXD 105 +#set_io SD 107 + +# Pmod connector +#set_io PIO1_02 78 # Pin 1 +#set_io PIO1_03 79 # Pin 2 +#set_io PIO1_04 80 # Pin 3 +#set_io PIO1_05 81 # Pin 4 +#set_io PIO1_06 87 # Pin 7 +#set_io PIO1_07 88 # Pin 8 +#set_io PIO1_08 90 # Pin 9 +#set_io PIO1_09 91 # Pin 10 + +# Connector J1 +#set_io PIO0_02 112 # Pin 3 +#set_io PIO0_03 113 # Pin 4 +#set_io PIO0_04 114 # Pin 5 +#set_io PIO0_05 115 # Pin 6 +#set_io PIO0_06 116 # Pin 7 +#set_io PIO0_07 117 # Pin 8 +#set_io PIO0_08 118 # Pin 9 +#set_io PIO0_09 119 # Pin 10 + +# Connector J3 +#set_io PIO2_17 62 # Pin 3 +#set_io PIO2_16 61 # Pin 4 +#set_io PIO2_15 60 # Pin 5 +#set_io PIO2_14 56 # Pin 6 +#set_io PIO2_13 48 # Pin 7 +#set_io PIO2_12 47 # Pin 8 +#set_io PIO2_11 45 # Pin 9 +#set_io PIO2_10 44 # Pin 10 + +# FTDI Port B UART +#set_io DCDn 1 +#set_io DSRn 2 +#set_io DTRn 3 +#set_io CTSn 4 +#set_io RTSn 7 +set_io rs232_tx_ttl 8 +set_io rs232_rx_ttl 9 + +# SPI +#set_io SPI_SCK 70 +#set_io SPI_SI 68 +#set_io SPI_SO 67 +#set_io SPI_SS_B 71 + +# Configuration pins +#set_io CDONE 65 +#set_io CRESET_B 66 + +# 12 MHz clock +set_io clk 21 diff --git a/examples/verilog/icestick/io_core_uart/top_level.sv b/examples/verilog/icestick/io_core_uart/top_level.sv new file mode 100644 index 0000000..f0740f1 --- /dev/null +++ b/examples/verilog/icestick/io_core_uart/top_level.sv @@ -0,0 +1,33 @@ +`default_nettype none +`timescale 1ns / 1ps + +`include "manta.v" + +module top_level ( + input wire clk, + + output logic LED0, + output logic LED1, + output logic LED2, + output logic LED3, + output logic LED4, + + input wire rs232_rx_ttl, + output logic rs232_tx_ttl + ); + + manta manta_inst ( + .clk(clk), + .rst(0), + + .rx(rs232_rx_ttl), + .tx(rs232_tx_ttl), + + .LED0(LED0), + .LED1(LED1), + .LED2(LED2), + .LED3(LED3), + .LED4(LED4)); +endmodule + +`default_nettype wire \ No newline at end of file diff --git a/examples/verilog/icestick/logic_analyzer_uart/.gitignore b/examples/verilog/icestick/logic_analyzer_uart/.gitignore new file mode 100644 index 0000000..a670a87 --- /dev/null +++ b/examples/verilog/icestick/logic_analyzer_uart/.gitignore @@ -0,0 +1 @@ +!top_level.sv \ No newline at end of file diff --git a/examples/verilog/icestick/logic_analyzer_uart/build.sh b/examples/verilog/icestick/logic_analyzer_uart/build.sh new file mode 100755 index 0000000..a300d28 --- /dev/null +++ b/examples/verilog/icestick/logic_analyzer_uart/build.sh @@ -0,0 +1,4 @@ +python3 -m manta gen manta.yaml manta.v +$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv +$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc +$ICEPACK top_level.asc top_level.bin \ No newline at end of file diff --git a/examples/verilog/icestick/logic_analyzer_uart/manta.yaml b/examples/verilog/icestick/logic_analyzer_uart/manta.yaml new file mode 100644 index 0000000..6422e2e --- /dev/null +++ b/examples/verilog/icestick/logic_analyzer_uart/manta.yaml @@ -0,0 +1,19 @@ +--- +cores: + my_logic_analyzer: + type: logic_analyzer + sample_depth: 256 + + probes: + probe0: 1 + probe1: 4 + probe2: 8 + probe3: 16 + + triggers: + - probe2 EQ 3 + +uart: + port: "/dev/ttyUSB3" + baudrate: 115200 + clock_freq: 12000000 \ No newline at end of file diff --git a/examples/verilog/icestick/logic_analyzer_uart/top_level.pcf b/examples/verilog/icestick/logic_analyzer_uart/top_level.pcf new file mode 100644 index 0000000..d042aa0 --- /dev/null +++ b/examples/verilog/icestick/logic_analyzer_uart/top_level.pcf @@ -0,0 +1,67 @@ +# Generic iCEstick placement constraints file + +# Red LEDs +set_io LED0 99 +set_io LED1 98 +set_io LED2 97 +set_io LED3 96 + +# Green LED +set_io LED4 95 + +# IrDA port +#set_io RXD 106 +#set_io TXD 105 +#set_io SD 107 + +# Pmod connector +#set_io PIO1_02 78 # Pin 1 +#set_io PIO1_03 79 # Pin 2 +#set_io PIO1_04 80 # Pin 3 +#set_io PIO1_05 81 # Pin 4 +#set_io PIO1_06 87 # Pin 7 +#set_io PIO1_07 88 # Pin 8 +#set_io PIO1_08 90 # Pin 9 +#set_io PIO1_09 91 # Pin 10 + +# Connector J1 +#set_io PIO0_02 112 # Pin 3 +#set_io PIO0_03 113 # Pin 4 +#set_io PIO0_04 114 # Pin 5 +#set_io PIO0_05 115 # Pin 6 +#set_io PIO0_06 116 # Pin 7 +#set_io PIO0_07 117 # Pin 8 +#set_io PIO0_08 118 # Pin 9 +#set_io PIO0_09 119 # Pin 10 + +# Connector J3 +#set_io PIO2_17 62 # Pin 3 +#set_io PIO2_16 61 # Pin 4 +#set_io PIO2_15 60 # Pin 5 +#set_io PIO2_14 56 # Pin 6 +#set_io PIO2_13 48 # Pin 7 +#set_io PIO2_12 47 # Pin 8 +#set_io PIO2_11 45 # Pin 9 +#set_io PIO2_10 44 # Pin 10 + +# FTDI Port B UART +#set_io DCDn 1 +#set_io DSRn 2 +#set_io DTRn 3 +#set_io CTSn 4 +#set_io RTSn 7 +set_io rs232_tx_ttl 8 +set_io rs232_rx_ttl 9 + +# SPI +#set_io SPI_SCK 70 +#set_io SPI_SI 68 +#set_io SPI_SO 67 +#set_io SPI_SS_B 71 + +# Configuration pins +#set_io CDONE 65 +#set_io CRESET_B 66 + +# 12 MHz clock +set_io clk 21 diff --git a/examples/verilog/icestick/logic_analyzer_uart/top_level.sv b/examples/verilog/icestick/logic_analyzer_uart/top_level.sv new file mode 100644 index 0000000..620be4b --- /dev/null +++ b/examples/verilog/icestick/logic_analyzer_uart/top_level.sv @@ -0,0 +1,38 @@ +`default_nettype none +`timescale 1ns / 1ps + +`include "manta.v" + +module top_level ( + input wire clk, + + input wire rs232_rx_ttl, + output logic rs232_tx_ttl + ); + + logic probe0; + logic [3:0] probe1; + logic [7:0] probe2; + logic [15:0] probe3; + + always @(posedge clk) begin + probe0 <= probe0 + 1; + probe1 <= probe1 + 1; + probe2 <= probe2 + 1; + probe3 <= probe3 + 1; + end + + manta manta_inst ( + .clk(clk), + .rst(0), + + .rx(rs232_rx_ttl), + .tx(rs232_tx_ttl), + + .probe0(probe0), + .probe1(probe1), + .probe2(probe2), + .probe3(probe3)); +endmodule + +`default_nettype wire \ No newline at end of file From 60066ccdcab17a938c23c1ff692482209aac0bf4 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 23:07:20 -0800 Subject: [PATCH 82/89] add examples for the Nexys4DDR, bump version to 1.0.0 --- .gitignore | 8 +- examples/icestick/io_core/blinky.py | 16 -- examples/icestick/io_core/build.sh | 4 - examples/icestick/io_core/manta.yaml | 16 -- examples/icestick/io_core/top_level.pcf | 67 ----- examples/icestick/io_core/top_level.sv | 33 --- .../verilog/icestick/io_core_uart/blinky.py | 6 +- .../.Xil/top_level_propImpl.xdc | 71 +++++ .../host_to_fpga_mem_uart}/.gitignore | 0 .../nexys_a7/host_to_fpga_mem_uart/build.sh | 3 + .../nexys_a7/host_to_fpga_mem_uart/build.tcl | 36 +++ .../nexys_a7/host_to_fpga_mem_uart/manta.yaml | 12 + .../host_to_fpga_mem_uart/top_level.sv | 23 ++ .../host_to_fpga_mem_uart/top_level.xdc | 254 ++++++++++++++++++ .../nexys_a7/host_to_fpga_mem_uart/write.py | 8 + .../io_core_uart/.Xil/top_level_propImpl.xdc | 93 +++++++ .../verilog/nexys_a7/io_core_uart/.gitignore | 1 + .../verilog/nexys_a7/io_core_uart/blinky.py | 25 ++ .../verilog/nexys_a7/io_core_uart/build.sh | 3 + .../verilog/nexys_a7/io_core_uart/build.tcl | 36 +++ .../verilog/nexys_a7/io_core_uart/manta.yaml | 26 ++ .../nexys_a7/io_core_uart/top_level.sv | 49 ++++ .../nexys_a7/io_core_uart/top_level.xdc | 254 ++++++++++++++++++ .../.Xil/top_level_propImpl.xdc | 11 + .../nexys_a7/logic_analyzer_uart/.gitignore | 1 + .../nexys_a7/logic_analyzer_uart/build.sh | 3 + .../nexys_a7/logic_analyzer_uart/build.tcl | 36 +++ .../nexys_a7/logic_analyzer_uart/manta.yaml | 19 ++ .../nexys_a7/logic_analyzer_uart/top_level.sv | 37 +++ .../logic_analyzer_uart/top_level.xdc | 254 ++++++++++++++++++ pyproject.toml | 2 +- src/manta/memory_core.py | 26 +- src/manta/utils.py | 2 + 33 files changed, 1280 insertions(+), 155 deletions(-) delete mode 100644 examples/icestick/io_core/blinky.py delete mode 100755 examples/icestick/io_core/build.sh delete mode 100644 examples/icestick/io_core/manta.yaml delete mode 100644 examples/icestick/io_core/top_level.pcf delete mode 100644 examples/icestick/io_core/top_level.sv create mode 100644 examples/verilog/nexys_a7/host_to_fpga_mem_uart/.Xil/top_level_propImpl.xdc rename examples/{icestick/io_core => verilog/nexys_a7/host_to_fpga_mem_uart}/.gitignore (100%) create mode 100755 examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.sh create mode 100644 examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.tcl create mode 100644 examples/verilog/nexys_a7/host_to_fpga_mem_uart/manta.yaml create mode 100644 examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.sv create mode 100644 examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc create mode 100644 examples/verilog/nexys_a7/host_to_fpga_mem_uart/write.py create mode 100644 examples/verilog/nexys_a7/io_core_uart/.Xil/top_level_propImpl.xdc create mode 100644 examples/verilog/nexys_a7/io_core_uart/.gitignore create mode 100644 examples/verilog/nexys_a7/io_core_uart/blinky.py create mode 100755 examples/verilog/nexys_a7/io_core_uart/build.sh create mode 100644 examples/verilog/nexys_a7/io_core_uart/build.tcl create mode 100644 examples/verilog/nexys_a7/io_core_uart/manta.yaml create mode 100644 examples/verilog/nexys_a7/io_core_uart/top_level.sv create mode 100644 examples/verilog/nexys_a7/io_core_uart/top_level.xdc create mode 100644 examples/verilog/nexys_a7/logic_analyzer_uart/.Xil/top_level_propImpl.xdc create mode 100644 examples/verilog/nexys_a7/logic_analyzer_uart/.gitignore create mode 100755 examples/verilog/nexys_a7/logic_analyzer_uart/build.sh create mode 100644 examples/verilog/nexys_a7/logic_analyzer_uart/build.tcl create mode 100644 examples/verilog/nexys_a7/logic_analyzer_uart/manta.yaml create mode 100644 examples/verilog/nexys_a7/logic_analyzer_uart/top_level.sv create mode 100644 examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc diff --git a/.gitignore b/.gitignore index 48226f2..6ef1d49 100644 --- a/.gitignore +++ b/.gitignore @@ -23,5 +23,9 @@ build/ *.bin *.bit *.out -*.xdc -.Xil/* \ No newline at end of file +.Xil/* + +# Yosys/IceStorm files from the same +*.asc +*.bin +*.json \ No newline at end of file diff --git a/examples/icestick/io_core/blinky.py b/examples/icestick/io_core/blinky.py deleted file mode 100644 index b1fd3d1..0000000 --- a/examples/icestick/io_core/blinky.py +++ /dev/null @@ -1,16 +0,0 @@ -from manta import Manta -from time import sleep - -manta = Manta('manta.yaml') - -i = 0 -while True: - # Turn each LED off - for j in range(5): - manta.my_io_core.set_probe(f"LED{j}", 0) - - # Turn one LED back on - manta.my_io_core.set_probe(f"LED{i}", 1) - - i = (i+1) % 5 - sleep(0.1) \ No newline at end of file diff --git a/examples/icestick/io_core/build.sh b/examples/icestick/io_core/build.sh deleted file mode 100755 index a300d28..0000000 --- a/examples/icestick/io_core/build.sh +++ /dev/null @@ -1,4 +0,0 @@ -python3 -m manta gen manta.yaml manta.v -$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv -$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc -$ICEPACK top_level.asc top_level.bin \ No newline at end of file diff --git a/examples/icestick/io_core/manta.yaml b/examples/icestick/io_core/manta.yaml deleted file mode 100644 index 162311e..0000000 --- a/examples/icestick/io_core/manta.yaml +++ /dev/null @@ -1,16 +0,0 @@ ---- -cores: - my_io_core: - type: io - - outputs: - LED0: 1 - LED1: 1 - LED2: 1 - LED3: 1 - LED4: 1 - -uart: - port: "/dev/ttyUSB3" - baudrate: 115200 - clock_freq: 12000000 \ No newline at end of file diff --git a/examples/icestick/io_core/top_level.pcf b/examples/icestick/io_core/top_level.pcf deleted file mode 100644 index d042aa0..0000000 --- a/examples/icestick/io_core/top_level.pcf +++ /dev/null @@ -1,67 +0,0 @@ -# Generic iCEstick placement constraints file - -# Red LEDs -set_io LED0 99 -set_io LED1 98 -set_io LED2 97 -set_io LED3 96 - -# Green LED -set_io LED4 95 - -# IrDA port -#set_io RXD 106 -#set_io TXD 105 -#set_io SD 107 - -# Pmod connector -#set_io PIO1_02 78 # Pin 1 -#set_io PIO1_03 79 # Pin 2 -#set_io PIO1_04 80 # Pin 3 -#set_io PIO1_05 81 # Pin 4 -#set_io PIO1_06 87 # Pin 7 -#set_io PIO1_07 88 # Pin 8 -#set_io PIO1_08 90 # Pin 9 -#set_io PIO1_09 91 # Pin 10 - -# Connector J1 -#set_io PIO0_02 112 # Pin 3 -#set_io PIO0_03 113 # Pin 4 -#set_io PIO0_04 114 # Pin 5 -#set_io PIO0_05 115 # Pin 6 -#set_io PIO0_06 116 # Pin 7 -#set_io PIO0_07 117 # Pin 8 -#set_io PIO0_08 118 # Pin 9 -#set_io PIO0_09 119 # Pin 10 - -# Connector J3 -#set_io PIO2_17 62 # Pin 3 -#set_io PIO2_16 61 # Pin 4 -#set_io PIO2_15 60 # Pin 5 -#set_io PIO2_14 56 # Pin 6 -#set_io PIO2_13 48 # Pin 7 -#set_io PIO2_12 47 # Pin 8 -#set_io PIO2_11 45 # Pin 9 -#set_io PIO2_10 44 # Pin 10 - -# FTDI Port B UART -#set_io DCDn 1 -#set_io DSRn 2 -#set_io DTRn 3 -#set_io CTSn 4 -#set_io RTSn 7 -set_io rs232_tx_ttl 8 -set_io rs232_rx_ttl 9 - -# SPI -#set_io SPI_SCK 70 -#set_io SPI_SI 68 -#set_io SPI_SO 67 -#set_io SPI_SS_B 71 - -# Configuration pins -#set_io CDONE 65 -#set_io CRESET_B 66 - -# 12 MHz clock -set_io clk 21 diff --git a/examples/icestick/io_core/top_level.sv b/examples/icestick/io_core/top_level.sv deleted file mode 100644 index f0740f1..0000000 --- a/examples/icestick/io_core/top_level.sv +++ /dev/null @@ -1,33 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -`include "manta.v" - -module top_level ( - input wire clk, - - output logic LED0, - output logic LED1, - output logic LED2, - output logic LED3, - output logic LED4, - - input wire rs232_rx_ttl, - output logic rs232_tx_ttl - ); - - manta manta_inst ( - .clk(clk), - .rst(0), - - .rx(rs232_rx_ttl), - .tx(rs232_tx_ttl), - - .LED0(LED0), - .LED1(LED1), - .LED2(LED2), - .LED3(LED3), - .LED4(LED4)); -endmodule - -`default_nettype wire \ No newline at end of file diff --git a/examples/verilog/icestick/io_core_uart/blinky.py b/examples/verilog/icestick/io_core_uart/blinky.py index b1fd3d1..95d3dec 100644 --- a/examples/verilog/icestick/io_core_uart/blinky.py +++ b/examples/verilog/icestick/io_core_uart/blinky.py @@ -1,7 +1,7 @@ from manta import Manta from time import sleep -manta = Manta('manta.yaml') +manta = Manta("manta.yaml") i = 0 while True: @@ -12,5 +12,5 @@ while True: # Turn one LED back on manta.my_io_core.set_probe(f"LED{i}", 1) - i = (i+1) % 5 - sleep(0.1) \ No newline at end of file + i = (i + 1) % 5 + sleep(0.1) diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/.Xil/top_level_propImpl.xdc b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/.Xil/top_level_propImpl.xdc new file mode 100644 index 0000000..a975d04 --- /dev/null +++ b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/.Xil/top_level_propImpl.xdc @@ -0,0 +1,71 @@ +set_property SRC_FILE_INFO {cfile:/home/fischerm/manta/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc rfile:../top_level.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property src_info {type:XDC file:1 line:219 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property src_info {type:XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out diff --git a/examples/icestick/io_core/.gitignore b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/.gitignore similarity index 100% rename from examples/icestick/io_core/.gitignore rename to examples/verilog/nexys_a7/host_to_fpga_mem_uart/.gitignore diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.sh b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.sh new file mode 100755 index 0000000..829824b --- /dev/null +++ b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.sh @@ -0,0 +1,3 @@ +python3 -m manta gen manta.yaml manta.v +mkdir -p build/ +$VIVADO -mode batch -source build.tcl \ No newline at end of file diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.tcl b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.tcl new file mode 100644 index 0000000..0e7570e --- /dev/null +++ b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/build.tcl @@ -0,0 +1,36 @@ +#!/usr/bin/tclsh + +set partNum xc7a100tcsg324-1 +set outputDir build + +read_verilog -sv [ glob *.{sv,v,svh,vh} ] +read_xdc top_level.xdc + +set_part $partNum + +# synth +synth_design -top top_level -part $partNum -verbose +report_utilization -file $outputDir/post_synth_util.rpt +report_timing_summary -file $outputDir/post_synth_timing_summary.rpt +report_timing -file $outputDir/post_synth_timing.rpt + +# place +opt_design +place_design +phys_opt_design +report_utilization -file $outputDir/post_place_util.rpt + +report_clock_utilization -file $outputDir/clock_util.rpt +report_timing_summary -file $outputDir/post_place_timing_summary.rpt +report_timing -file $outputDir/post_place_timing.rpt + +# route design and generate bitstream +route_design -directive Explore +write_bitstream -force $outputDir/out.bit + +report_route_status -file $outputDir/post_route_status.rpt +report_timing_summary -file $outputDir/post_route_timing_summary.rpt +report_timing -file $outputDir/post_route_timing.rpt +report_power -file $outputDir/post_route_power.rpt +report_drc -file $outputDir/post_imp_drc.rpt +write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/manta.yaml b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/manta.yaml new file mode 100644 index 0000000..382458c --- /dev/null +++ b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/manta.yaml @@ -0,0 +1,12 @@ +--- +cores: + my_memory: + type: memory + mode: host_to_fpga + width: 16 + depth: 1024 + +uart: + port: "/dev/ttyUSB1" + baudrate: 115200 + clock_freq: 100000000 \ No newline at end of file diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.sv b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.sv new file mode 100644 index 0000000..7272c36 --- /dev/null +++ b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.sv @@ -0,0 +1,23 @@ +`default_nettype none +`timescale 1ns / 1ps + +module top_level ( + input wire clk, + input wire [15:0] sw, + output logic [15:0] led, + + input wire uart_txd_in, + output logic uart_rxd_out); + + manta manta_inst ( + .clk(clk), + + .rx(uart_txd_in), + .tx(uart_rxd_out), + + .user_addr(sw), + .user_data_out(led)); + +endmodule + +`default_nettype wire \ No newline at end of file diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc new file mode 100644 index 0000000..6184324 --- /dev/null +++ b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc @@ -0,0 +1,254 @@ +## This file is a general .xdc for the Nexys4 DDR Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 + +## Clock signal - uncomment _both_ of these lines to create clk_100mhz +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; + +##Switches + +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +# +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +# +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + + diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/write.py b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/write.py new file mode 100644 index 0000000..3c62506 --- /dev/null +++ b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/write.py @@ -0,0 +1,8 @@ +from manta import Manta + +m = Manta("manta.yaml") + +# Memory addresses can be written to in Python, and then be read out by +# flipping the switches on the FPGA, and watching the LEDs update! + +m.my_memory.write(0, 1) diff --git a/examples/verilog/nexys_a7/io_core_uart/.Xil/top_level_propImpl.xdc b/examples/verilog/nexys_a7/io_core_uart/.Xil/top_level_propImpl.xdc new file mode 100644 index 0000000..e76c2e0 --- /dev/null +++ b/examples/verilog/nexys_a7/io_core_uart/.Xil/top_level_propImpl.xdc @@ -0,0 +1,93 @@ +set_property SRC_FILE_INFO {cfile:/home/fischerm/manta/examples/verilog/nexys_a7/io_core_uart/top_level.xdc rfile:../top_level.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r +set_property src_info {type:XDC file:1 line:85 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc +set_property src_info {type:XDC file:1 line:86 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu +set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property src_info {type:XDC file:1 line:89 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +set_property src_info {type:XDC file:1 line:219 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property src_info {type:XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out diff --git a/examples/verilog/nexys_a7/io_core_uart/.gitignore b/examples/verilog/nexys_a7/io_core_uart/.gitignore new file mode 100644 index 0000000..a670a87 --- /dev/null +++ b/examples/verilog/nexys_a7/io_core_uart/.gitignore @@ -0,0 +1 @@ +!top_level.sv \ No newline at end of file diff --git a/examples/verilog/nexys_a7/io_core_uart/blinky.py b/examples/verilog/nexys_a7/io_core_uart/blinky.py new file mode 100644 index 0000000..e4c4920 --- /dev/null +++ b/examples/verilog/nexys_a7/io_core_uart/blinky.py @@ -0,0 +1,25 @@ +from manta import Manta +from time import sleep +from random import randint + +m = Manta("manta.yaml") + +i = 0 +while True: + i = (i + 1) % 16 + m.my_io_core.set_probe("led", 2**i) + + m.my_io_core.set_probe("led16_r", randint(0, 1)) + m.my_io_core.set_probe("led16_g", randint(0, 1)) + m.my_io_core.set_probe("led16_b", randint(0, 1)) + + print(f'Switches: {m.my_io_core.get_probe("sw")}') + print(f"Buttons:") + print(f'btnu: {m.my_io_core.get_probe("btnu")}') + print(f'btnd: {m.my_io_core.get_probe("btnd")}') + print(f'btnr: {m.my_io_core.get_probe("btnr")}') + print(f'btnl: {m.my_io_core.get_probe("btnl")}') + print(f'btnc: {m.my_io_core.get_probe("btnc")}') + print("") + + sleep(0.1) diff --git a/examples/verilog/nexys_a7/io_core_uart/build.sh b/examples/verilog/nexys_a7/io_core_uart/build.sh new file mode 100755 index 0000000..829824b --- /dev/null +++ b/examples/verilog/nexys_a7/io_core_uart/build.sh @@ -0,0 +1,3 @@ +python3 -m manta gen manta.yaml manta.v +mkdir -p build/ +$VIVADO -mode batch -source build.tcl \ No newline at end of file diff --git a/examples/verilog/nexys_a7/io_core_uart/build.tcl b/examples/verilog/nexys_a7/io_core_uart/build.tcl new file mode 100644 index 0000000..0e7570e --- /dev/null +++ b/examples/verilog/nexys_a7/io_core_uart/build.tcl @@ -0,0 +1,36 @@ +#!/usr/bin/tclsh + +set partNum xc7a100tcsg324-1 +set outputDir build + +read_verilog -sv [ glob *.{sv,v,svh,vh} ] +read_xdc top_level.xdc + +set_part $partNum + +# synth +synth_design -top top_level -part $partNum -verbose +report_utilization -file $outputDir/post_synth_util.rpt +report_timing_summary -file $outputDir/post_synth_timing_summary.rpt +report_timing -file $outputDir/post_synth_timing.rpt + +# place +opt_design +place_design +phys_opt_design +report_utilization -file $outputDir/post_place_util.rpt + +report_clock_utilization -file $outputDir/clock_util.rpt +report_timing_summary -file $outputDir/post_place_timing_summary.rpt +report_timing -file $outputDir/post_place_timing.rpt + +# route design and generate bitstream +route_design -directive Explore +write_bitstream -force $outputDir/out.bit + +report_route_status -file $outputDir/post_route_status.rpt +report_timing_summary -file $outputDir/post_route_timing_summary.rpt +report_timing -file $outputDir/post_route_timing.rpt +report_power -file $outputDir/post_route_power.rpt +report_drc -file $outputDir/post_imp_drc.rpt +write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys_a7/io_core_uart/manta.yaml b/examples/verilog/nexys_a7/io_core_uart/manta.yaml new file mode 100644 index 0000000..b924fb3 --- /dev/null +++ b/examples/verilog/nexys_a7/io_core_uart/manta.yaml @@ -0,0 +1,26 @@ +--- +cores: + my_io_core: + type: io + + inputs: + btnu: 1 + btnd: 1 + btnl: 1 + btnr: 1 + btnc: 1 + sw: 16 + + outputs: + led: 16 + led16_b: 1 + led16_g: 1 + led16_r: 1 + led17_b: 1 + led17_g: 1 + led17_r: 1 + +uart: + port: "/dev/ttyUSB1" + baudrate: 115200 + clock_freq: 100000000 \ No newline at end of file diff --git a/examples/verilog/nexys_a7/io_core_uart/top_level.sv b/examples/verilog/nexys_a7/io_core_uart/top_level.sv new file mode 100644 index 0000000..a005530 --- /dev/null +++ b/examples/verilog/nexys_a7/io_core_uart/top_level.sv @@ -0,0 +1,49 @@ +`default_nettype none +`timescale 1ns / 1ps + +module top_level ( + input wire clk, + + input wire uart_txd_in, + output logic uart_rxd_out, + + input wire btnu, + input wire btnd, + input wire btnl, + input wire btnr, + input wire btnc, + + input wire [15:0] sw, + + output logic [15:0] led, + output logic led16_b, + output logic led16_g, + output logic led16_r, + output logic led17_b, + output logic led17_g, + output logic led17_r); + + manta manta_inst ( + .clk(clk), + .rst(0), + + .rx(uart_txd_in), + .tx(uart_rxd_out), + + .btnu(btnu), + .btnd(btnd), + .btnl(btnl), + .btnr(btnr), + .btnc(btnc), + .sw(sw), + .led(led), + .led16_b(led16_b), + .led16_g(led16_g), + .led16_r(led16_r), + .led17_b(led17_b), + .led17_g(led17_g), + .led17_r(led17_r)); + +endmodule + +`default_nettype wire \ No newline at end of file diff --git a/examples/verilog/nexys_a7/io_core_uart/top_level.xdc b/examples/verilog/nexys_a7/io_core_uart/top_level.xdc new file mode 100644 index 0000000..82c04c3 --- /dev/null +++ b/examples/verilog/nexys_a7/io_core_uart/top_level.xdc @@ -0,0 +1,254 @@ +## This file is a general .xdc for the Nexys4 DDR Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 + +## Clock signal - uncomment _both_ of these lines to create clk_100mhz +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; + +##Switches + +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b +set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc +set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu +set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +# +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +# +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + + diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/.Xil/top_level_propImpl.xdc b/examples/verilog/nexys_a7/logic_analyzer_uart/.Xil/top_level_propImpl.xdc new file mode 100644 index 0000000..9b1c029 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_uart/.Xil/top_level_propImpl.xdc @@ -0,0 +1,11 @@ +set_property SRC_FILE_INFO {cfile:/home/fischerm/manta/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc rfile:../top_level.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk +set_property src_info {type:XDC file:1 line:219 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property src_info {type:XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +set_property src_info {type:XDC file:1 line:226 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +set_property src_info {type:XDC file:1 line:227 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/.gitignore b/examples/verilog/nexys_a7/logic_analyzer_uart/.gitignore new file mode 100644 index 0000000..a670a87 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_uart/.gitignore @@ -0,0 +1 @@ +!top_level.sv \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/build.sh b/examples/verilog/nexys_a7/logic_analyzer_uart/build.sh new file mode 100755 index 0000000..829824b --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_uart/build.sh @@ -0,0 +1,3 @@ +python3 -m manta gen manta.yaml manta.v +mkdir -p build/ +$VIVADO -mode batch -source build.tcl \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/build.tcl b/examples/verilog/nexys_a7/logic_analyzer_uart/build.tcl new file mode 100644 index 0000000..0e7570e --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_uart/build.tcl @@ -0,0 +1,36 @@ +#!/usr/bin/tclsh + +set partNum xc7a100tcsg324-1 +set outputDir build + +read_verilog -sv [ glob *.{sv,v,svh,vh} ] +read_xdc top_level.xdc + +set_part $partNum + +# synth +synth_design -top top_level -part $partNum -verbose +report_utilization -file $outputDir/post_synth_util.rpt +report_timing_summary -file $outputDir/post_synth_timing_summary.rpt +report_timing -file $outputDir/post_synth_timing.rpt + +# place +opt_design +place_design +phys_opt_design +report_utilization -file $outputDir/post_place_util.rpt + +report_clock_utilization -file $outputDir/clock_util.rpt +report_timing_summary -file $outputDir/post_place_timing_summary.rpt +report_timing -file $outputDir/post_place_timing.rpt + +# route design and generate bitstream +route_design -directive Explore +write_bitstream -force $outputDir/out.bit + +report_route_status -file $outputDir/post_route_status.rpt +report_timing_summary -file $outputDir/post_route_timing_summary.rpt +report_timing -file $outputDir/post_route_timing.rpt +report_power -file $outputDir/post_route_power.rpt +report_drc -file $outputDir/post_imp_drc.rpt +write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/manta.yaml b/examples/verilog/nexys_a7/logic_analyzer_uart/manta.yaml new file mode 100644 index 0000000..6502705 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_uart/manta.yaml @@ -0,0 +1,19 @@ +--- +cores: + my_logic_analyzer: + type: logic_analyzer + sample_depth: 256 + + probes: + probe0: 1 + probe1: 4 + probe2: 8 + probe3: 16 + + triggers: + - probe2 EQ 3 + +uart: + port: "/dev/ttyUSB1" + baudrate: 115200 + clock_freq: 100000000 \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.sv b/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.sv new file mode 100644 index 0000000..b79f36b --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.sv @@ -0,0 +1,37 @@ +`default_nettype none +`timescale 1ns / 1ps + +module top_level ( + input wire clk, + + input wire uart_txd_in, + output logic uart_rxd_out + ); + + logic probe0; + logic [3:0] probe1; + logic [7:0] probe2; + logic [15:0] probe3; + + always @(posedge clk) begin + probe0 <= probe0 + 1; + probe1 <= probe1 + 1; + probe2 <= probe2 + 1; + probe3 <= probe3 + 1; + end + + manta manta_inst ( + .clk(clk), + .rst(0), + + .rx(uart_txd_in), + .tx(uart_rxd_out), + + .probe0(probe0), + .probe1(probe1), + .probe2(probe2), + .probe3(probe3)); + +endmodule + +`default_nettype wire \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc b/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc new file mode 100644 index 0000000..81c1998 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc @@ -0,0 +1,254 @@ +## This file is a general .xdc for the Nexys4 DDR Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 + +## Clock signal - uncomment _both_ of these lines to create clk_100mhz +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; + +##Switches + +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +# +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +# +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + + diff --git a/pyproject.toml b/pyproject.toml index b794d15..711a9b0 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,6 +1,6 @@ [project] name = "manta" -version = "0.1.0" +version = "1.0.0" authors = [ { name="Fischer Moseley", email="fischerm@mit.edu" }, ] diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 32237ab..177cae7 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -60,6 +60,19 @@ class MemoryCore(MantaCore): self.user_write_enable, ] + # Define memories + n_full = self._width // 16 + n_partial = self._width % 16 + + self._mems = [ + Memory(width=16, depth=self._depth, init=[0] * self._depth) + for _ in range(n_full) + ] + if n_partial > 0: + self._mems += [ + Memory(width=n_partial, depth=self._depth, init=[0] * self._depth) + ] + @property def top_level_ports(self): return self._top_level_ports @@ -199,19 +212,6 @@ class MemoryCore(MantaCore): def elaborate(self, platform): m = Module() - # Define memories - n_full = self._width // 16 - n_partial = self._width % 16 - - self._mems = [ - Memory(width=16, depth=self._depth, init=[0] * self._depth) - for _ in range(n_full) - ] - if n_partial > 0: - self._mems += [ - Memory(width=n_partial, depth=self._depth, init=[0] * self._depth) - ] - # Add memories as submodules for i, mem in enumerate(self._mems): m.submodules[f"mem_{i}"] = mem diff --git a/src/manta/utils.py b/src/manta/utils.py index e2fa22c..62913c5 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -115,6 +115,7 @@ def split_into_chunks(data, chunk_size): return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)] + def make_build_dir_if_it_does_not_exist_already(): """ Make build/ if it doesn't exist already. @@ -133,6 +134,7 @@ def simulate(top): def decorator(testbench): make_build_dir_if_it_does_not_exist_already() + def wrapper(*args, **kwargs): sim = Simulator(top) sim.add_clock(1e-6) # 1 MHz From 7957d41a9926165158a39dfb52929f94c68b627c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 6 Mar 2024 23:09:37 -0800 Subject: [PATCH 83/89] fix consistency in .gitignore --- .gitignore | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 6ef1d49..348d56d 100644 --- a/.gitignore +++ b/.gitignore @@ -16,7 +16,7 @@ build/ *.out *.csv -# Vivado files from the occasional debugging sesh +# Vivado files *.log *.jou *.rpt @@ -25,7 +25,7 @@ build/ *.out .Xil/* -# Yosys/IceStorm files from the same +# Yosys/IceStorm files *.asc *.bin *.json \ No newline at end of file From 04cfa4119064dd5b790747cbed0ee2dfeff56148 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 7 Mar 2024 09:18:30 -0800 Subject: [PATCH 84/89] add logic analyzer/io core ethernet example --- .../.Xil/top_level_propImpl.xdc | 71 ----- .../io_core_uart/.Xil/top_level_propImpl.xdc | 93 ------- .../logic_analyzer_io_core_ethernet/build.sh | 3 + .../logic_analyzer_io_core_ethernet/build.tcl | 36 +++ .../manta.yaml | 35 +++ .../logic_analyzer_io_core_ethernet/test.py | 6 + .../top_level.xdc | 260 ++++++++++++++++++ .../.Xil/top_level_propImpl.xdc | 11 - 8 files changed, 340 insertions(+), 175 deletions(-) delete mode 100644 examples/verilog/nexys_a7/host_to_fpga_mem_uart/.Xil/top_level_propImpl.xdc delete mode 100644 examples/verilog/nexys_a7/io_core_uart/.Xil/top_level_propImpl.xdc create mode 100755 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.sh create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.tcl create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/manta.yaml create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/test.py create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.xdc delete mode 100644 examples/verilog/nexys_a7/logic_analyzer_uart/.Xil/top_level_propImpl.xdc diff --git a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/.Xil/top_level_propImpl.xdc b/examples/verilog/nexys_a7/host_to_fpga_mem_uart/.Xil/top_level_propImpl.xdc deleted file mode 100644 index a975d04..0000000 --- a/examples/verilog/nexys_a7/host_to_fpga_mem_uart/.Xil/top_level_propImpl.xdc +++ /dev/null @@ -1,71 +0,0 @@ -set_property SRC_FILE_INFO {cfile:/home/fischerm/manta/examples/verilog/nexys_a7/host_to_fpga_mem_uart/top_level.xdc rfile:../top_level.xdc id:1} [current_design] -set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] -set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] -set_property src_info {type:XDC file:1 line:219 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property src_info {type:XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out diff --git a/examples/verilog/nexys_a7/io_core_uart/.Xil/top_level_propImpl.xdc b/examples/verilog/nexys_a7/io_core_uart/.Xil/top_level_propImpl.xdc deleted file mode 100644 index e76c2e0..0000000 --- a/examples/verilog/nexys_a7/io_core_uart/.Xil/top_level_propImpl.xdc +++ /dev/null @@ -1,93 +0,0 @@ -set_property SRC_FILE_INFO {cfile:/home/fischerm/manta/examples/verilog/nexys_a7/io_core_uart/top_level.xdc rfile:../top_level.xdc id:1} [current_design] -set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] -set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] -set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r -set_property src_info {type:XDC file:1 line:85 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property src_info {type:XDC file:1 line:86 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property src_info {type:XDC file:1 line:89 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd -set_property src_info {type:XDC file:1 line:219 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property src_info {type:XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.sh b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.sh new file mode 100755 index 0000000..829824b --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.sh @@ -0,0 +1,3 @@ +python3 -m manta gen manta.yaml manta.v +mkdir -p build/ +$VIVADO -mode batch -source build.tcl \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.tcl b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.tcl new file mode 100644 index 0000000..0e7570e --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/build.tcl @@ -0,0 +1,36 @@ +#!/usr/bin/tclsh + +set partNum xc7a100tcsg324-1 +set outputDir build + +read_verilog -sv [ glob *.{sv,v,svh,vh} ] +read_xdc top_level.xdc + +set_part $partNum + +# synth +synth_design -top top_level -part $partNum -verbose +report_utilization -file $outputDir/post_synth_util.rpt +report_timing_summary -file $outputDir/post_synth_timing_summary.rpt +report_timing -file $outputDir/post_synth_timing.rpt + +# place +opt_design +place_design +phys_opt_design +report_utilization -file $outputDir/post_place_util.rpt + +report_clock_utilization -file $outputDir/clock_util.rpt +report_timing_summary -file $outputDir/post_place_timing_summary.rpt +report_timing -file $outputDir/post_place_timing.rpt + +# route design and generate bitstream +route_design -directive Explore +write_bitstream -force $outputDir/out.bit + +report_route_status -file $outputDir/post_route_status.rpt +report_timing_summary -file $outputDir/post_route_timing_summary.rpt +report_timing -file $outputDir/post_route_timing.rpt +report_power -file $outputDir/post_route_power.rpt +report_drc -file $outputDir/post_imp_drc.rpt +write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/manta.yaml b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/manta.yaml new file mode 100644 index 0000000..8dd1036 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/manta.yaml @@ -0,0 +1,35 @@ +--- +cores: + my_logic_analyzer: + type: logic_analyzer + sample_depth: 8192 + + probes: + probe0: 1 + probe1: 4 + probe2: 8 + probe3: 16 + + triggers: + - probe2 EQ 3 + + my_io_core: + type: io + inputs: + sw: 16 + outputs: + led: 16 + + +ethernet: + phy: LiteEthPHYRMII + device: xc7a + vendor: xilinx + toolchain: vivado + + refclk_freq: 50e6 + clk_freq: 50e6 + + fpga_ip_addr: "192.168.0.110" + host_ip_addr: "192.168.0.100" + udp_port: 2000 diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/test.py b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/test.py new file mode 100644 index 0000000..06ab14a --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/test.py @@ -0,0 +1,6 @@ +from manta import Manta + +m = Manta("manta.yaml") + +print(m.my_io_core.get_probe("sw")) +m.my_io_core.set_probe("led", 4) diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.xdc b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.xdc new file mode 100644 index 0000000..e2ad6f3 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.xdc @@ -0,0 +1,260 @@ +## R1.0 2019-08-27 +## Updated by jodalyst in 2020-2022 +## all inputs/outputs changed to lowercase; arrays start with zero. +## system clock renamed to clk_100mhz +## ja, jb, jc, jd renamed to 0-7 +## xa port renamed 0-3 +## seven segments renamed to a,b,c,d,e,f,dp + +## This file is a general .xdc for the Nexys4 DDR Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; + + +##Switches + +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc +set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu +set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +# +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +# +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + diff --git a/examples/verilog/nexys_a7/logic_analyzer_uart/.Xil/top_level_propImpl.xdc b/examples/verilog/nexys_a7/logic_analyzer_uart/.Xil/top_level_propImpl.xdc deleted file mode 100644 index 9b1c029..0000000 --- a/examples/verilog/nexys_a7/logic_analyzer_uart/.Xil/top_level_propImpl.xdc +++ /dev/null @@ -1,11 +0,0 @@ -set_property SRC_FILE_INFO {cfile:/home/fischerm/manta/examples/verilog/nexys_a7/logic_analyzer_uart/top_level.xdc rfile:../top_level.xdc id:1} [current_design] -set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk -set_property src_info {type:XDC file:1 line:219 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property src_info {type:XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -set_property src_info {type:XDC file:1 line:226 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -set_property src_info {type:XDC file:1 line:227 export:INPUT save:INPUT read:READ} [current_design] -set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data From 05f9da383cf8412a6d15b29f474efe21727c16a1 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 7 Mar 2024 09:19:11 -0800 Subject: [PATCH 85/89] banish all .Xil/ folders --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 348d56d..44697e8 100644 --- a/.gitignore +++ b/.gitignore @@ -23,7 +23,7 @@ build/ *.bin *.bit *.out -.Xil/* +.Xil/ # Yosys/IceStorm files *.asc From 4ae061ffdc322f0ba4a6ef44af1dac0eab2ad731 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 7 Mar 2024 09:21:40 -0800 Subject: [PATCH 86/89] add missing .gitignore --- .../.gitignore | 2 + .../divider.sv | 193 ++++++++++++++++++ .../top_level.sv | 54 +++++ 3 files changed, 249 insertions(+) create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore new file mode 100644 index 0000000..f6ca93a --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore @@ -0,0 +1,2 @@ +!top_level.sv +!divider.sv \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv new file mode 100644 index 0000000..623cce7 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv @@ -0,0 +1,193 @@ +`default_nettype wire + +// file: divider.sv +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// popopopopopopopopopopop +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// __ethclk__50.00000______0.000______50.0______151.636_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +module divider + + (// Clock in ports + // Clock out ports + output ethclk, + input clk + ); + // Input buffering + //------------------------------------ +wire clk_divider; +wire clk_in2_divider; + IBUF clkin1_ibufg + (.O (clk_divider), + .I (clk)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire ethclk_divider; + wire clk_out2_divider; + wire clk_out3_divider; + wire clk_out4_divider; + wire clk_out5_divider; + wire clk_out6_divider; + wire clk_out7_divider; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_divider; + wire clkfbout_buf_divider; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (10.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (20.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (10.000)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_divider), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (ethclk_divider), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clkout1_unused), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_divider), + .CLKIN1 (clk_divider), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (1'b0)); + +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_divider), + .I (clkfbout_divider)); + + BUFG clkout1_buf + (.O (ethclk), + .I (ethclk_divider)); + +endmodule + +`default_nettype none \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv new file mode 100644 index 0000000..c38deb8 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv @@ -0,0 +1,54 @@ +module top_level ( + input wire clk_100mhz, + output logic eth_refclk, + input wire btnc, + + output logic [15:0] led, + input wire [15:0] sw, + + input wire eth_crsdv, + output logic eth_mdc, + output logic eth_mdio, + output logic eth_rstn, + input wire [1:0] eth_rxd, + output logic [1:0] eth_txd, + output logic eth_txen +); + +logic ethclk; +assign eth_refclk = ethclk; +divider div (.clk(clk_100mhz), .ethclk(ethclk)); + + logic probe0; + logic [3:0] probe1; + logic [7:0] probe2; + logic [15:0] probe3; + + always @(posedge ethclk) begin + probe0 <= probe0 + 1; + probe1 <= probe1 + 1; + probe2 <= probe2 + 1; + probe3 <= probe3 + 1; + end + +manta manta_inst( + .clk(ethclk), + .rst(btnc), + .rmii_clocks_ref_clk(ethclk), + .rmii_crs_dv(eth_crsdv), + .rmii_mdc(eth_mdc), + .rmii_mdio(eth_mdio), + .rmii_rst_n(eth_rstn), + .rmii_rx_data(eth_rxd), + .rmii_tx_data(eth_txd), + .rmii_tx_en(eth_txen), + + .probe0(probe0), + .probe1(probe1), + .probe2(probe2), + .probe3(probe3), + + .led(led), + .sw(sw)); + +endmodule \ No newline at end of file From c8665e87033484d961a31047dc8eabaf1a417e4c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 7 Mar 2024 09:33:50 -0800 Subject: [PATCH 87/89] update environment on CI runner --- .github/workflows/run_tests.yml | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index 3396525..bb2640f 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -27,13 +27,6 @@ jobs: - name: Run tests run: | - # export tool paths - export VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado - export YOSYS=/tools/oss-cad-suite/bin/yosys - export NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr-ice40 - export ICEPACK=/tools/oss-cad-suite/bin/icepack - export ICEPROG=/tools/oss-cad-suite/bin/iceprog - + source ./environment.sh source venv/bin/activate - make test \ No newline at end of file From 6251c162cca37bfad41b4479501aa2c59971c278 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 7 Mar 2024 09:35:47 -0800 Subject: [PATCH 88/89] update to node 20-based checkout in CI --- .github/workflows/run_tests.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/run_tests.yml b/.github/workflows/run_tests.yml index bb2640f..8d718c1 100644 --- a/.github/workflows/run_tests.yml +++ b/.github/workflows/run_tests.yml @@ -4,7 +4,7 @@ jobs: all: runs-on: self-hosted steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 - name: Install Manta from Source run: | From e0aeb38cdbd9c0ec4c654f364349b8ba7ad54f1c Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 7 Mar 2024 12:25:30 -0800 Subject: [PATCH 89/89] update docs --- Makefile | 2 +- doc/architecture.md | 22 +- doc/assets/bus_architecture.drawio.svg | 261 +++++++----------- .../logic_analyzer_architecture.drawio.svg | 182 +++++------- doc/assets/memory_architecture.drawio.svg | 62 ++--- doc/getting_started.md | 6 +- doc/io_core.md | 32 ++- doc/logic_analyzer_core.md | 14 +- doc/memory_core.md | 55 ++-- doc/repository_structure.md | 14 +- 10 files changed, 281 insertions(+), 369 deletions(-) diff --git a/Makefile b/Makefile index 229247e..d8b63bc 100644 --- a/Makefile +++ b/Makefile @@ -8,5 +8,5 @@ format: clean: git clean -Xdf -serve_docs: +preview_site: mkdocs serve diff --git a/doc/architecture.md b/doc/architecture.md index 53ed0db..6bab858 100644 --- a/doc/architecture.md +++ b/doc/architecture.md @@ -86,13 +86,19 @@ Each Memory core is actually a set of 16-bit wide BRAMs with their ports concate Since each $n$-bit wide block memory is actually $ceil(n/16)$ BRAMs under the hood, addressing the BRAMs correctly from Manta's internal bus is important. BRAMs are organized such that each 16-bit slice of a $N$-bit word in the Block Memory core are placed next to each other in bus address space. For instance, a 34-bit wide block memory would exist on Manta's internal bus as: -| Bus Address Space | BRAM Address Space | -| ----------- | -------------------- | -| BASE_ADDR + 0 | address 0, bits 0-15 | -| BASE_ADDR + 1 | address 0, bits 16-31| -| BASE_ADDR + 2 | address 0, bits 32-33| -| BASE_ADDR + 3 | address 1, bits 0-15 | -| BASE_ADDR + 4 | address 1, bits 16-31| -| BASE_ADDR + 5 | address 1, bits 32-33| +| Bus Address Space | BRAM Address Space | +| ----------- | -------------------- | +| BASE_ADDR + 0 | address 0, bits 0-15 | +| BASE_ADDR + 1 | address 1, bits 0-15 | +| BASE_ADDR + n | address n, bits 0-15 | +| ... | ... | +| BASE_ADDR + 0 + DEPTH | address 0, bits 16-31| +| BASE_ADDR + 1 + DEPTH | address 1, bits 16-31| +| BASE_ADDR + n + DEPTH | address n, bits 16-31| +| ... | ... | +| BASE_ADDR + 0 + (2 * DEPTH) | address 0, bits 32-33| +| BASE_ADDR + 1 + (2 * DEPTH) | address 1, bits 32-33| +| BASE_ADDR + n + (2 * DEPTH) | address n, bits 32-33| +| ... | ... | ...and so on. diff --git a/doc/assets/bus_architecture.drawio.svg b/doc/assets/bus_architecture.drawio.svg index a8b8077..739e2ad 100644 --- a/doc/assets/bus_architecture.drawio.svg +++ b/doc/assets/bus_architecture.drawio.svg @@ -1,74 +1,15 @@ - - - - + + - - - - - + + + + + -
    +
    bus @@ -76,17 +17,17 @@
    - + bus - - + + -
    +
    bus @@ -94,16 +35,16 @@
    - + bus - + -
    +

    @@ -113,16 +54,16 @@

    - + manta - + -
    +

    @@ -132,17 +73,17 @@

    - + FPGA Fabric - - + + -
    +
    bus @@ -150,17 +91,17 @@
    - + bus - - + + -
    +
    bus @@ -168,17 +109,17 @@
    - + bus - - + + -
    +
    rx @@ -186,17 +127,17 @@
    - + rx - - + + -
    +
    input_0 @@ -204,17 +145,17 @@
    - + input_0 - - + + -
    +
    output_1 @@ -222,16 +163,16 @@
    - + output_1 - + -
    +
    rx bridge @@ -239,16 +180,16 @@
    - + rx bridge - + -
    +
    logic @@ -258,16 +199,16 @@
    - + logic... - + -
    +
    io core @@ -275,16 +216,16 @@
    - + io core - + -
    +
    block memory core @@ -292,16 +233,16 @@
    - + block memo... - + -
    +
    tx bridge @@ -309,16 +250,16 @@
    - + tx bridge - + -
    +
    user logic @@ -326,89 +267,89 @@
    - + user logic - - + + -
    +
    - addr + user_addr
    - - addr + + user_addr - - + + -
    +
    - din + user_data_in
    - - din + + user_data_in - - + + -
    +
    - dout + user_data_out
    - - dout + + user_data_out - - + + -
    +
    - we + user_write_enable
    - - we + + user_write_enable - - + + -
    +
    tx @@ -416,17 +357,17 @@
    - + tx - - + + -
    +
    probe_2 @@ -434,17 +375,17 @@
    - + probe_2 - - + + -
    +
    probe_3 @@ -452,17 +393,17 @@
    - + probe_3 - - + + -
    +
    probe_1 @@ -470,17 +411,17 @@
    - + probe_1 - - + + -
    +
    output_0 @@ -488,7 +429,7 @@
    - + output_0 diff --git a/doc/assets/logic_analyzer_architecture.drawio.svg b/doc/assets/logic_analyzer_architecture.drawio.svg index 4f3dc26..8e6f240 100644 --- a/doc/assets/logic_analyzer_architecture.drawio.svg +++ b/doc/assets/logic_analyzer_architecture.drawio.svg @@ -1,4 +1,4 @@ - + - - - + + + -
    -
    -
    - block +
    +
    +
    + Sample Memory
    - memory + (Memory Core)
    - - block... + + Sample Memory... @@ -88,7 +86,7 @@ -
    +
    bus @@ -96,7 +94,7 @@
    - + bus @@ -107,7 +105,7 @@ -
    +
    bus @@ -115,7 +113,7 @@
    - + bus @@ -130,6 +128,8 @@ fsm
    registers +
    + (IO Core)
    @@ -156,12 +156,12 @@ - - + + -
    +
    bus @@ -169,7 +169,7 @@
    - + bus @@ -182,6 +182,8 @@
    trigger registers +
    + (IO Core)
    @@ -208,12 +210,12 @@ - - + + -
    +
    arg @@ -261,12 +263,12 @@ - - + + -
    +
    arg @@ -302,7 +304,7 @@ -
    +
    trigger_mode @@ -320,7 +322,7 @@ -
    +
    request_start @@ -338,7 +340,7 @@ -
    +
    request_stop @@ -356,7 +358,7 @@ -
    +
    read_pointer @@ -374,7 +376,7 @@ -
    +
    write_pointer @@ -392,7 +394,7 @@ -
    +
    state @@ -410,7 +412,7 @@ -
    +
    trigger_location @@ -440,12 +442,12 @@ - - + + -
    +
    bus @@ -453,34 +455,17 @@
    - + bus - + + -
    -
    -
    - port A -
    -
    -
    -     - - port A - -     -     - - - - - -
    +
    data @@ -488,28 +473,11 @@
    - + data - - - - -
    -
    -
    - port B -
    -
    -
    -     - - port B - -     -     @@ -536,7 +504,7 @@ -
    +
    trig @@ -544,7 +512,7 @@
    - + trig @@ -567,27 +535,27 @@ - + -
    +
    - + - + -
    +
    probe_2 @@ -604,23 +572,23 @@ -
    +
    - + - + -
    +
    probe_1 @@ -633,7 +601,7 @@ - + @@ -658,7 +626,7 @@ -
    +
    probe_0 @@ -688,12 +656,12 @@ - - + + -
    +
    arg @@ -724,12 +692,12 @@ - - + + -
    +
    we @@ -737,7 +705,7 @@
    - + we @@ -745,7 +713,7 @@ -
    +
    we @@ -753,17 +721,17 @@
    - + we - - + + -
    +
    addr @@ -771,7 +739,7 @@
    - + addr @@ -779,7 +747,7 @@ -
    +
    addr @@ -787,16 +755,16 @@
    - + addr - + - + - + diff --git a/doc/assets/memory_architecture.drawio.svg b/doc/assets/memory_architecture.drawio.svg index c929ee4..84c6998 100644 --- a/doc/assets/memory_architecture.drawio.svg +++ b/doc/assets/memory_architecture.drawio.svg @@ -1,4 +1,4 @@ - +
    - block RAM + RAM
    - block RAM + RAM     @@ -101,7 +101,7 @@ -
    +
    addr @@ -119,7 +119,7 @@ -
    +
    din @@ -127,7 +127,7 @@
    - + din @@ -137,7 +137,7 @@ -
    +
    dout @@ -155,7 +155,7 @@ -
    +
    we @@ -209,13 +209,13 @@
    - block RAM + RAM
    - block RAM + RAM @@ -261,7 +261,7 @@ -
    +
    user_addr @@ -274,8 +274,8 @@ - - + + @@ -287,7 +287,7 @@
    - + user_din @@ -297,7 +297,7 @@ -
    +
    user_dout @@ -310,8 +310,8 @@ - - + + @@ -351,7 +351,7 @@ -
    +
    din @@ -359,7 +359,7 @@
    - + din @@ -407,13 +407,13 @@
    - block RAM + RAM
    - block RAM + RAM @@ -474,7 +474,7 @@ -
    +
    din @@ -482,7 +482,7 @@
    - + din @@ -601,12 +601,12 @@ - - + + -
    +
    bus @@ -614,17 +614,17 @@
    - + bus - - + + -
    +
    bus @@ -632,7 +632,7 @@
    - + bus diff --git a/doc/getting_started.md b/doc/getting_started.md index e6b3141..7494a49 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -5,7 +5,7 @@ To use Manta, you'll need a host machine with a FPGA board connected over UART, - _Specify a set of debug cores you wish to include in your design._ This is done by writing a configuration file, typically called `manta.yaml`. Specifying files in JSON is also supported, as long as the hierarchy in the file is equivalent. Just make sure that your YAML files end in `.yaml` or `.yml`, and that JSON files end in `.json`. - _Invoke Manta to generate Verilog from the configuration provided._ This is done by running `manta gen [config_file] [verilog_file]` at the command line, which generates a Verilog file (typically named `manta.v`) from the provided configuration file. This Verilog file contains a definition for a Verilog module named `manta`, and all its constituent modules. -- _Instantiate `manta` in your design, and connecting it to the logic you'd like to debug._ An example instantiation is provided at the top of `manta.v`, which you can copy-paste into your main source code. You'll connect its ports to the logic you're trying to debug, as well as to whatever interface you're using to communicate with the host. This will be a serial transciever on your development board if you're using UART, or it's RMII PHY if you're using Ethernet. +- _Instantiate `manta` in your design, and connecting it to the logic you'd like to debug._ Manta will provide an example instantiation if you run `manta inst [config_file]`, which you can copy-paste into your source code. You'll connect its ports to the logic you're trying to debug, as well as to whatever interface you're using to communicate with the host. This will be a serial transciever on your development board if you're using UART, or it's RMII PHY if you're using Ethernet. - _Build and upload the design to your FPGA using your preferred toolchain._ - _Use the debug core(s) through the Python API or the command line._ The functions availble to each core are described in their documentation. - _Repeat!_ As you debug, you'll probably want to change exactly how Manta is configured. This means tweaking the configuration file, regenerating the Verilog module, and so on. @@ -58,12 +58,12 @@ This Manta instance has an IO Core and a Logic Analyzer, each containing a numbe ## Example Instantiation -Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design. This is done by running `manta inst` with the path to the configuration file describing the Manta core you'd like to instantiate. For example, the following snippet is generated for the configuration above: +Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design by running `manta inst [config_file]`. For example, the following snippet is generated for the configuration above: ```verilog manta manta_inst ( .clk(clk), - .rst(rst) + .rst(rst), .rx(rx), .tx(tx), .probe_0_in(probe_0_in), diff --git a/doc/io_core.md b/doc/io_core.md index da61255..0e97bfd 100644 --- a/doc/io_core.md +++ b/doc/io_core.md @@ -43,22 +43,26 @@ Inside this configuration, the following parameters may be configured: ## Python API -The IO core functionality is stored in the `Manta.IOCore`, `Manta.InputProbe`, and `Manta.OutputProbe` classes in [src/manta/io_core/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/io_core/__init__.py), and it may be controlled with the two functions: - -`Manta.IOCoreProbe.set(data)` - -- [`int`, `bool`] _data_: The value to write to an output probe. May be signed or unsigned, but will raise an exception if the value is too large for the width of the port. -- _returns_: None - -This method is blocking. When called it will dispatch a request to the FPGA, and wait until a response has been received. +The IO core functionality is stored in the `Manta.IOCore` class in [src/manta/io_core/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/io_core.py), and it may be controlled with the two functions: --- -`Manta.IOCoreProbe.get()` +`Manta.IOCore.set_probe(name, data)` +- [`string`] _name_: The probe to write to. Must not be an output port, and must match the name provided in the config file. +- [`int`, `bool`] _data_: The value to write to an output probe. May be signed or unsigned, but will raise an exception if the value is too large for the width of the port. +- _returns_: None + +This method is blocking. When called it will dispatch a request to the FPGA, and halt execution until the request has been sent. + +--- + +`Manta.IOCore.get_probe(name)` + +- [`string`] _name_: The probe to read from. May be either an input or an output port, and must match the name provided in the config file. - _returns_: The value of an input or output probe. In the case of an output probe, the value returned will be the last value written to the probe. -This method is blocking. When called it will dispatch a request to the FPGA, and wait until a response has been received. +This method is blocking. When called it will dispatch a request to the FPGA, and halt execution until the request has been sent and a response has been received. --- @@ -70,11 +74,11 @@ A small example is shown below, using the [example configuration](#configuration ```python >>> import Manta >>> m = Manta ->>> m.my_io_core.fozzy.set(True) ->>> m.my_io_core.fozzy.get() +>>> m.my_io_core.set_probe("fozzy", True) +>>> m.my_io_core.get_probe("fozzy") True ->>> m.my_io_core.gonzo.set(4) ->>> m.my_io_core.scooter.get() +>>> m.my_io_core.set_probe("gonzo", 4) +>>> m.my_io_core.get_probe("scooter") 5 ``` diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index 450f20d..69aed07 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -67,17 +67,9 @@ Each individual trigger is specified with the following structure: Lastly, if you're not able to express your desired trigger condition in terms of the operators above, fear not! You can also specify an `external_trigger: true` entry in the config file, which exposes an input on Manta's top level for your own trigger. ### Trigger Position (optional) -Sometimes, you care more about what happens before a trigger is met than afterwards, or vice versa. To accommodate this, the logic analyzer has an optional _Trigger Position_ parameter, which sets when probe data is captured relative to the trigger condition being met. This is specified with the `trigger_position` entry in the configuration file, which sets how many samples to save prior to the trigger condition occurring. This is best explained with a picture: +Sometimes, you care more about what happens before a trigger is met than afterwards, or vice versa. To accommodate this, the logic analyzer has an optional _Trigger Position_ parameter, which sets when probe data is captured relative to the trigger condition being met. This is specified with the `trigger_position` entry in the configuration file, which sets how many samples to save prior to the trigger condition occurring. This is similar to a "holdoff" option on a traditional oscilloscope or logic analyzer. -![](assets/trigger_positions.png){style="width:90%"} - -The windows at the bottom of the diagram show what portions of the timeseries will be captured for different trigger positions. For instance: - -- A trigger position of half the sample depth centers the capture window around when the trigger condition is met. -- A trigger position of zero places the trigger at the zeroth clock cycle of the capture. -- A trigger position equal to the sample depth causes the trigger to occur on the last sample in the capture. - -If `trigger_position` is not specified, Manta will default to centering the capture window around the trigger condition. +If `trigger_position` is not specified, Manta will default to centering the capture window around the trigger condition. This results in just as many samples before the trigger as after. ### Capture Modes (optional) The logic analyzer has a few different ways of capturing data, which are represented by the _capture modes_ below: @@ -125,5 +117,5 @@ This is useful for two situations in particular: - _Sparse Sampling_ Sometimes designs will have a small number of inputs, but a huge amount of internal state. In situations like these, it may be more efficient to sample the inputs and simulate the logic, instead of directly sampling the state. For instance, debugging a misbehaving branch predictor in a CPU can be done by recording activity on the address and data busses and playing them back in simulation - which would use less FPGA resources than sampling the entire pattern history table. ## Python API -The Logic Analyzer core functionality is stored in the `Manta.LogicAnalyzerCore` class in [src/manta/la_core/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/la_core/__init__.py). This class contains methods for capturing data, and exporting `.vcd` and `.v` files. +The Logic Analyzer core functionality is stored in the `Manta.LogicAnalyzerCore` class in [src/manta/la_core/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/la_core/__init__.py). This class contains methods for capturing data, exporting it as `.vcd`, `.v` or `.csv` files, or as a Python list. diff --git a/doc/memory_core.md b/doc/memory_core.md index 26109f8..96be6ec 100644 --- a/doc/memory_core.md +++ b/doc/memory_core.md @@ -1,18 +1,19 @@ ## Overview -Block Memory (also called Block RAM, or BRAM) is the de facto means of storing data on FPGAs when the space needed exceeds a few registers. As a result, Manta provides a Block Memory core, which instantiates a dual-port BRAM on the FPGA. One port is provided to the host, and the other is connected to your logic with the standard BRAM interface (`addr`, `din`, `dout`, `wea`). This allows the host to provide reasonably large amounts of data to user logic - or the other way around, or a mix of both! +Memory is the de facto means of storing data on FPGAs when the space needed exceeds a few registers. As a result, Manta provides a Memory core, which instantiates a dual-port RAM on the FPGA. One port is provided to the host, and the other is connected to your logic with the standard RAM interface (`addr`, `data_in`, `data_out`, `write_enable`). This allows the host to provide reasonably large amounts of data to user logic - or the other way around, or a mix of both! This is a very, very simple task - and while configuration is straightforward, there are a few caveats. More on both topics below: ## Configuration -Just like the rest of the cores, the Block Memory core is configured via an entry in a project's configuration file. This is easiest to show by example: +Just like the rest of the cores, the Memory core is configured via an entry in a project's configuration file. This is easiest to show by example: ```yaml --- cores: - my_block_memory: - type: block_memory + my_memory: + type: memory + mode: bidirectional width: 12 depth: 16384 @@ -20,34 +21,38 @@ cores: There's a few parameters that get configured here, including: -- `name`: The name of the Block Memory core. This name is used to reference the core when working with the API, and can be whatever you'd like. -- `type`: This denotes that this is a Block Memory core. All cores contain a `type` field, which must be set to `block_memory` to be recognized as an Block Memory core. +- `name`: The name of the Memory core. This name is used to reference the core when working with the API, and can be whatever you'd like. +- `type`: This denotes that this is a Memory core. All cores contain a `type` field, which must be set to `memory` to be recognized as an Memory core. +- `mode`: The mode for the Memory core to operate in. This must be one of `bidirectional`, `host_to_fpga`, or `fpga_to_host`. Bidirectional memories can be both read or written to by the host and FPGA, but they require the use of a True Dual Port RAM, which is not available on all platforms (most notably, the ice40). Host-to-fpga and fpga-to-host RAMs only require a Simple Dual Port RAM, which is available on nearly all platforms. +- `width`: The width of the Memory core, in bits. +- `depth`: The depth of the Memory core, in entries. -### Dimensions -The dimensions of the block memory are specified in the config file with the `width` and `depth` entries. +Manta won't impose any limit on the width or depth of the memory you instantiate, but since Manta instantiates BRAM primitives on the FPGA, you will be limited by what your FPGA can support. It helps to know your particular FPGA's architecture here. -Manta won't impose any limit on the width or depth of the block memory you instantiate, but since Manta instantiates BRAM primitives on the FPGA, you will be limited by what your FPGA can support. It helps to know your particular FPGA's architecture here. +!!! warning "Bidirectional memories are currently broken on Xilinx platforms." + Due to a bug in Amaranth, trying to use a bidirectional memory on a Xilinx platform will cause Vivado to throw an `Unable to infer RAMs due to unsupported pattern.` error. This is a known issue, and has been reported [here](https://github.com/amaranth-lang/amaranth/issues/1011). In the meantime, if you have a Xilinx device, consider if your data flow is unidirectional, and you could use the `host_to_fpga` or `fpga_to_host` modes. Other platforms with dual-port RAM capability (such as the Lattice ECP5) appear to not be affected by this issue. -If your BRAM is more than 16 bits wide, check out the section on [Synchronicity](#synchronicity) and make sure your project will tolerate how Manta writes to the block memory. +### On-Chip Implementation +For most use cases, Manta will choose to implement the memory in Block RAM, if it is available on the device. However, the Verilog produced by Manta may be inferred to a number of memory types, including FF RAM or LUT (Distributed) RAM. For more information on how this is chosen, please refer to the [Yosys documentation](https://yosyshq.readthedocs.io/projects/yosys/en/latest/CHAPTER_Memorymap.html). ### Python API -The Block Memory core functionality is stored in the `Manta.IOCore` and `Manta.IOCoreProbe` classes in [src/manta/io_core/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/io_core/__init__.py), and it may be controlled with the two functions: +The Memory core functionality is stored in the `Manta.MemoryCore` classes in [src/manta/memory_core.py](https://github.com/fischermoseley/manta/blob/main/src/manta/memory_core.py), and it may be controlled with the two functions: -Just like with the other cores, interfacing with the BRAM with the Python API is simple: +Just like with the other cores, interfacing with the Memory with the Python API is simple: ```python from manta import Manta m = manta('manta.yaml') -m.my_block_memory.write(addr=38, data=600) -m.my_block_memory.write(addr=0x1234, data = 0b100011101011) -m.my_block_memory.write(0x0612, 0x2001) +m.my_memory.write(addr=38, data=600) +m.my_memory.write(addr=0x1234, data = 0b100011101011) +m.my_memory.write(0x0612, 0x2001) -foo = m.my_block_memory.write(addr=38) -foo = m.my_block_memory.write(addr=1234) -foo = m.my_block_memory.write(0x0612) +foo = m.my_memory.write(addr=38) +foo = m.my_memory.write(addr=1234) +foo = m.my_memory.write(0x0612) ``` Reading/writing in batches is also supported. This is recommended where possible, as reads are massively sped up by performing them in bulk: @@ -55,19 +60,15 @@ Reading/writing in batches is also supported. This is recommended where possible ```python addrs = list(range(0, 1234)) datas = list(range(1234, 2468)) -m.my_block_memory.write(addrs, datas) +m.my_memory.write(addrs, datas) -foo = m.my_block_memory.read(addrs) +foo = m.my_memory.read(addrs) ``` -### Examples - -A Block Memory core is used in the [video_sprite](https://github.com/fischermoseley/manta/blob/main/examples/nexys_a7/video_sprite) example. This uses the core to store a 128x128 image sprite in 12-bit color, and outputs it to a VGA display at 1024x768. The sprite contents can be filled with an arbitrary image using the [send_image.py](https://github.com/fischermoseley/manta/blob/main/examples/nexys_a7/video_sprite/send_image.py) python script. - ### Synchronicity -Since Manta's [data bus](architecture.md#data-bus) is only 16-bits wide, it's only possible to manipulate the BRAM core in 16-bit increments. This means that if you have a BRAM that's ≤16 bits wide, you'll only need to issue a single bus transaction to read/write one entry in the BRAM. However, if you have a BRAM that's ≥16 bits wide, you'll need to issue a bus transaction to update each 16-bit slice of it. For instance, updating a single entry in a 33-bit wide BRAM would require sending 3 messages to the FPGA: one for bits 1-16, another for bits 17-32, and one for bit 33. If your application expects each BRAM entry to update instantaneously, this could be problematic. +Since Manta's [data bus](architecture.md#data-bus) is only 16-bits wide, it's only possible to manipulate the Memory core in 16-bit increments. This means that if you have a RAM that's ≤16 bits wide, you'll only need to issue a single bus transaction to read/write one entry in the RAM. However, if you have a RAM that's ≥16 bits wide, you'll need to issue a bus transaction to update each 16-bit slice of it. For instance, updating a single entry in a 33-bit wide RAM would require sending 3 messages to the FPGA: one for bits 1-16, another for bits 17-32, and one for bit 33. If your application expects each RAM entry to update instantaneously, this could be problematic. -There's a few different ways to solve this - you could use an IO core to signal when a BRAM's contents or valid - or you could ping-pong between two BRAMs while one is being modified. The choice is yours, and Manta makes no attempt to prescribe any particular approach. +There's a few different ways to solve this - you could use an IO core to signal when a RAM's contents or valid - or you could ping-pong between two RAMs while one is being modified. The choice is yours, and Manta makes no attempt to prescribe any particular approach. -Lastly, the interface you use (and to a lesser extent, your operating system) will determine the space between bus transactions. For instance, 100Mbit Ethernet is a thousand times faster than 115200bps UART, so the time where the BRAM is invalid is a thousand times smaller. +Lastly, the interface you use (and to a lesser extent, your operating system) will determine the space between bus transactions. For instance, 100Mbit Ethernet is a thousand times faster than 115200bps UART, so the time where the RAM is invalid is a thousand times smaller. diff --git a/doc/repository_structure.md b/doc/repository_structure.md index 9652d74..6fc6d3f 100644 --- a/doc/repository_structure.md +++ b/doc/repository_structure.md @@ -1,15 +1,15 @@ ## Repository Structure -- `src/manta/` contains the Python and Verilog source needed to generate and run the cores. -- `test/` contains testbenchs for HDL. Manta is written in Verilog 2001, but the testbenches are written in SystemVerilog 2012. These are simulated using Icarus Verilog, which produces `.vcd` files, viewable with your favorite waveform viewer, like GTKWave. -- `doc/` contains the documentation you're reading right now! It's built into a nice static site by Material for MkDocs, which automatically rebuilds the site on every commit to `main`. This is done with a GitHub Action configured in `.github/` -- `examples/` is exactly what it sounds like. It contains examples for both the Digilent Nexys 4 DDR/Nexys A7 with thier onboard Series-7, as well as the Icestick with its onboard iCE40. -- `.github/` also contains some GitHub Actions configuration for automatically running the SystemVerilog testbenches and building the examples, in addition to automatically rebuilding the site. +- `src/manta/` contains the Python source needed to generate and run the cores. +- `test/` contains Manta's tests, which are a mix of functional simulations and hardware-in-the-loop testing. These tests leverage the `pytest` testing framework. +- `doc/` contains the documentation you're reading right now! +- `examples/` contains examples for both the Digilent Nexys 4 DDR/Nexys A7 with thier onboard Series-7, as well as the Icestick with its onboard iCE40. +- `.github/` contains GitHub Actions workflows for automatically running the tests and building the documentation site on every commit. ## Tools Used - The [YosysHQ](https://github.com/YosysHQ) tools and [Vivado](https://www.xilinx.com/products/design-tools/vivado.html) are used for building bitstreams. -- [Wavedrom](https://wavedrom.com/) is used for for waveform diagrams, and [draw.io](https://app.diagrams.net/) for block diagrams +- [draw.io](https://app.diagrams.net/) is used for block diagrams. - [GitHub Pages](https://pages.github.com/) is used to serve the documentation site, which is built with [Material for MkDocs](https://squidfunk.github.io/mkdocs-material/). - [GitHub Actions](https://docs.github.com/en/actions) is used for continuous integration. ## GitHub Actions Setup -Since Vivado is large and requires individual licenses it's run on a private server, which is configured as a self-hosted runner in GitHub Actions. This is a virtual server hosted with KVM/QEMU and managed by libvirt, which is configured as transient so that it reloads its state from a snapshot periodically. A Nexys A7 and Icestick are connected to the physical machine and passthrough-ed to this VM so that continuous integration can check against real hardware. \ No newline at end of file +Since Vivado is large and requires individual licenses, it is run on a private server, which is configured as a self-hosted runner in GitHub Actions. This is a virtual server hosted with KVM/QEMU and managed by libvirt, which is configured as transient so that it reloads its state from a snapshot periodically. A Nexys A7 and Icestick are connected to the physical machine and passthrough-ed to this VM so that continuous integration can check against real hardware. \ No newline at end of file

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    +
    +
    + block RAM +
    +
    +
    +     + + block RAM + +     +     + + + + +
    +
    +
    + port A +
    +
    +
    +     + + port A + +     +     + + + + + +
    +
    +
    + addr +
    +
    +
    +     + + addr + +     +     + + + + + +
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    +
    + din +
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    +
    +     + + din + +     +     + + + + + +
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    + dout +
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    +
    +
    + we +
    +
    +
    +     + + we + +     +     + + + + +
    +
    +
    + port B +
    +
    +
    +     + + port B + +     +     + + + + +
    +
    +
    + Bus Controller +
    +
    +
    +     + + Bus Controller + +     +     + + + + +
    +
    +
    + block RAM +
    +
    +
    +     + + block RAM + +     +     + + + + +
    +
    +
    + port A +
    +
    +
    +     + + port A + +     +     + + + + +
    +
    +
    + port B +
    +
    +
    +     + + port B + +     +     + + + + + + + + +
    +
    +
    + user_addr +
    +
    +
    +     + + user_addr + +     +     + + + + + +
    +
    +
    + user_din +
    +
    +
    +     + + user_din + +     +     + + + + + +
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    + user_dout +
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    +
    +     + + user_dout + +     +     + + + + + +
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    + user_we +
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    +
    +     + + user_we + +     +     + + + + + +
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    + addr +
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    +
    +     + + addr + +     +     + + + + + +
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    +
    + din +
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    +
    +     + + din + +     +     + + + + + +
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    + dout +
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    +
    +     + + dout + +     +     + + + + + +
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    +
    + we +
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    +
    +     + + we + +     +     + + + + +
    +
    +
    + block RAM +
    +
    +
    +     + + block RAM + +     +     + + + + +
    +
    +
    + port A +
    +
    +
    +     + + port A + +     +     + + + + +
    +
    +
    + port B +
    +
    +
    +     + + port B + +     +     + + + + + +
    +
    +
    + addr +
    +
    +
    +     + + addr + +     +     + + + + + +
    +
    +
    + din +
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    +
    +     + + din + +     +     + + + + + +
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    + dout +
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    +     + + dout + +     +     + + + + + +
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    + we +
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    +     + + we + +     +     + + + + +
    +
    +
    + + + ... + + +
    +
    +
    +     + + ... + +     +     + + + + + + +
    +
    +
    + 16 bits +
    +
    +
    +     + + 16 bits + +     +     + + + + + + +
    +
    +
    + 16 bits +
    +
    +
    +     + + 16 bits + +     +     + + + + + + +
    +
    +
    + 10 bits +
    +
    +
    +     + + 10 bits + +     +     + + + + + +
    +
    +
    + bus +
    +
    +
    +     + + bus + +     +     + + + + + +
    +
    +
    + bus +
    +
    +
    +     + + bus + +     +     + + + + +
    +
    +
    +

    + Memory Core +

    +
    +
    +
    +     + + Memory Core + +     +     +     + + + + + Text is not SVG - cannot display + + + +     \ No newline at end of file diff --git a/doc/assets/system_architecture.drawio.svg b/doc/assets/system_architecture.drawio.svg new file mode 100644 index 0000000..930a0c7 --- /dev/null +++ b/doc/assets/system_architecture.drawio.svg @@ -0,0 +1,342 @@ + + + + + + + + + +
    +
    +
    +

    + Host Machine +

    +
    +
    +
    +     + + Host Machine + +     +     + + + + + + +
    +
    +
    + User Application +
    +
    +
    +     + + User Application + +     +     + + + + + + +
    +
    +
    + Manta API +
    +
    +
    +     + + Manta API + +     +     + + + + + + +
    +
    +
    + Interface API +
    +
    +
    +     + + Interface API + +     +     + + + + + +
    +
    +
    + USB/Ethernet Cable +
    +
    +
    +     + + USB/Ethernet Cable + +     +     + + + + +
    +
    +
    + OS Device Driver +
    +
    +
    +     + + OS Device Driver + +     +     + + + + +
    +
    +
    + Interface Transceiver +
    +
    + (USB UART +
    + Converter / Ethernet PHY) +
    +
    +
    +     + + Interface Trans... + +     +     + + + + + + +
    +
    +
    + rxd +
    +
    +
    +     + + rxd + +     +     + + + + +
    +
    +
    + bridge_rx +
    +
    +
    +     + + bridge_rx + +     +     + + + + +
    +
    +
    + logic_analyzer +
    +
    +
    +     + + logic_analyzer + +     +     + + + + +
    +
    +
    + io_core +
    +
    +
    +     + + io_core + +     +     + + + + +
    +
    +
    + block_memory +
    +
    +
    +     + + block_memory + +     +     + + + + +
    +
    +
    + bridge_tx +
    +
    +
    +     + + bridge_tx + +     +     + + + + + + + + + + + + +
    +
    +
    + User Logic +
    +
    +
    +     + + User Logic + +     +     + + + + + + + + + + + + +
    +
    +
    + txd +
    +
    +
    +     + + txd + +     +     + + + + +
    +
    +
    +

    + FPGA Development Board +

    +
    +
    +
    +     + + FPGA Development Board + +     +     + + + + +
    +
    +
    +

    + + Manta RTL + +

    +
    +
    +
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sys.argv[1] - image_in = Image.open(input_fname) - image_in = image_in.convert('RGB') - - # Resize the image - image_in = image_in.resize((128, 128)) - image_out = image_in.copy() - w, h = image_in.size - - # Take input image and divide each color channel's value by 16 - for y in range(h): - for x in range(w): - r, g, b = image_in.getpixel((x, y)) - image_out.putpixel((x,y), (r//16, g//16, b//16)) - - - # Save the image itself - pixels = [] - for y in range(h): - for x in range(w): - (r, g, b) = image_out.getpixel((x,y)) - color = (r*16*16) + (g*16) + (b) - pixels.append(color) - - from manta import Manta - m = Manta('manta.yaml') - - addrs = list(range(len(pixels))) - m.image_mem.write(addrs, pixels) \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_ether/src/clk_gen.v b/examples/nexys_a7/video_sprite_ether/src/clk_gen.v deleted file mode 100644 index 91d4265..0000000 --- a/examples/nexys_a7/video_sprite_ether/src/clk_gen.v +++ /dev/null @@ -1,207 +0,0 @@ - -// file: clk_gen.v -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_50mhz__50.00000______0.000______50.0______150.541_____99.281 -// clk_65mhz__65.00000______0.000______50.0______142.278_____99.281 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary_________100.000____________0.010 - -`timescale 1ps/1ps - -module clk_gen - - (// Clock in ports - // Clock out ports - output clk_50mhz, - output clk_65mhz, - input clk_100mhz - ); - // Input buffering - //------------------------------------ -wire clk_100mhz_clk_gen; -wire clk_in2_clk_gen; - IBUF clkin1_ibufg - (.O (clk_100mhz_clk_gen), - .I (clk_100mhz)); - - - - - // Clocking PRIMITIVE - //------------------------------------ - - // Instantiation of the MMCM PRIMITIVE - // * Unused inputs are tied off - // * Unused outputs are labeled unused - - wire clk_50mhz_clk_gen; - wire clk_65mhz_clk_gen; - wire clk_out3_clk_gen; - wire clk_out4_clk_gen; - wire clk_out5_clk_gen; - wire clk_out6_clk_gen; - wire clk_out7_clk_gen; - - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_int; - wire clkfbout_clk_gen; - wire clkfbout_buf_clk_gen; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (9.750), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (19.500), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (15), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (10.000)) - mmcm_adv_inst - // Output clocks - ( - .CLKFBOUT (clkfbout_clk_gen), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (clk_50mhz_clk_gen), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clk_65mhz_clk_gen), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout_buf_clk_gen), - .CLKIN1 (clk_100mhz_clk_gen), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (1'b0)); - -// Clock Monitor clock assigning -//-------------------------------------- - // Output buffering - //----------------------------------- - - BUFG clkf_buf - (.O (clkfbout_buf_clk_gen), - .I (clkfbout_clk_gen)); - - - - - - - BUFG clkout1_buf - (.O (clk_50mhz), - .I (clk_50mhz_clk_gen)); - - - BUFG clkout2_buf - (.O (clk_65mhz), - .I (clk_65mhz_clk_gen)); - - - -endmodule diff --git a/examples/nexys_a7/video_sprite_ether/src/top_level.sv b/examples/nexys_a7/video_sprite_ether/src/top_level.sv deleted file mode 100644 index c1023db..0000000 --- a/examples/nexys_a7/video_sprite_ether/src/top_level.sv +++ /dev/null @@ -1,108 +0,0 @@ -`timescale 1ns / 1ps -`default_nettype none - -module top_level ( - input wire clk_100mhz, - - output reg eth_refclk, - output reg eth_rstn, - - input wire eth_crsdv, - input wire [1:0] eth_rxd, - - output reg eth_txen, - output reg [1:0] eth_txd, - - output logic [3:0] vga_r, vga_g, vga_b, - output logic vga_hs, vga_vs); - - assign eth_rstn = 1; - - // Clock generation - logic clk_50mhz; - logic clk_65mhz; - assign eth_refclk = clk_50mhz; - - clk_gen gen( - .clk_100mhz(clk_100mhz), - .clk_50mhz(clk_50mhz), - .clk_65mhz(clk_65mhz)); - - // VGA signals - logic [10:0] hcount; - logic [9:0] vcount; - logic hsync, vsync, blank; - - vga vga_gen( - .pixel_clk_in(clk_65mhz), - .hcount_out(hcount), - .vcount_out(vcount), - .hsync_out(hsync), - .vsync_out(vsync), - .blank_out(blank)); - - // VGA Pipelining - reg[1:0][10:0] hcount_pipe; - reg[1:0][10:0] vcount_pipe; - reg[1:0] hsync_pipe; - reg[1:0] vsync_pipe; - reg[1:0] blank_pipe; - - always_ff @(posedge clk_65mhz)begin - hcount_pipe[0] <= hcount; - vcount_pipe[0] <= vcount; - hsync_pipe[0] <= hsync; - vsync_pipe[0] <= vsync; - blank_pipe[0] <= blank; - for (int i=1; i<2; i = i+1)begin - hcount_pipe[i] <= hcount_pipe[i-1]; - vcount_pipe[i] <= vcount_pipe[i-1]; - hsync_pipe[i] <= hsync_pipe[i-1]; - vsync_pipe[i] <= vsync_pipe[i-1]; - blank_pipe[i] <= blank_pipe[i-1]; - end - end - - localparam WIDTH = 128; - localparam HEIGHT = 128; - - localparam X = 0; - localparam Y = 0; - - // calculate rom address - logic [$clog2(WIDTH*HEIGHT)-1:0] image_addr; - assign image_addr = (hcount - X) + ((vcount - Y) * WIDTH); - - logic in_sprite; - assign in_sprite = ((hcount_pipe[1] >= X && hcount_pipe[1] < (X + WIDTH)) && - (vcount_pipe[1] >= Y && vcount_pipe[1] < (Y + HEIGHT))); - - manta manta_inst ( - .clk(clk_50mhz), - - .crsdv(eth_crsdv), - .rxd(eth_rxd), - .txen(eth_txen), - .txd(eth_txd), - - .image_mem_clk(clk_65mhz), - .image_mem_addr(image_addr), - .image_mem_din(), - .image_mem_dout(sprite_color), - .image_mem_we(1'b0)); - - logic [11:0] sprite_color; - logic [11:0] color; - assign color = in_sprite ? sprite_color : 12'h0; - - // the following lines are required for the Nexys4 VGA circuit - do not change - assign vga_r = ~blank_pipe[1] ? color[11:8]: 0; - assign vga_g = ~blank_pipe[1] ? color[7:4] : 0; - assign vga_b = ~blank_pipe[1] ? color[3:0] : 0; - - assign vga_hs = ~hsync_pipe[1]; - assign vga_vs = ~vsync_pipe[1]; - - -endmodule -`default_nettype wire diff --git a/examples/nexys_a7/video_sprite_ether/src/vga.sv b/examples/nexys_a7/video_sprite_ether/src/vga.sv deleted file mode 100644 index 3fa787f..0000000 --- a/examples/nexys_a7/video_sprite_ether/src/vga.sv +++ /dev/null @@ -1,68 +0,0 @@ - -/* vga: Generate VGA display signals (1024 x 768 @ 60Hz) - * - * ---- HORIZONTAL ----- ------VERTICAL ----- - * Active Active - * Freq Video FP Sync BP Video FP Sync BP - * 640x480, 60Hz 25.175 640 16 96 48 480 11 2 31 - * 800x600, 60Hz 40.000 800 40 128 88 600 1 4 23 - * 1024x768, 60Hz 65.000 1024 24 136 160 768 3 6 29 - * 1280x1024, 60Hz 108.00 1280 48 112 248 768 1 3 38 - * 1280x720p 60Hz 75.25 1280 72 80 216 720 3 5 30 - * 1920x1080 60Hz 148.5 1920 88 44 148 1080 4 5 36 - * - * change the clock frequency, front porches, sync's, and back porches to create - * other screen resolutions - */ - -module vga( - input wire pixel_clk_in, - output logic [10:0] hcount_out, // pixel number on current line - output logic [9:0] vcount_out, // line number - output logic vsync_out, hsync_out, - output logic blank_out); - - parameter DISPLAY_WIDTH = 1024; // display width - parameter DISPLAY_HEIGHT = 768; // number of lines - - parameter H_FP = 24; // horizontal front porch - parameter H_SYNC_PULSE = 136; // horizontal sync - parameter H_BP = 160; // horizontal back porch - - parameter V_FP = 3; // vertical front porch - parameter V_SYNC_PULSE = 6; // vertical sync - parameter V_BP = 29; // vertical back porch - - // horizontal: 1344 pixels total - // display 1024 pixels per line - logic hblank,vblank; - logic hsyncon,hsyncoff,hreset,hblankon; - assign hblankon = (hcount_out == (DISPLAY_WIDTH -1)); - assign hsyncon = (hcount_out == (DISPLAY_WIDTH + H_FP - 1)); //1047 - assign hsyncoff = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE - 1)); // 1183 - assign hreset = (hcount_out == (DISPLAY_WIDTH + H_FP + H_SYNC_PULSE + H_BP - 1)); //1343 - - // vertical: 806 lines total - // display 768 lines - logic vsyncon,vsyncoff,vreset,vblankon; - assign vblankon = hreset & (vcount_out == (DISPLAY_HEIGHT - 1)); // 767 - assign vsyncon = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP - 1)); // 771 - assign vsyncoff = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE - 1)); // 777 - assign vreset = hreset & (vcount_out == (DISPLAY_HEIGHT + V_FP + V_SYNC_PULSE + V_BP - 1)); // 805 - - // sync and blanking - logic next_hblank,next_vblank; - assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank; - assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank; - always_ff @(posedge pixel_clk_in) begin - hcount_out <= hreset ? 0 : hcount_out + 1; - hblank <= next_hblank; - hsync_out <= hsyncon ? 0 : hsyncoff ? 1 : hsync_out; // active low - - vcount_out <= hreset ? (vreset ? 0 : vcount_out + 1) : vcount_out; - vblank <= next_vblank; - vsync_out <= vsyncon ? 0 : vsyncoff ? 1 : vsync_out; // active low - - blank_out <= next_vblank | (next_hblank & ~hreset); - end -endmodule \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_ether/xdc/top_level.xdc b/examples/nexys_a7/video_sprite_ether/xdc/top_level.xdc deleted file mode 100644 index 8a3551b..0000000 --- a/examples/nexys_a7/video_sprite_ether/xdc/top_level.xdc +++ /dev/null @@ -1,253 +0,0 @@ -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## This file has been modified from the default .xdc provided by Digilent for the Nexys A7 - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; - - -##Switches - -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] - -set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] - -set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv -#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file diff --git a/examples/nexys_a7/video_sprite_uart/img/buff_doge.png b/examples/nexys_a7/video_sprite_uart/img/buff_doge.png deleted file mode 100644 index d504d022b1fbe9896a43e008ec41ffbad202d00d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 69692 zcmeFZWl&t*wl>;0!5at=v}r5^clX9!gS$2E?(PH$Zb5@XaMuJva1HJf++8m3yZ6~= z@A|%~Tc_&Ye}^iHwdNe-8FM^CdabTeL@FsrqN5O^0001VX(@;b008rP2?Iceef=|q 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