From ccc75270a88f672a86cbb7303299958ecf50774f Mon Sep 17 00:00:00 2001 From: Kenneth Wilke Date: Sun, 31 Mar 2024 23:17:03 -0500 Subject: [PATCH 1/3] Update getting_started.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I was working through using Manta for the first time, and the only bit that gave me a struggle so far was that I was expecting the `rst` signal to be active LOW. I thought this might be worth calling out in the documentation here. Awesome project btw, will definitely be using it more and try to contribute as I can! 😄 --- doc/getting_started.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/doc/getting_started.md b/doc/getting_started.md index 7494a49..70f900f 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -60,6 +60,8 @@ This Manta instance has an IO Core and a Logic Analyzer, each containing a numbe Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design by running `manta inst [config_file]`. For example, the following snippet is generated for the configuration above: +> Note: The reset signal, `rst`, is an active HIGH signal. + ```verilog manta manta_inst ( .clk(clk), @@ -73,4 +75,4 @@ manta manta_inst ( .larry(larry), .curly(curly), .moe(moe)); -``` \ No newline at end of file +``` From af0dec7d764a5c0f26e10fbfa69db60fdad3b136 Mon Sep 17 00:00:00 2001 From: Kenneth Wilke Date: Fri, 5 Apr 2024 19:03:01 -0500 Subject: [PATCH 2/3] Updated reset note and a doc link --- doc/getting_started.md | 5 ++++- doc/logic_analyzer_core.md | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/doc/getting_started.md b/doc/getting_started.md index 70f900f..c28a0a6 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -60,7 +60,10 @@ This Manta instance has an IO Core and a Logic Analyzer, each containing a numbe Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design by running `manta inst [config_file]`. For example, the following snippet is generated for the configuration above: -> Note: The reset signal, `rst`, is an active HIGH signal. + +!!! note "Reset is active HIGH" + + The manta instance resets while `rst` signal is held high. If you want to share reset logic with an active LOW reset signal, e.g. `rst_n`, be sure to invert this signal before passing it in. ```verilog manta manta_inst ( diff --git a/doc/logic_analyzer_core.md b/doc/logic_analyzer_core.md index 69aed07..7e89b70 100644 --- a/doc/logic_analyzer_core.md +++ b/doc/logic_analyzer_core.md @@ -117,5 +117,5 @@ This is useful for two situations in particular: - _Sparse Sampling_ Sometimes designs will have a small number of inputs, but a huge amount of internal state. In situations like these, it may be more efficient to sample the inputs and simulate the logic, instead of directly sampling the state. For instance, debugging a misbehaving branch predictor in a CPU can be done by recording activity on the address and data busses and playing them back in simulation - which would use less FPGA resources than sampling the entire pattern history table. ## Python API -The Logic Analyzer core functionality is stored in the `Manta.LogicAnalyzerCore` class in [src/manta/la_core/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/la_core/__init__.py). This class contains methods for capturing data, exporting it as `.vcd`, `.v` or `.csv` files, or as a Python list. +The Logic Analyzer core functionality is stored in the `Manta.LogicAnalyzerCore` class in [src/manta/logic_analyzer/\_\_init\_\_.py](https://github.com/fischermoseley/manta/blob/main/src/manta/logic_analyzer/__init__.py). This class contains methods for capturing data, exporting it as `.vcd`, `.v` or `.csv` files, or as a Python list. From 7a44f34ae3c43d0f549b7adf02e756e33513fc62 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 5 Apr 2024 23:46:54 -0700 Subject: [PATCH 3/3] tweak wording of active low reset warning --- doc/getting_started.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/getting_started.md b/doc/getting_started.md index c28a0a6..cf7a5cd 100644 --- a/doc/getting_started.md +++ b/doc/getting_started.md @@ -61,9 +61,9 @@ This Manta instance has an IO Core and a Logic Analyzer, each containing a numbe Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design by running `manta inst [config_file]`. For example, the following snippet is generated for the configuration above: -!!! note "Reset is active HIGH" +!!! note "Reset is active high!" - The manta instance resets while `rst` signal is held high. If you want to share reset logic with an active LOW reset signal, e.g. `rst_n`, be sure to invert this signal before passing it in. + The Manta instance will reset while `rst` is held high. If you want to share reset logic with an active low reset signal (for example, `rst_n`), be sure to invert it first. ```verilog manta manta_inst (