From 8c645a5115957c13d00694088e0e48dfd01325c6 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Wed, 8 Mar 2023 13:52:13 -0500
Subject: [PATCH] update github workflows to use Makefile for sim

---
 .github/workflows/functional_simulation.yml | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/.github/workflows/functional_simulation.yml b/.github/workflows/functional_simulation.yml
index 5956b07..113a5a2 100644
--- a/.github/workflows/functional_simulation.yml
+++ b/.github/workflows/functional_simulation.yml
@@ -1,18 +1,9 @@
 name: functional_simulation
 on: [push]
 jobs:
-  uart:
+  all:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v3
       - run: sudo apt install iverilog
-      - run: iverilog -g2012 -o sim.out test/uart_tb.sv src/manta/uart_tx.sv src/manta/uart_rx.sv
-      - run: vvp sim.out
-  
-  fifo:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v3
-      - run: sudo apt install iverilog
-      - run: iverilog -g2012 -o sim.out test/fifo_tb.sv src/manta/fifo.sv src/manta/xilinx_true_dual_port_read_first_2_clock_ram.v
-      - run: vvp sim.out
\ No newline at end of file
+      - run: make sim 
\ No newline at end of file