From 839bd4f8e46b0f8154005d01561a71e18d20f521 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Sat, 1 Apr 2023 16:38:45 -0700
Subject: [PATCH] update arg order for iverilog - seems to throw errors across
 versions/OSs

---
 Makefile | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile
index b595e42..5f90228 100644
--- a/Makefile
+++ b/Makefile
@@ -27,47 +27,47 @@ api_gen:
 func_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb 
 
 io_core_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/io_core_tb.sv -y src/manta
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/io_core_tb.sv
 	vvp sim.out
 	rm sim.out
 
 logic_analyzer_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/logic_analyzer_tb.sv -y src/manta
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/logic_analyzer_tb.sv
 	vvp sim.out
 	rm sim.out
 
 bit_fifo_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/bit_fifo_tb.sv -y src/manta
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bit_fifo_tb.sv
 	vvp sim.out
 	rm sim.out
 
 bridge_rx_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/bridge_rx_tb.sv -y src/manta
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bridge_rx_tb.sv
 	vvp sim.out
 	rm sim.out
 
 bridge_tx_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/bridge_tx_tb.sv -y src/manta
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/bridge_tx_tb.sv
 	vvp sim.out
 	rm sim.out
 
 fifo_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/fifo_tb.sv -y src/manta 
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/fifo_tb.sv 
 	vvp sim.out >> /dev/null # this one is noisy right now
 	rm sim.out
 
 lut_ram_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/lut_ram_tb.sv -y src/manta
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/lut_ram_tb.sv
 	vvp sim.out
 	rm sim.out
 
 uart_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/uart_tb.sv -y src/manta
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/uart_tb.sv
 	vvp sim.out
 	rm sim.out
 
 uart_tx_tb:
-	iverilog -g2012 -o sim.out test/hdl_tb/uart_tx_tb.sv -y src/manta
+	iverilog -g2012 -o sim.out -y src/manta test/hdl_tb/uart_tx_tb.sv
 	vvp sim.out
 	rm sim.out