From 82f289aa748fe4da9869cc07d4d9d1b34f2093fb Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 14 Jan 2026 14:43:55 -0700 Subject: [PATCH] logic_analyzer: use context manager for VCD file export --- src/manta/logic_analyzer/capture.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/manta/logic_analyzer/capture.py b/src/manta/logic_analyzer/capture.py index 30b111f..b5739f4 100644 --- a/src/manta/logic_analyzer/capture.py +++ b/src/manta/logic_analyzer/capture.py @@ -129,9 +129,11 @@ class LogicAnalyzerCapture: # Use the same datetime format that iVerilog uses timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y") - vcd_file = open(path, "w") - with VCDWriter(vcd_file, timescale, timestamp, "manta") as writer: + with ( + open(path, "w") as vcd_file, + VCDWriter(vcd_file, timescale, timestamp, "manta") as writer, + ): # Each probe has a name, width, and writer associated with it signals = [] for p in self._probes: @@ -168,8 +170,6 @@ class LogicAnalyzerCapture: writer.change(var, sample_timestamp, sample) - vcd_file.close() - def get_playback_module(self): """ Returns an Amaranth module that will playback the captured data. This