diff --git a/src/manta/logic_analyzer/capture.py b/src/manta/logic_analyzer/capture.py
index 30b111f..b5739f4 100644
--- a/src/manta/logic_analyzer/capture.py
+++ b/src/manta/logic_analyzer/capture.py
@@ -129,9 +129,11 @@ class LogicAnalyzerCapture:
 
         # Use the same datetime format that iVerilog uses
         timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y")
-        vcd_file = open(path, "w")
 
-        with VCDWriter(vcd_file, timescale, timestamp, "manta") as writer:
+        with (
+            open(path, "w") as vcd_file,
+            VCDWriter(vcd_file, timescale, timestamp, "manta") as writer,
+        ):
             # Each probe has a name, width, and writer associated with it
             signals = []
             for p in self._probes:
@@ -168,8 +170,6 @@ class LogicAnalyzerCapture:
 
                     writer.change(var, sample_timestamp, sample)
 
-        vcd_file.close()
-
     def get_playback_module(self):
         """
         Returns an Amaranth module that will playback the captured data. This