diff --git a/examples/amaranth/ethernet_io_core.py b/examples/amaranth/ethernet_io_core.py
index 45cfbe2..b0be3ef 100644
--- a/examples/amaranth/ethernet_io_core.py
+++ b/examples/amaranth/ethernet_io_core.py
@@ -76,13 +76,6 @@ class EthernetIOCoreExample(Elaboratable):
         #     rmii_mdio = eth_pins.mdio,
         # )
 
-        # m.submodules.rxd = rxd = io.Buffer("i", eth_pins.rxd)
-        # m.submodules.crs_dv = crs_dv = io.Buffer("i", eth_pins.crs_dv)
-        # m.submodules.txen = txen = io.Buffer("o", eth_pins.txen)
-        # m.submodules.txd = txd = io.Buffer("o", eth_pins.txd)
-        # m.submodules.mdc = mdc = io.Buffer("o", eth_pins.mdc)
-        # m.submodules.mdio = mdio = io.SingleEndedPort(io.Buffer("io", eth_pins.mdio))
-
         m.submodules.eth_clk_io_buf = eth_clk_io_buf = io.Buffer("o", eth_pins.clk)
         m.d.comb += eth_clk_io_buf.o.eq(ethclk.clk)
 
@@ -97,8 +90,6 @@ class EthernetIOCoreExample(Elaboratable):
             ("io", "rmii_mdio", eth_pins.mdio.io),
         ]
 
-        platform.add_file("liteeth.v", self.manta.interface.generate_liteeth_core())
-
         return m
 
     def test(self):
diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py
index a31ea6f..ecef087 100644
--- a/src/manta/ethernet/__init__.py
+++ b/src/manta/ethernet/__init__.py
@@ -293,6 +293,12 @@ class EthernetInterface(Elaboratable):
             ("i", "udp0_sink_valid", self._sink_valid),
         )
 
+        # Add LiteEth module definition if we're in an Amaranth-native workflow
+        # If we're in a Verilog-based workflow, then platform will be None, and
+        # the module will be added in manta.generate_verilog()
+        if platform:
+            platform.add_file("liteeth.v", self.generate_liteeth_core())
+
         m.submodules.source_bridge = source_bridge = UDPSourceBridge()
         m.submodules.sink_bridge = sink_bridge = UDPSinkBridge()