diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py
index c55b82b..4b8f466 100644
--- a/src/manta/logic_analyzer/__init__.py
+++ b/src/manta/logic_analyzer/__init__.py
@@ -191,6 +191,11 @@ class LogicAnalyzerCore(Elaboratable):
     def get_top_level_ports(self):
         return self.probes
 
+    def get_probe(self, name):
+        for p in self.probes:
+            if p.name == name:
+                return p
+
     def get_max_addr(self):
         return self.sample_mem.get_max_addr()
 
diff --git a/src/manta/logic_analyzer/trigger_block.py b/src/manta/logic_analyzer/trigger_block.py
index 9e446e0..2b15530 100644
--- a/src/manta/logic_analyzer/trigger_block.py
+++ b/src/manta/logic_analyzer/trigger_block.py
@@ -67,11 +67,8 @@ class LogicAnalyzerTriggerBlock(Elaboratable):
         for t in self.triggers:
             m.submodules[t.signal.name + "_trigger"] = t
 
+        # Connect IO core registers to triggers
         for probe, trigger in zip(self.probes, self.triggers):
-            # Connect trigger input signals to top-level signals
-            m.d.comb += trigger.signal.eq(probe)
-
-            # Connect IO core registers to triggers
             m.d.comb += trigger.arg.eq(getattr(self.r, probe.name + "_arg"))
             m.d.comb += trigger.op.eq(getattr(self.r, probe.name + "_op"))