From 7e707e1fc192b984072151cd75a1946d2ae872e3 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Sun, 30 Jul 2023 19:13:16 -0700
Subject: [PATCH] manually specify vivado path in makefile

---
 Makefile                    | 35 ++++++++++++++----------------
 examples/nexys_a7/build.tcl | 43 +++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 19 deletions(-)
 create mode 100644 examples/nexys_a7/build.tcl

diff --git a/Makefile b/Makefile
index 821f85f..ddf2800 100644
--- a/Makefile
+++ b/Makefile
@@ -1,3 +1,5 @@
+VIVADO_PATH=/tools/Xilinx/Vivado/2023.1/bin/vivado
+
 test: auto_gen sim formal
 
 examples: icestick nexys_a7
@@ -107,49 +109,44 @@ formal:
 nexys_a7: nexys_a7_io_core_ether nexys_a7_io_core_uart nexys_a7_ps2_logic_analyzer nexys_a7_video_sprite_ether nexys_a7_video_sprite_uart
 
 nexys_a7_io_core_ether:
-	cd examples/nexys_a7/io_core_ether/;\
+	cd examples/nexys_a7/io_core_ether/; \
 	python3 -m manta gen manta.yaml src/manta.v; \
 	rm -rf obj; \
 	mkdir -p obj; \
-	wget -nc https://fpga.mit.edu/6205/_static/F22/labs/lab05/build.tcl; \
-	vivado -mode batch -source build.tcl
+	$(VIVADO_PATH) -mode batch -source ../build.tcl
 
 nexys_a7_io_core_uart:
 	cd examples/nexys_a7/io_core_uart/; \
-	python3 -m manta gen manta.yaml src/manta.v;		\
+	python3 -m manta gen manta.yaml src/manta.v; \
 	rm -rf obj; \
 	mkdir -p obj; \
-	wget -nc https://fpga.mit.edu/6205/_static/F22/labs/lab05/build.tcl; \
-	vivado -mode batch -source build.tcl
+	$(VIVADO_PATH) -mode batch -source ../build.tcl
 
 nexys_a7_ps2_logic_analyzer:
-	cd examples/nexys_a7/ps2_logic_analyzer/;  					\
-	python3 -m manta gen manta.yaml src/manta.v;							\
+	cd examples/nexys_a7/ps2_logic_analyzer/; \
+	python3 -m manta gen manta.yaml src/manta.v; \
 	manta playback manta.yaml my_logic_analyzer sim/playback.v;	\
 	rm -rf obj; \
 	mkdir -p obj; \
-	wget -nc https://fpga.mit.edu/6205/_static/F22/labs/lab05/build.tcl; \
-	vivado -mode batch -source build.tcl
+	$(VIVADO_PATH) -mode batch -source ../build.tcl
 
 nexys_a7_video_sprite_ether:
-	cd examples/nexys_a7/video_sprite_ether;\
-	python3 -m manta gen manta.yaml src/manta.v;		\
+	cd examples/nexys_a7/video_sprite_ether; \
+	python3 -m manta gen manta.yaml src/manta.v; \
 	rm -rf obj; \
 	mkdir -p obj; \
-	wget -nc https://fpga.mit.edu/6205/_static/F22/labs/lab05/build.tcl; \
-	vivado -mode batch -source build.tcl
+	$(VIVADO_PATH) -mode batch -source ../build.tcl
 
 nexys_a7_video_sprite_uart:
 	cd examples/nexys_a7/video_sprite_uart;	\
-	python3 -m manta gen manta.yaml src/manta.v;		\
+	python3 -m manta gen manta.yaml src/manta.v; \
 	rm -rf obj; \
 	mkdir -p obj; \
-	wget -nc https://fpga.mit.edu/6205/_static/F22/labs/lab05/build.tcl; \
-	vivado -mode batch -source build.tcl
+	$(VIVADO_PATH) -mode batch -source ../build.tcl
 
 icestick: icestick_io_core
 
 icestick_io_core:
-	cd examples/icestick/io_core/;	\
-	python3 -m manta gen manta.yaml manta.v;  	\
+	cd examples/icestick/io_core/; \
+	python3 -m manta gen manta.yaml manta.v; \
 	./build.sh
diff --git a/examples/nexys_a7/build.tcl b/examples/nexys_a7/build.tcl
new file mode 100644
index 0000000..548cc7e
--- /dev/null
+++ b/examples/nexys_a7/build.tcl
@@ -0,0 +1,43 @@
+#!/usr/bin/tclsh
+
+set partNum xc7a100tcsg324-1
+set outputDir obj
+
+file mkdir $outputDir
+set files [glob -nocomplain "$outputDir/*"]
+if {[llength $files] != 0} {
+    file delete -force {*}[glob -directory $outputDir *];
+}
+
+read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ]
+read_xdc ./xdc/top_level.xdc
+
+set_part $partNum
+
+# synth
+synth_design -top top_level -part $partNum -verbose
+report_utilization -file $outputDir/post_synth_util.rpt
+report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
+report_timing -file $outputDir/post_synth_timing.rpt
+
+# place
+opt_design
+place_design
+phys_opt_design
+report_utilization -file $outputDir/post_place_util.rpt
+
+report_clock_utilization -file $outputDir/clock_util.rpt
+report_timing_summary -file $outputDir/post_place_timing_summary.rpt
+report_timing -file $outputDir/post_place_timing.rpt
+
+# route design and generate bitstream
+
+route_design -directive Explore
+write_bitstream -force $outputDir/final.bit
+
+report_route_status -file $outputDir/post_route_status.rpt
+report_timing_summary -file $outputDir/post_route_timing_summary.rpt
+report_timing -file $outputDir/post_route_timing.rpt
+report_power -file $outputDir/post_route_power.rpt
+report_drc -file $outputDir/post_imp_drc.rpt
+write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true