diff --git a/src/manta/__init__.py b/src/manta/__init__.py
index 828c699..9e3c3c4 100644
--- a/src/manta/__init__.py
+++ b/src/manta/__init__.py
@@ -546,6 +546,7 @@ class LogicAnalyzerCore:
         # load source files
         hdl = self.gen_logic_analyzer_def() + "\n"
         hdl += VerilogManipulator("logic_analyzer_controller.v").get_hdl() + "\n"
+        hdl += VerilogManipulator("logic_analyzer_fsm_registers.v").get_hdl() + "\n"
         hdl += VerilogManipulator("block_memory.v").get_hdl() + "\n"
         hdl += VerilogManipulator("dual_port_bram.v").get_hdl() + "\n"
         hdl += self.gen_trigger_block_def() + "\n"
diff --git a/src/manta/logic_analyzer_controller.v b/src/manta/logic_analyzer_controller.v
index 492014a..953acaf 100644
--- a/src/manta/logic_analyzer_controller.v
+++ b/src/manta/logic_analyzer_controller.v
@@ -84,13 +84,7 @@ module logic_analyzer_controller (
             end
         end
 
-        else if(state == CAPTURED) begin
-            // actually nothing to do here doooodeeedoooo
-        end
-
         else if(request_stop && ~prev_request_stop) state <= IDLE;
-
-        else state <= IDLE;
     end