From 7a44f34ae3c43d0f549b7adf02e756e33513fc62 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Fri, 5 Apr 2024 23:46:54 -0700
Subject: [PATCH] tweak wording of active low reset warning

---
 doc/getting_started.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/doc/getting_started.md b/doc/getting_started.md
index c28a0a6..cf7a5cd 100644
--- a/doc/getting_started.md
+++ b/doc/getting_started.md
@@ -61,9 +61,9 @@ This Manta instance has an IO Core and a Logic Analyzer, each containing a numbe
 Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design by running `manta inst [config_file]`. For example, the following snippet is generated for the configuration above:
 
 
-!!! note "Reset is active HIGH"
+!!! note "Reset is active high!"
 
-    The manta instance resets while `rst` signal is held high. If you want to share reset logic with an active LOW reset signal, e.g. `rst_n`, be sure to invert this signal before passing it in.
+    The Manta instance will reset while `rst` is held high. If you want to share reset logic with an active low reset signal (for example, `rst_n`), be sure to invert it first.
 
 ```verilog
 manta manta_inst (