From 70e2bd10e74da249f0a6e637e6444f416f2a28b5 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 3 Mar 2023 16:58:09 -0500 Subject: [PATCH] rename, slightly patch bridge_tx --- .DS_Store | Bin 0 -> 6148 bytes .gitignore | 7 + .../{counter => single_lut_ram}/lab-bc.py | 0 .../{counter => single_lut_ram}/manta.yaml | 0 .../{counter => single_lut_ram}/read.py | 0 .../src/bridge_rx.v | 0 .../src/bridge_tx.v | 6 - .../{counter => single_lut_ram}/src/lut_mem.v | 0 .../{counter => single_lut_ram}/src/manta.v | 0 .../{counter => single_lut_ram}/src/rx_uart.v | 0 .../{counter => single_lut_ram}/src/ssd.v | 0 .../src/top_level.sv | 0 .../{counter => single_lut_ram}/src/uart_tx.v | 1 + .../{counter => single_lut_ram}/write.py | 3 +- .../xdc/top_level.xdc | 0 src/manta/bridge_tx.v | 6 - test/minimal_bus_tb.sv | 226 ++++++++++++++++++ 17 files changed, 235 insertions(+), 14 deletions(-) create mode 100644 .DS_Store rename examples/nexys_a7/{counter => single_lut_ram}/lab-bc.py (100%) rename examples/nexys_a7/{counter => single_lut_ram}/manta.yaml (100%) rename examples/nexys_a7/{counter => single_lut_ram}/read.py (100%) rename examples/nexys_a7/{counter => single_lut_ram}/src/bridge_rx.v (100%) rename examples/nexys_a7/{counter => single_lut_ram}/src/bridge_tx.v (92%) rename examples/nexys_a7/{counter => single_lut_ram}/src/lut_mem.v (100%) rename examples/nexys_a7/{counter => single_lut_ram}/src/manta.v (100%) rename examples/nexys_a7/{counter => single_lut_ram}/src/rx_uart.v (100%) rename examples/nexys_a7/{counter => single_lut_ram}/src/ssd.v (100%) rename examples/nexys_a7/{counter => single_lut_ram}/src/top_level.sv (100%) rename examples/nexys_a7/{counter => single_lut_ram}/src/uart_tx.v (98%) rename examples/nexys_a7/{counter => single_lut_ram}/write.py (83%) rename examples/nexys_a7/{counter => single_lut_ram}/xdc/top_level.xdc (100%) create mode 100644 test/minimal_bus_tb.sv diff --git a/.DS_Store b/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..c3ac046f6c51a2cd4bc2df32c603e493458c382e GIT binary patch literal 6148 zcmeH~F^{dt=u>Bl;zddfqZjB=JE!l7EiIwCR znHYd=e=Zwf1hAw#vGy=AV?N-4FWm9?zTD5J+wJN_+D8XGrH`2G=e8gPq<|EV0#ZN< z%t(Pe#+RQndL})J6p#Y*P{6+rh3>4$))}7;h8O|Jf#oo+W0oL`7s#4yovhF-rw7Yc zi!sFO(N31Ut|nV&Z-?dZVR>isDTZdf9afmotOgXMfE1W0u;}^d=l`Dm-~2ymQ7Q$b zz?&&x!|t%#@}=@@{quTWKW5d}jZVhp3{O7+O#CQb(Zjf3d_mS^>tuzdAAyiTK?=N7 FfnTX=61e~X literal 0 HcmV?d00001 diff --git a/.gitignore b/.gitignore index 2b760e1..295c3e6 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,13 @@ +# Vivado output products *.log +*.jou +*.rpt *.bit + +# iVerilog output products *.vcd *.out + +# Python Packaging output dist/ *.egg-info \ No newline at end of file diff --git a/examples/nexys_a7/counter/lab-bc.py b/examples/nexys_a7/single_lut_ram/lab-bc.py similarity index 100% rename from examples/nexys_a7/counter/lab-bc.py rename to examples/nexys_a7/single_lut_ram/lab-bc.py diff --git a/examples/nexys_a7/counter/manta.yaml b/examples/nexys_a7/single_lut_ram/manta.yaml similarity index 100% rename from examples/nexys_a7/counter/manta.yaml rename to examples/nexys_a7/single_lut_ram/manta.yaml diff --git a/examples/nexys_a7/counter/read.py b/examples/nexys_a7/single_lut_ram/read.py similarity index 100% rename from examples/nexys_a7/counter/read.py rename to examples/nexys_a7/single_lut_ram/read.py diff --git a/examples/nexys_a7/counter/src/bridge_rx.v b/examples/nexys_a7/single_lut_ram/src/bridge_rx.v similarity index 100% rename from examples/nexys_a7/counter/src/bridge_rx.v rename to examples/nexys_a7/single_lut_ram/src/bridge_rx.v diff --git a/examples/nexys_a7/counter/src/bridge_tx.v b/examples/nexys_a7/single_lut_ram/src/bridge_tx.v similarity index 92% rename from examples/nexys_a7/counter/src/bridge_tx.v rename to examples/nexys_a7/single_lut_ram/src/bridge_tx.v index 2bfd895..c1a81d8 100644 --- a/examples/nexys_a7/counter/src/bridge_tx.v +++ b/examples/nexys_a7/single_lut_ram/src/bridge_tx.v @@ -76,12 +76,6 @@ always @(posedge clk) begin axiod <= 8'h0A; if (axior) begin axiov <= 0; - bytes_transmitted <= 7; - end - end - - else if(bytes_transmitted == 7) begin - if(axior) begin res_ready <= 1; bytes_transmitted <= 0; end diff --git a/examples/nexys_a7/counter/src/lut_mem.v b/examples/nexys_a7/single_lut_ram/src/lut_mem.v similarity index 100% rename from examples/nexys_a7/counter/src/lut_mem.v rename to examples/nexys_a7/single_lut_ram/src/lut_mem.v diff --git a/examples/nexys_a7/counter/src/manta.v b/examples/nexys_a7/single_lut_ram/src/manta.v similarity index 100% rename from examples/nexys_a7/counter/src/manta.v rename to examples/nexys_a7/single_lut_ram/src/manta.v diff --git a/examples/nexys_a7/counter/src/rx_uart.v b/examples/nexys_a7/single_lut_ram/src/rx_uart.v similarity index 100% rename from examples/nexys_a7/counter/src/rx_uart.v rename to examples/nexys_a7/single_lut_ram/src/rx_uart.v diff --git a/examples/nexys_a7/counter/src/ssd.v b/examples/nexys_a7/single_lut_ram/src/ssd.v similarity index 100% rename from examples/nexys_a7/counter/src/ssd.v rename to examples/nexys_a7/single_lut_ram/src/ssd.v diff --git a/examples/nexys_a7/counter/src/top_level.sv b/examples/nexys_a7/single_lut_ram/src/top_level.sv similarity index 100% rename from examples/nexys_a7/counter/src/top_level.sv rename to examples/nexys_a7/single_lut_ram/src/top_level.sv diff --git a/examples/nexys_a7/counter/src/uart_tx.v b/examples/nexys_a7/single_lut_ram/src/uart_tx.v similarity index 98% rename from examples/nexys_a7/counter/src/uart_tx.v rename to examples/nexys_a7/single_lut_ram/src/uart_tx.v index 554d087..9f2f2f5 100644 --- a/examples/nexys_a7/counter/src/uart_tx.v +++ b/examples/nexys_a7/single_lut_ram/src/uart_tx.v @@ -47,6 +47,7 @@ module uart_tx( // transfers if(axiiv && ~busy) begin busy <= 1; + baud_counter <= 0; data_buf <= axiid; end diff --git a/examples/nexys_a7/counter/write.py b/examples/nexys_a7/single_lut_ram/write.py similarity index 83% rename from examples/nexys_a7/counter/write.py rename to examples/nexys_a7/single_lut_ram/write.py index ecb9330..9911c25 100644 --- a/examples/nexys_a7/counter/write.py +++ b/examples/nexys_a7/single_lut_ram/write.py @@ -4,9 +4,8 @@ from time import sleep with serial.Serial("/dev/tty.usbserial-210292AE39A41", 115200) as ser: for i in range(8): req = '{:04X}'.format(i) - req = f"M{req}1234\r\n " + req = f"M{req}5678\r\n" req = req.encode('ascii') ser.write(req) print(f"req --> {req}") - sleep(0.1) \ No newline at end of file diff --git a/examples/nexys_a7/counter/xdc/top_level.xdc b/examples/nexys_a7/single_lut_ram/xdc/top_level.xdc similarity index 100% rename from examples/nexys_a7/counter/xdc/top_level.xdc rename to examples/nexys_a7/single_lut_ram/xdc/top_level.xdc diff --git a/src/manta/bridge_tx.v b/src/manta/bridge_tx.v index 2bfd895..c1a81d8 100644 --- a/src/manta/bridge_tx.v +++ b/src/manta/bridge_tx.v @@ -76,12 +76,6 @@ always @(posedge clk) begin axiod <= 8'h0A; if (axior) begin axiov <= 0; - bytes_transmitted <= 7; - end - end - - else if(bytes_transmitted == 7) begin - if(axior) begin res_ready <= 1; bytes_transmitted <= 0; end diff --git a/test/minimal_bus_tb.sv b/test/minimal_bus_tb.sv new file mode 100644 index 0000000..472a76e --- /dev/null +++ b/test/minimal_bus_tb.sv @@ -0,0 +1,226 @@ +`default_nettype none +`timescale 1ns/1ps + +`define CP 10 +`define HCP 5 + +`define SEND_MSG_BITS(MSG) \ + for(int j=0; j < $size(msg); j++) begin \ + char = msg[j]; \ + for(int i=0; i < 10; i++) begin \ + if (i == 0) tb_urx_rxd = 0; \ + else if ((i > 0) & (i < 9)) tb_urx_rxd = char[i-1]; \ + else if (i == 9) tb_urx_rxd = 1; \ + #(10*`CP); \ + end \ + end \ + +module minimal_bus_tb; + // https://www.youtube.com/watch?v=WCOAr-96bGc + + //boilerplate + logic clk; + logic rst; + integer test_num; + string msg; + logic [7:0] char; + logic baud_counter; + + assign baud_counter = utx.baud_counter == 0; + + // tb --> uart_rx signals + logic tb_urx_rxd; + uart_rx #( + .DATA_WIDTH(8), + .CLK_FREQ_HZ(100_000_000), + .BAUDRATE(10_000_000) + ) urx ( + .clk(clk), + .rst(rst), + .rxd(tb_urx_rxd), + + .axiod(urx_brx_axid), + .axiov(urx_brx_axiv)); + + // uart_rx --> bridge_rx signals + logic [7:0] urx_brx_axid; + logic urx_brx_axiv; + + bridge_rx brx ( + .clk(clk), + + .axiid(urx_brx_axid), + .axiiv(urx_brx_axiv), + + .req_addr(brx_mem_addr), + .req_data(brx_mem_wdata), + .req_rw(brx_mem_rw), + .req_valid(brx_mem_valid), + .req_ready(1'b1)); + + // bridge_rx --> mem signals + logic [15:0] brx_mem_addr; + logic [15:0] brx_mem_wdata; + logic brx_mem_rw; + logic brx_mem_valid; + + lut_mem #( + .DEPTH(8), + .BASE_ADDR(0) + ) mem ( + .clk(clk), + .addr_i(brx_mem_addr), + .wdata_i(brx_mem_wdata), + .rdata_i(0), + .rw_i(brx_mem_rw), + .valid_i(brx_mem_valid), + + .addr_o(mem_btx_addr), + .wdata_o(mem_btx_wdata), + .rdata_o(mem_btx_rdata), + .rw_o(mem_btx_rw), + .valid_o(mem_btx_valid)); + + // mem --> bridge_tx signals + logic [15:0] mem_btx_addr; + logic [15:0] mem_btx_wdata; + logic [15:0] mem_btx_rdata; + logic mem_btx_rw; + logic mem_btx_valid; + + bridge_tx btx ( + .clk(clk), + + .res_data(mem_btx_rdata), + .res_valid(mem_btx_valid), + .res_ready(), + + .axiod(btx_utx_axid), + .axiov(btx_utx_axiv), + .axior(btx_utx_axir)); + + // bridge_tx --> uart_tx signals + logic [7:0] btx_utx_axid; + logic btx_utx_axiv; + logic btx_utx_axir; + + uart_tx #( + .DATA_WIDTH(8), + .CLK_FREQ_HZ(100_000_000), + .BAUDRATE(10_000_000) + ) utx ( + .clk(clk), + .rst(rst), + + .axiid(btx_utx_axid), + .axiiv(btx_utx_axiv), + .axiir(btx_utx_axir), + .txd(utx_tb_txd)); + + // utx --> tb signals + logic utx_tb_txd; + + /* + actually just for shiggles let's see what happens when you put a uart_rx on a uart_tx + */ + + uart_rx #( + .DATA_WIDTH(8), + .CLK_FREQ_HZ(100_000_000), + .BAUDRATE(10_000_000) + ) tb_decoder ( + .clk(clk), + .rst(rst), + .rxd(utx_tb_txd), + + .axiod(), + .axiov()); + + always begin + #`HCP + clk = !clk; + end + + initial begin + $dumpfile("minimal_bus.vcd"); + $dumpvars(0, minimal_bus_tb); + + // setup and reset + clk = 0; + rst = 0; + tb_urx_rxd = 1; + test_num = 0; + #`CP + rst = 1; + #`CP + rst = 0; + #`HCP + + // throw some nonzero data in the memories just so we know that we're pulling from the right ones + mem.mem[0] = 16'h0000; + mem.mem[1] = 16'h0001; + mem.mem[2] = 16'h0002; + mem.mem[3] = 16'h0003; + mem.mem[4] = 16'h0004; + mem.mem[5] = 16'h0005; + mem.mem[6] = 16'h0006; + mem.mem[7] = 16'h0007; + + #(10*`CP); + + /* ==== Test 1 Begin ==== */ + $display("\n=== test 1: write 0x5678 to 0x1234 for baseline functionality ==="); + test_num = 1; + msg = {"M1234", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + #(10*`CP); + /* ==== Test 1 End ==== */ + + /* ==== Test 2 Begin ==== */ + $display("\n=== test 2: read from 0x0001 for baseline functionality ==="); + test_num = 2; + msg = {"M1234", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + #(1000*`CP); + /* ==== Test 2 End ==== */ + + /* ==== Test 3 Begin ==== */ + $display("\n=== test 3: read from 0x0000-0x0007 for baseline functionality ==="); + test_num = 3; + msg = {"M0000", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + msg = {"M0001", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + msg = {"M0002", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + msg = {"M0003", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + msg = {"M0004", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + msg = {"M0005", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + msg = {"M0006", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + msg = {"M0007", 8'h0D, 8'h0A}; + `SEND_MSG_BITS(msg) + + #(10*`CP); + /* ==== Test 3 End ==== */ + + + #(1000*`CP) + + $finish(); + end +endmodule + +`default_nettype wire \ No newline at end of file