From 70154f690414026a0bce4c7901f467bde6e4262d Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Tue, 28 Feb 2023 21:07:02 -0500
Subject: [PATCH] add uart_rx module, bus seems to be working end-to-end

---
 test/bus.gtkw  | 55 +++++++++++++++++++++++++++++++--------------
 test/bus_tb.sv | 60 ++++++++++++++++++++++++++++++++------------------
 2 files changed, 78 insertions(+), 37 deletions(-)

diff --git a/test/bus.gtkw b/test/bus.gtkw
index cc8211a..dfb01bb 100644
--- a/test/bus.gtkw
+++ b/test/bus.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
-[*] Tue Feb 28 23:56:47 2023
+[*] Wed Mar  1 02:04:43 2023
 [*]
 [dumpfile] "/Users/fischerm/fpga/manta/bus.vcd"
-[dumpfile_mtime] "Tue Feb 28 23:52:25 2023"
-[dumpfile_size] 6844
+[dumpfile_mtime] "Wed Mar  1 02:00:40 2023"
+[dumpfile_size] 91134
 [savefile] "/Users/fischerm/fpga/manta/bus.gtkw"
-[timestart] 18600000000000
+[timestart] 0
 [size] 1710 994
 [pos] -1 -1
-*-46.201744 327700000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-21.981709 8420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] bus_tb.
 [sst_width] 353
 [signals_width] 276
@@ -23,11 +23,19 @@ bus_tb.test_num
 @200
 -
 -
--tb --> bridge_rx
-@820
-bus_tb.tb_brx_axid[7:0]
+-tb --> uart_rx
 @28
-bus_tb.tb_brx_axiv
+bus_tb.tb_urx_rxd
+@200
+-
+-
+-uart_rx --> bridge_rx
+@820
+bus_tb.urx_brx_axid[7:0]
+@28
+bus_tb.urx_brx_axiv
+@22
+bus_tb.urx.bit_index[4:0]
 @200
 -
 -
@@ -65,14 +73,29 @@ bus_tb.mem_2_mem_3_wdata[15:0]
 @200
 -
 -
--mem_3 --> tb
+-mem_3 --> bridge_tx
 @22
-bus_tb.mem_3_tb_addr[15:0]
-bus_tb.mem_3_tb_rdata[15:0]
-@23
-bus_tb.mem_3_tb_wdata[15:0]
+bus_tb.mem_3_btx_addr[15:0]
+bus_tb.mem_3_btx_rdata[15:0]
 @28
-bus_tb.mem_3_tb_rw
-bus_tb.mem_3_tb_valid
+bus_tb.mem_3_btx_rw
+bus_tb.mem_3_btx_valid
+@22
+bus_tb.mem_3_btx_wdata[15:0]
+@200
+-
+-
+-bridge_tx --> uart_tx
+@23
+bus_tb.btx_utx_axid[7:0]
+@28
+bus_tb.btx_utx_axir
+bus_tb.btx_utx_axiv
+@200
+-
+-
+-uart_tx --> tb
+@28
+bus_tb.utx_tb_txd
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/test/bus_tb.sv b/test/bus_tb.sv
index 51f761a..6eb746c 100644
--- a/test/bus_tb.sv
+++ b/test/bus_tb.sv
@@ -1,15 +1,19 @@
 `default_nettype none
+`timescale 1ns/1ps
 
 `define CP 10
 `define HCP 5
 
-`define SEND_MESSAGE(MESSAGE) \
-   tb_brx_axiv = 1; \
-    for(int i=0; i < $size(MESSAGE); i++) begin \
-        tb_brx_axid = MESSAGE[i]; \
-        #`CP; \
-    end \
-    tb_brx_axiv = 0; \
+`define SEND_MSG_BITS(MSG) \
+    for(int j=0; j < $size(msg); j++) begin                 \
+        char = msg[j];                                      \
+        for(int i=0; i < 10; i++) begin                     \
+            if (i == 0) tb_urx_rxd = 0;                            \
+            else if ((i > 0) & (i < 9)) tb_urx_rxd = char[i-1];    \
+            else if (i == 9) tb_urx_rxd = 1;                       \
+            #(10*`CP);                                         \
+        end                                                 \
+    end                                                     \
 
 module bus_tb;
     // https://www.youtube.com/watch?v=WCOAr-96bGc
@@ -18,21 +22,36 @@ module bus_tb;
     logic clk;
     logic rst;
     integer test_num;
-    string message;
+    string msg;
+    logic [7:0] char;
 
-    // tb --> bridge_rx signals
-    logic [7:0] tb_brx_axid;
-    logic tb_brx_axiv;
+    // tb --> uart_rx signals
+    logic tb_urx_rxd;
+    uart_rx #(
+        .DATA_WIDTH(8),
+        .CLK_FREQ_HZ(100_000_000),
+        .BAUDRATE(10_000_000)
+    ) urx (
+        .clk(clk),
+        .rst(rst),
+        .rxd(tb_urx_rxd),
+
+        .axiod(urx_brx_axid),
+        .axiov(urx_brx_axiv));
+
+    // uart_rx --> bridge_rx signals
+    logic [7:0] urx_brx_axid;
+    logic urx_brx_axiv;
 
     bridge_rx brx (
         .clk(clk),
-        .axiid(tb_brx_axid),
-        .axiiv(tb_brx_axiv),
+        .axiid(urx_brx_axid),
+        .axiiv(urx_brx_axiv),
         .req_addr(brx_mem_1_addr),
         .req_data(brx_mem_1_wdata),
         .req_rw(brx_mem_1_rw),
         .req_valid(brx_mem_1_valid),
-        .req_ready(1'b1)); 
+        .req_ready(1'b1));
 
     // bridge_rx --> mem_1 signals
     logic [15:0] brx_mem_1_addr;
@@ -67,7 +86,7 @@ module bus_tb;
     logic mem_1_mem_2_rw;
     logic mem_1_mem_2_valid;
 
-    lut_mem #( 
+    lut_mem #(
         .DEPTH(8),
         .BASE_ADDR(8)
     ) mem_2 (
@@ -114,7 +133,7 @@ module bus_tb;
     logic [15:0] mem_3_btx_rdata;
     logic mem_3_btx_rw;
     logic mem_3_btx_valid;
-    
+
     bridge_tx btx (
         .clk(clk),
         .axiod(btx_utx_axid),
@@ -158,8 +177,7 @@ module bus_tb;
         // setup and reset
         clk = 0;
         rst = 0;
-        tb_brx_axid = 0;
-        tb_brx_axiv = 0;
+        tb_urx_rxd = 1;
         test_num = 0;
         #`CP
         rst = 1;
@@ -203,11 +221,11 @@ module bus_tb;
         #(10*`CP);
         /* ==== Test 1 End ==== */
 
-        message = {"M12345678", 8'h0D, 8'h0A};
-        `SEND_MESSAGE(message)
+        msg = {"M12345678", 8'h0D, 8'h0A};
+        `SEND_MSG_BITS(msg)
 
         #(1000*`CP)
-        
+
         $finish();
     end
 endmodule