From 6b426306beaa2721c00e404e534319b3cdd6c17e Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Sat, 7 Sep 2024 15:06:35 -0600
Subject: [PATCH] doc: reference use cases/examples in index.md

---
 doc/index.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/doc/index.md b/doc/index.md
index 0da5123..c73bfc7 100644
--- a/doc/index.md
+++ b/doc/index.md
@@ -6,6 +6,8 @@ Manta is a tool for rapidly prototyping and debugging FPGA designs. It works by
 
 These cores include functionality such as register reads/writes, memory accesses, and an embedded logic analyzer. Manta includes both a UART and Ethernet (via UDP) interface for communication between the host and FPGA.
 
+For more information on how Manta can be used, please refer to the [Use Cases](../use_cases) page and the repository's [examples](https://github.com/fischermoseley/manta/tree/main/examples) folder.
+
 Manta specifies its RTL logic with [Amaranth](https://github.com/amaranth-lang/amaranth) which allows it to target nearly any FPGA device, regardless of vendor. Manta itself is written in pure Python, which allows it to run on Windows, macOS, Linux, and BSD across a variety of CPU architectures. Manta can be included natively in Amaranth-based designs, or export Verilog-2001 for use in traditional Verilog-based workflows.
 
 ## About