From 66a1a2d6eb2d11d8ad00f85c66f96c3a43137cd9 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Mon, 9 Sep 2024 19:27:29 -0700
Subject: [PATCH] logic_analyzer: only set triggers if extra info provided in
 config

---
 .../icestick/uart_logic_analyzer/manta.yaml      |  1 +
 .../ether_logic_analyzer_io_core/manta.yaml      |  1 +
 .../nexys4_ddr/uart_logic_analyzer/manta.yaml    |  1 +
 src/manta/logic_analyzer/__init__.py             | 16 ++++++++++------
 4 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/examples/verilog/icestick/uart_logic_analyzer/manta.yaml b/examples/verilog/icestick/uart_logic_analyzer/manta.yaml
index 4a83724..a6be86c 100644
--- a/examples/verilog/icestick/uart_logic_analyzer/manta.yaml
+++ b/examples/verilog/icestick/uart_logic_analyzer/manta.yaml
@@ -3,6 +3,7 @@ cores:
   my_logic_analyzer:
     type: logic_analyzer
     sample_depth: 2048
+    trigger_mode: single_shot
 
     probes:
       probe0: 1
diff --git a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml
index 8dd1036..8b413a2 100644
--- a/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml
+++ b/examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/manta.yaml
@@ -3,6 +3,7 @@ cores:
   my_logic_analyzer:
     type: logic_analyzer
     sample_depth: 8192
+    trigger_mode: single_shot
 
     probes:
       probe0: 1
diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml b/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml
index 6502705..908e47f 100644
--- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml
+++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml
@@ -3,6 +3,7 @@ cores:
   my_logic_analyzer:
     type: logic_analyzer
     sample_depth: 256
+    trigger_mode: single_shot
 
     probes:
       probe0: 1
diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py
index 9ac027e..b566421 100644
--- a/src/manta/logic_analyzer/__init__.py
+++ b/src/manta/logic_analyzer/__init__.py
@@ -113,13 +113,17 @@ class LogicAnalyzerCore(MantaCore):
 
         # Checks and formatting complete, create LogicAnalyzerCore
         probes = [Signal(width, name=name) for name, width in config["probes"].items()]
-
         core = cls(sample_depth, probes)
-        core.set_triggers(
-            trigger_mode=config.get("trigger_mode"),
-            triggers=triggers,
-            trigger_location=config.get("trigger_location"),
-        )
+
+        # If any trigger-related configuration was provided, set the triggers with it
+        keys = ["trigger_mode", "triggers", "trigger_location"]
+        if any([key in config for key in keys]):
+            core.set_triggers(
+                trigger_mode=config.get("trigger_mode"),
+                triggers=triggers,
+                trigger_location=config.get("trigger_location"),
+            )
+
         return core
 
     def define_submodules(self):