From 62049bac84ffbf7c083cd99b8ffb56954eafa6e5 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Mon, 19 Jan 2026 16:31:12 -0700 Subject: [PATCH] meta: replace Signal(1) with Signal() --- examples/amaranth/uart_logic_analyzer.py | 2 +- src/manta/logic_analyzer/fsm.py | 4 ++-- src/manta/logic_analyzer/playback.py | 6 +++--- src/manta/uart/receive_bridge.py | 4 ++-- src/manta/uart/receiver.py | 2 +- src/manta/uart/transmit_bridge.py | 4 ++-- test/test_config_export.py | 4 ++-- test/test_io_core_sim.py | 2 +- test/test_logic_analyzer_sim.py | 2 +- 9 files changed, 15 insertions(+), 15 deletions(-) diff --git a/examples/amaranth/uart_logic_analyzer.py b/examples/amaranth/uart_logic_analyzer.py index f9f9dd1..122d15a 100644 --- a/examples/amaranth/uart_logic_analyzer.py +++ b/examples/amaranth/uart_logic_analyzer.py @@ -20,7 +20,7 @@ class UARTLogicAnalyzerExample(Elaboratable): clock_freq=platform.default_clk_frequency, ) - self.probe0 = Signal(1) + self.probe0 = Signal() self.probe1 = Signal(2) self.probe2 = Signal(3) self.probe3 = Signal(4) diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index b22560c..35135f9 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -31,8 +31,8 @@ class LogicAnalyzerFSM(Elaboratable): self._sample_depth = sample_depth # Outputs to rest of Logic Analyzer - self.trigger = Signal(1) - self.write_enable = Signal(1) + self.trigger = Signal() + self.write_enable = Signal() # Outputs from FSM, inputs from IOCore self.state = Signal(States) diff --git a/src/manta/logic_analyzer/playback.py b/src/manta/logic_analyzer/playback.py index 9392a50..29894dc 100644 --- a/src/manta/logic_analyzer/playback.py +++ b/src/manta/logic_analyzer/playback.py @@ -13,8 +13,8 @@ class LogicAnalyzerPlayback(Elaboratable): self._data = data # State Machine - self.start = Signal(1) - self.valid = Signal(1) + self.start = Signal() + self.valid = Signal() def elaborate(self, platform): m = Module() @@ -32,7 +32,7 @@ class LogicAnalyzerPlayback(Elaboratable): m.d.comb += read_port.en.eq(1) # State Machine - busy = Signal(1) + busy = Signal() with m.If(~busy): with m.If(self.start): m.d.sync += busy.eq(1) diff --git a/src/manta/uart/receive_bridge.py b/src/manta/uart/receive_bridge.py index f0b8187..c15c9f5 100644 --- a/src/manta/uart/receive_bridge.py +++ b/src/manta/uart/receive_bridge.py @@ -22,8 +22,8 @@ class ReceiveBridge(Elaboratable): self.addr_o = Signal(16) self.data_o = Signal(16) - self.rw_o = Signal(1) - self.valid_o = Signal(1) + self.rw_o = Signal() + self.valid_o = Signal() # Internal Signals self._buffer = Signal(ArrayLayout(4, 8)) diff --git a/src/manta/uart/receiver.py b/src/manta/uart/receiver.py index 2fe65df..faadb48 100644 --- a/src/manta/uart/receiver.py +++ b/src/manta/uart/receiver.py @@ -13,7 +13,7 @@ class UARTReceiver(Elaboratable): # Top-Level Ports self.rx = Signal() self.data_o = Signal(8) - self.valid_o = Signal(1) + self.valid_o = Signal() # Internal Signals self._busy = Signal() diff --git a/src/manta/uart/transmit_bridge.py b/src/manta/uart/transmit_bridge.py index abb1c82..f7f51c4 100644 --- a/src/manta/uart/transmit_bridge.py +++ b/src/manta/uart/transmit_bridge.py @@ -14,13 +14,13 @@ class TransmitBridge(Elaboratable): self.valid_i = Signal() self.data_o = Signal(8) - self.start_o = Signal(1) + self.start_o = Signal() self.done_i = Signal() # Internal Signals self._buffer = Signal(16) self._count = Signal(4) - self._busy = Signal(1) + self._busy = Signal() self._to_ascii_hex = Signal(8) self._n = Signal(4) diff --git a/test/test_config_export.py b/test/test_config_export.py index edeff62..85ceb39 100644 --- a/test/test_config_export.py +++ b/test/test_config_export.py @@ -8,7 +8,7 @@ from manta import * def test_io_core_dump(): # Create some dummy signals to pass to the IO Core - probe0 = Signal(1) + probe0 = Signal() probe1 = Signal(2) probe2 = Signal(3) probe3 = Signal(4, init=13) @@ -84,7 +84,7 @@ def test_memory_core_dump(): def test_logic_analyzer_core_dump(): # Create some dummy signals to pass to the Logic Analyzer - probe0 = Signal(1) + probe0 = Signal() probe1 = Signal(2) probe2 = Signal(3) diff --git a/test/test_io_core_sim.py b/test/test_io_core_sim.py index e270efd..84b5175 100644 --- a/test/test_io_core_sim.py +++ b/test/test_io_core_sim.py @@ -5,7 +5,7 @@ from amaranth import * from manta import * from manta.utils import * -probe0 = Signal(1) +probe0 = Signal() probe1 = Signal(2) probe2 = Signal(8) probe3 = Signal(20) diff --git a/test/test_logic_analyzer_sim.py b/test/test_logic_analyzer_sim.py index 010525d..f4bed0d 100644 --- a/test/test_logic_analyzer_sim.py +++ b/test/test_logic_analyzer_sim.py @@ -4,7 +4,7 @@ from manta.logic_analyzer import LogicAnalyzerCore from manta.logic_analyzer.trigger_block import Operations from manta.utils import * -larry = Signal(1) +larry = Signal() curly = Signal(3) moe = Signal(9)