diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py
index 375bc04..0219420 100644
--- a/src/manta/ethernet/__init__.py
+++ b/src/manta/ethernet/__init__.py
@@ -70,8 +70,8 @@ class EthernetInterface(Elaboratable):
         self._additional_config = kwargs
         self._check_config()
 
-        self.bus_i = Signal(InternalBus())
-        self.bus_o = Signal(InternalBus())
+        self.bus_i = Signal(InternalBusLayout)
+        self.bus_o = Signal(InternalBusLayout)
 
         # Define PHY IO, assuming that we're in a Verilog-based workflow.
         self._define_phy_io(self._phy)
diff --git a/src/manta/io_core.py b/src/manta/io_core.py
index 6bb3895..0fa416a 100644
--- a/src/manta/io_core.py
+++ b/src/manta/io_core.py
@@ -34,8 +34,8 @@ class IOCore(MantaCore):
         self._outputs = outputs
 
         # Bus Connections
-        self.bus_i = Signal(InternalBus())
-        self.bus_o = Signal(InternalBus())
+        self.bus_i = Signal(InternalBusLayout)
+        self.bus_o = Signal(InternalBusLayout)
 
         # Internal Signals
         self._strobe = Signal()
diff --git a/src/manta/logic_analyzer/__init__.py b/src/manta/logic_analyzer/__init__.py
index c78a9d2..82b5ddf 100644
--- a/src/manta/logic_analyzer/__init__.py
+++ b/src/manta/logic_analyzer/__init__.py
@@ -41,8 +41,8 @@ class LogicAnalyzerCore(MantaCore):
         self._triggers = []
 
         # Bus Input/Output
-        self.bus_i = Signal(InternalBus())
-        self.bus_o = Signal(InternalBus())
+        self.bus_i = Signal(InternalBusLayout)
+        self.bus_o = Signal(InternalBusLayout)
 
     @property
     def max_addr(self):